Read the interrupt status only once, to prevent wrong status reads in the
iwn_intr function. This should fix firmware timeouts, which occure due to the second read just returns wrong values. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@34804 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
@@ -275,7 +275,7 @@ iwn_attach(device_t dev)
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RF_ACTIVE);
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RF_ACTIVE);
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if (sc->mem == NULL ) {
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if (sc->mem == NULL ) {
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device_printf(dev, "could not allocate memory resources\n");
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device_printf(dev, "could not allocate memory resources\n");
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error = ENOMEM;
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error = ENOMEM;
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return error;
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return error;
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}
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}
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@@ -366,7 +366,7 @@ iwn_attach(device_t dev)
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}
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}
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ic = ifp->if_l2com;
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ic = ifp->if_l2com;
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ic->ic_ifp = ifp;
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ic->ic_ifp = ifp;
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ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
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ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
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ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
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ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
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@@ -582,7 +582,7 @@ iwn_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
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*(bus_addr_t *)arg = segs[0].ds_addr;
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*(bus_addr_t *)arg = segs[0].ds_addr;
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}
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}
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static int
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static int
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iwn_dma_contig_alloc(struct iwn_softc *sc, struct iwn_dma_info *dma,
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iwn_dma_contig_alloc(struct iwn_softc *sc, struct iwn_dma_info *dma,
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void **kvap, bus_size_t size, bus_size_t alignment, int flags)
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void **kvap, bus_size_t size, bus_size_t alignment, int flags)
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{
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{
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@@ -732,7 +732,7 @@ iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring)
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goto fail;
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goto fail;
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}
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}
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error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
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error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
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BUS_SPACE_MAXADDR_32BIT,
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BUS_SPACE_MAXADDR_32BIT,
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BUS_SPACE_MAXADDR, NULL, NULL, MJUMPAGESIZE, 1,
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BUS_SPACE_MAXADDR, NULL, NULL, MJUMPAGESIZE, 1,
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MJUMPAGESIZE, BUS_DMA_NOWAIT, NULL, NULL, &ring->data_dmat);
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MJUMPAGESIZE, BUS_DMA_NOWAIT, NULL, NULL, &ring->data_dmat);
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@@ -777,7 +777,7 @@ iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring)
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error = ENOMEM; /* XXX unique code */
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error = ENOMEM; /* XXX unique code */
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goto fail;
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goto fail;
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}
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}
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bus_dmamap_sync(ring->data_dmat, data->map,
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bus_dmamap_sync(ring->data_dmat, data->map,
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BUS_DMASYNC_PREWRITE);
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BUS_DMASYNC_PREWRITE);
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data->m = m;
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data->m = m;
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@@ -856,7 +856,7 @@ iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid)
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goto fail;
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goto fail;
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}
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}
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error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
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error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
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BUS_SPACE_MAXADDR_32BIT,
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BUS_SPACE_MAXADDR_32BIT,
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BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, IWN_MAX_SCATTER - 1,
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BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, IWN_MAX_SCATTER - 1,
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MCLBYTES, BUS_DMA_NOWAIT, NULL, NULL, &ring->data_dmat);
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MCLBYTES, BUS_DMA_NOWAIT, NULL, NULL, &ring->data_dmat);
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@@ -877,7 +877,7 @@ iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid)
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__func__, error);
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__func__, error);
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goto fail;
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goto fail;
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}
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}
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bus_dmamap_sync(ring->data_dmat, data->map,
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bus_dmamap_sync(ring->data_dmat, data->map,
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BUS_DMASYNC_PREWRITE);
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BUS_DMASYNC_PREWRITE);
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}
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}
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return 0;
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return 0;
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@@ -1099,7 +1099,7 @@ iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int len)
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iwn_mem_lock(sc);
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iwn_mem_lock(sc);
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for (; len > 0; len -= 2, addr++) {
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for (; len > 0; len -= 2, addr++) {
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IWN_WRITE(sc, IWN_EEPROM_CTL, addr << 2);
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IWN_WRITE(sc, IWN_EEPROM_CTL, addr << 2);
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tmp = IWN_READ(sc, IWN_EEPROM_CTL);
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tmp = IWN_READ(sc, IWN_EEPROM_CTL);
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IWN_WRITE(sc, IWN_EEPROM_CTL, tmp & ~IWN_EEPROM_MSK );
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IWN_WRITE(sc, IWN_EEPROM_CTL, tmp & ~IWN_EEPROM_MSK );
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for (ntries = 0; ntries < 10; ntries++) {
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for (ntries = 0; ntries < 10; ntries++) {
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@@ -1808,6 +1808,7 @@ iwn_intr(void *arg)
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IWN_LOCK(sc);
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IWN_LOCK(sc);
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#if !defined(__HAIKU__)
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/* disable interrupts */
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/* disable interrupts */
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IWN_WRITE(sc, IWN_MASK, 0);
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IWN_WRITE(sc, IWN_MASK, 0);
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@@ -1821,6 +1822,10 @@ iwn_intr(void *arg)
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if (r1 == 0xffffffff)
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if (r1 == 0xffffffff)
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goto done; /* hardware gone */
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goto done; /* hardware gone */
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#else
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r1 = atomic_and((int32*)&sc->sc_intr_status_1, 0);
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r2 = atomic_and((int32*)&sc->sc_intr_status_2, 0);
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#endif
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/* ack interrupts */
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/* ack interrupts */
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IWN_WRITE(sc, IWN_INTR, r1);
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IWN_WRITE(sc, IWN_INTR, r1);
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@@ -2928,7 +2933,7 @@ iwn_power_calibration(struct iwn_softc *sc, int temp)
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DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d->%d\n",
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DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d->%d\n",
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__func__, sc->temp, temp);
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__func__, sc->temp, temp);
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/* adjust Tx power if need be (delta >= 3°C) */
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/* adjust Tx power if need be (delta >= 3�C) */
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if (abs(temp - sc->temp) < 3)
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if (abs(temp - sc->temp) < 3)
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return;
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return;
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@@ -3443,7 +3448,7 @@ iwn_send_sensitivity(struct iwn_softc *sc)
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cmd.corr_barker = htole16(190);
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cmd.corr_barker = htole16(190);
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cmd.corr_barker_mrc = htole16(390);
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cmd.corr_barker_mrc = htole16(390);
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DPRINTF(sc, IWN_DEBUG_RESET,
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DPRINTF(sc, IWN_DEBUG_RESET,
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"%s: set sensitivity %d/%d/%d/%d/%d/%d/%d\n", __func__,
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"%s: set sensitivity %d/%d/%d/%d/%d/%d/%d\n", __func__,
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calib->corr_ofdm_x1, calib->corr_ofdm_mrc_x1, calib->corr_ofdm_x4,
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calib->corr_ofdm_x1, calib->corr_ofdm_mrc_x1, calib->corr_ofdm_x4,
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calib->corr_ofdm_mrc_x4, calib->corr_cck_x4,
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calib->corr_ofdm_mrc_x4, calib->corr_cck_x4,
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@@ -200,6 +200,11 @@ struct iwn_softc {
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int16_t eeprom_voltage;
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int16_t eeprom_voltage;
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int8_t maxpwr2GHz;
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int8_t maxpwr2GHz;
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int8_t maxpwr5GHz;
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int8_t maxpwr5GHz;
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#if defined(__HAIKU__)
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uint32_t sc_intr_status_1;
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uint32_t sc_intr_status_2;
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#endif
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};
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};
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#define IWN_LOCK_INIT(_sc) \
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#define IWN_LOCK_INIT(_sc) \
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@@ -30,30 +30,27 @@ HAIKU_CHECK_DISABLE_INTERRUPTS(device_t dev)
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{
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{
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struct iwn_softc* sc = (struct iwn_softc*)device_get_softc(dev);
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struct iwn_softc* sc = (struct iwn_softc*)device_get_softc(dev);
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uint32 r1, r2;
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uint32 r1, r2;
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HAIKU_INTR_REGISTER_STATE;
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HAIKU_INTR_REGISTER_ENTER();
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r1 = IWN_READ(sc, IWN_INTR);
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r1 = IWN_READ(sc, IWN_INTR);
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r2 = IWN_READ(sc, IWN_INTR_STATUS);
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r2 = IWN_READ(sc, IWN_INTR_STATUS);
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if (r1 == 0 && r2 == 0) {
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if (r1 == 0 && r2 == 0) {
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/* not for us */
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/* not for us */
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IWN_WRITE(sc, IWN_MASK, IWN_INTR_MASK);
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IWN_WRITE(sc, IWN_MASK, IWN_INTR_MASK);
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HAIKU_INTR_REGISTER_LEAVE();
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return 0;
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return 0;
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}
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}
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if (r1 == 0xffffffff) {
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if (r1 == 0xffffffff) {
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/* hardware gone */
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/* hardware gone */
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HAIKU_INTR_REGISTER_LEAVE();
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return 0;
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return 0;
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}
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}
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atomic_or((int32*)&sc->sc_intr_status_1, r1);
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atomic_or((int32*)&sc->sc_intr_status_2, r2);
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/* disable interrupts */
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/* disable interrupts */
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IWN_WRITE(sc, IWN_MASK, 0);
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IWN_WRITE(sc, IWN_MASK, 0);
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HAIKU_INTR_REGISTER_LEAVE();
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return 1;
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return 1;
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}
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}
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