Read the interrupt status only once, to prevent wrong status reads in the

iwn_intr function. This should fix firmware timeouts, which occure due to
the second read just returns wrong values.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@34804 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Colin Günther
2009-12-29 17:40:59 +00:00
parent ca833f9f1b
commit 92ba12f110
3 changed files with 23 additions and 16 deletions
@@ -275,7 +275,7 @@ iwn_attach(device_t dev)
RF_ACTIVE); RF_ACTIVE);
if (sc->mem == NULL ) { if (sc->mem == NULL ) {
device_printf(dev, "could not allocate memory resources\n"); device_printf(dev, "could not allocate memory resources\n");
error = ENOMEM; error = ENOMEM;
return error; return error;
} }
@@ -366,7 +366,7 @@ iwn_attach(device_t dev)
} }
ic = ifp->if_l2com; ic = ifp->if_l2com;
ic->ic_ifp = ifp; ic->ic_ifp = ifp;
ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */
ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */ ic->ic_opmode = IEEE80211_M_STA; /* default to BSS mode */
@@ -582,7 +582,7 @@ iwn_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nsegs, int error)
*(bus_addr_t *)arg = segs[0].ds_addr; *(bus_addr_t *)arg = segs[0].ds_addr;
} }
static int static int
iwn_dma_contig_alloc(struct iwn_softc *sc, struct iwn_dma_info *dma, iwn_dma_contig_alloc(struct iwn_softc *sc, struct iwn_dma_info *dma,
void **kvap, bus_size_t size, bus_size_t alignment, int flags) void **kvap, bus_size_t size, bus_size_t alignment, int flags)
{ {
@@ -732,7 +732,7 @@ iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring)
goto fail; goto fail;
} }
error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR_32BIT,
BUS_SPACE_MAXADDR, NULL, NULL, MJUMPAGESIZE, 1, BUS_SPACE_MAXADDR, NULL, NULL, MJUMPAGESIZE, 1,
MJUMPAGESIZE, BUS_DMA_NOWAIT, NULL, NULL, &ring->data_dmat); MJUMPAGESIZE, BUS_DMA_NOWAIT, NULL, NULL, &ring->data_dmat);
@@ -777,7 +777,7 @@ iwn_alloc_rx_ring(struct iwn_softc *sc, struct iwn_rx_ring *ring)
error = ENOMEM; /* XXX unique code */ error = ENOMEM; /* XXX unique code */
goto fail; goto fail;
} }
bus_dmamap_sync(ring->data_dmat, data->map, bus_dmamap_sync(ring->data_dmat, data->map,
BUS_DMASYNC_PREWRITE); BUS_DMASYNC_PREWRITE);
data->m = m; data->m = m;
@@ -856,7 +856,7 @@ iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid)
goto fail; goto fail;
} }
error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0,
BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR_32BIT,
BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, IWN_MAX_SCATTER - 1, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, IWN_MAX_SCATTER - 1,
MCLBYTES, BUS_DMA_NOWAIT, NULL, NULL, &ring->data_dmat); MCLBYTES, BUS_DMA_NOWAIT, NULL, NULL, &ring->data_dmat);
@@ -877,7 +877,7 @@ iwn_alloc_tx_ring(struct iwn_softc *sc, struct iwn_tx_ring *ring, int qid)
__func__, error); __func__, error);
goto fail; goto fail;
} }
bus_dmamap_sync(ring->data_dmat, data->map, bus_dmamap_sync(ring->data_dmat, data->map,
BUS_DMASYNC_PREWRITE); BUS_DMASYNC_PREWRITE);
} }
return 0; return 0;
@@ -1099,7 +1099,7 @@ iwn_read_prom_data(struct iwn_softc *sc, uint32_t addr, void *data, int len)
iwn_mem_lock(sc); iwn_mem_lock(sc);
for (; len > 0; len -= 2, addr++) { for (; len > 0; len -= 2, addr++) {
IWN_WRITE(sc, IWN_EEPROM_CTL, addr << 2); IWN_WRITE(sc, IWN_EEPROM_CTL, addr << 2);
tmp = IWN_READ(sc, IWN_EEPROM_CTL); tmp = IWN_READ(sc, IWN_EEPROM_CTL);
IWN_WRITE(sc, IWN_EEPROM_CTL, tmp & ~IWN_EEPROM_MSK ); IWN_WRITE(sc, IWN_EEPROM_CTL, tmp & ~IWN_EEPROM_MSK );
for (ntries = 0; ntries < 10; ntries++) { for (ntries = 0; ntries < 10; ntries++) {
@@ -1808,6 +1808,7 @@ iwn_intr(void *arg)
IWN_LOCK(sc); IWN_LOCK(sc);
#if !defined(__HAIKU__)
/* disable interrupts */ /* disable interrupts */
IWN_WRITE(sc, IWN_MASK, 0); IWN_WRITE(sc, IWN_MASK, 0);
@@ -1821,6 +1822,10 @@ iwn_intr(void *arg)
if (r1 == 0xffffffff) if (r1 == 0xffffffff)
goto done; /* hardware gone */ goto done; /* hardware gone */
#else
r1 = atomic_and((int32*)&sc->sc_intr_status_1, 0);
r2 = atomic_and((int32*)&sc->sc_intr_status_2, 0);
#endif
/* ack interrupts */ /* ack interrupts */
IWN_WRITE(sc, IWN_INTR, r1); IWN_WRITE(sc, IWN_INTR, r1);
@@ -2928,7 +2933,7 @@ iwn_power_calibration(struct iwn_softc *sc, int temp)
DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d->%d\n", DPRINTF(sc, IWN_DEBUG_CALIBRATE, "%s: temperature %d->%d\n",
__func__, sc->temp, temp); __func__, sc->temp, temp);
/* adjust Tx power if need be (delta >= 3°C) */ /* adjust Tx power if need be (delta >= 3C) */
if (abs(temp - sc->temp) < 3) if (abs(temp - sc->temp) < 3)
return; return;
@@ -3443,7 +3448,7 @@ iwn_send_sensitivity(struct iwn_softc *sc)
cmd.corr_barker = htole16(190); cmd.corr_barker = htole16(190);
cmd.corr_barker_mrc = htole16(390); cmd.corr_barker_mrc = htole16(390);
DPRINTF(sc, IWN_DEBUG_RESET, DPRINTF(sc, IWN_DEBUG_RESET,
"%s: set sensitivity %d/%d/%d/%d/%d/%d/%d\n", __func__, "%s: set sensitivity %d/%d/%d/%d/%d/%d/%d\n", __func__,
calib->corr_ofdm_x1, calib->corr_ofdm_mrc_x1, calib->corr_ofdm_x4, calib->corr_ofdm_x1, calib->corr_ofdm_mrc_x1, calib->corr_ofdm_x4,
calib->corr_ofdm_mrc_x4, calib->corr_cck_x4, calib->corr_ofdm_mrc_x4, calib->corr_cck_x4,
@@ -200,6 +200,11 @@ struct iwn_softc {
int16_t eeprom_voltage; int16_t eeprom_voltage;
int8_t maxpwr2GHz; int8_t maxpwr2GHz;
int8_t maxpwr5GHz; int8_t maxpwr5GHz;
#if defined(__HAIKU__)
uint32_t sc_intr_status_1;
uint32_t sc_intr_status_2;
#endif
}; };
#define IWN_LOCK_INIT(_sc) \ #define IWN_LOCK_INIT(_sc) \
@@ -30,30 +30,27 @@ HAIKU_CHECK_DISABLE_INTERRUPTS(device_t dev)
{ {
struct iwn_softc* sc = (struct iwn_softc*)device_get_softc(dev); struct iwn_softc* sc = (struct iwn_softc*)device_get_softc(dev);
uint32 r1, r2; uint32 r1, r2;
HAIKU_INTR_REGISTER_STATE;
HAIKU_INTR_REGISTER_ENTER();
r1 = IWN_READ(sc, IWN_INTR); r1 = IWN_READ(sc, IWN_INTR);
r2 = IWN_READ(sc, IWN_INTR_STATUS); r2 = IWN_READ(sc, IWN_INTR_STATUS);
if (r1 == 0 && r2 == 0) { if (r1 == 0 && r2 == 0) {
/* not for us */ /* not for us */
IWN_WRITE(sc, IWN_MASK, IWN_INTR_MASK); IWN_WRITE(sc, IWN_MASK, IWN_INTR_MASK);
HAIKU_INTR_REGISTER_LEAVE();
return 0; return 0;
} }
if (r1 == 0xffffffff) { if (r1 == 0xffffffff) {
/* hardware gone */ /* hardware gone */
HAIKU_INTR_REGISTER_LEAVE();
return 0; return 0;
} }
atomic_or((int32*)&sc->sc_intr_status_1, r1);
atomic_or((int32*)&sc->sc_intr_status_2, r2);
/* disable interrupts */ /* disable interrupts */
IWN_WRITE(sc, IWN_MASK, 0); IWN_WRITE(sc, IWN_MASK, 0);
HAIKU_INTR_REGISTER_LEAVE();
return 1; return 1;
} }