From 932b55644f1fcbe6055796a5cfb3d6d397437e28 Mon Sep 17 00:00:00 2001 From: Owen Anderson Date: Tue, 20 Aug 2024 22:15:20 +0000 Subject: [PATCH] arm64/uefi: Perform MMU maintenance when TBBR1_EL1 is enabled. * Cache & TLB maintenance need to be performed when TBBR1_EL1 is enabled, not when it is setup. * Boots all the way into the kernel (and dies in the kernel debugger) on M1 Max hardware under virtualization. * Add more details comments on the reasoning behind the process. Change-Id: Ib4b5aa3bbae71d69169575c06c7cd75d616307d9 Reviewed-on: https://review.haiku-os.org/c/haiku/+/8084 Haiku-Format: Haiku-format Bot Reviewed-by: Fredrik Holmqvist Reviewed-by: David Karoly Tested-by: Commit checker robot --- src/system/boot/platform/efi/arch/arm64/arch_mmu.cpp | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-) diff --git a/src/system/boot/platform/efi/arch/arm64/arch_mmu.cpp b/src/system/boot/platform/efi/arch/arm64/arch_mmu.cpp index a98e8b4bc8..043ad08c0e 100644 --- a/src/system/boot/platform/efi/arch/arm64/arch_mmu.cpp +++ b/src/system/boot/platform/efi/arch/arm64/arch_mmu.cpp @@ -122,7 +122,14 @@ void arch_mmu_setup_EL1(uint64 tcr) { // TODO: Compiler dependency? tcr |= TCR_T1SZ(__builtin_popcountl(KERNEL_BASE)); + // Flush the cache so that we don't receive unexpected writebacks later. + _arch_cache_clean_poc(); + WRITE_SPECIALREG(TCR_EL1, tcr); + + // Invalidate all TLB entries. Also ensures that all memory traffic has + // resolved, and flushes the instruction pipeline. + _arch_mmu_invalidate_tlb_all(arch_exception_level()); } @@ -348,9 +355,7 @@ arch_mmu_allocate_kernel_page_tables(void) if (page == NULL) { page = CurrentRegime.AllocatePage(); if (page != NULL) { - arch_cache_disable(); WRITE_SPECIALREG(TTBR1_EL1, page); - arch_cache_enable(); } else { panic("Not enough memory for kernel initial page\n"); }