From 9331e9bb0d6dfbd77e2fc25a5c969b7abd999d0a Mon Sep 17 00:00:00 2001 From: Alexander von Gluck IV Date: Thu, 12 May 2011 22:03:47 +0000 Subject: [PATCH] fix bitwise check for mode timing polarity git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@41466 a95241bf-73f2-0310-859d-f6bbb57e9c96 --- src/add-ons/accelerants/radeon_hd/mode.cpp | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-) diff --git a/src/add-ons/accelerants/radeon_hd/mode.cpp b/src/add-ons/accelerants/radeon_hd/mode.cpp index 5b7cd6d63d..427afc8a9b 100644 --- a/src/add-ons/accelerants/radeon_hd/mode.cpp +++ b/src/add-ons/accelerants/radeon_hd/mode.cpp @@ -159,7 +159,7 @@ CardModeSet(display_mode *mode) (displayTiming.h_sync_end - displayTiming.h_sync_start) << 16); // set flag for neg. H sync - if (displayTiming.flags & ~B_POSITIVE_HSYNC) + if (!(displayTiming.flags & B_POSITIVE_HSYNC)) write32(regOffset + D1CRTC_H_SYNC_A_CNTL, 0x01); // *** Vertical @@ -184,7 +184,7 @@ CardModeSet(display_mode *mode) (displayTiming.v_sync_end - displayTiming.v_sync_start) << 16); // set flag for neg. V sync - if (displayTiming.flags & ~B_POSITIVE_VSYNC) + if (!(displayTiming.flags & B_POSITIVE_VSYNC)) write32(regOffset + D1CRTC_V_SYNC_A_CNTL, 0x01); /* set D1CRTC_HORZ_COUNT_BY2_EN to 0;