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More SandyBridge specifics: Use the proper registers for display detection and

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DPMS. Still needs to be reworked...


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42846 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Michael Lotz
2011-10-13 16:56:11 +00:00
parent 832d09b54d
commit 951b5e5147
3 changed files with 50 additions and 27 deletions
Download Patch File Download Diff File Expand all files Collapse all files
src/add-ons/accelerants/intel_extreme/accelerant.cpp
+10 -5
View File
@@ -203,22 +203,27 @@ intel_init_accelerant(int device)
if (read32(INTEL_DISPLAY_A_PIPE_CONTROL) & DISPLAY_PIPE_ENABLED)
gInfo->head_mode |= HEAD_MODE_A_ANALOG;
uint32 lvds = read32(INTEL_DISPLAY_LVDS_PORT);
bool isSNB = gInfo->shared_info->device_type.InGroup(INTEL_TYPE_SNB);
int lvdsRegister = isSNB ? PCH_DISPLAY_LVDS_PORT : INTEL_DISPLAY_LVDS_PORT;
uint32 lvds = read32(lvdsRegister);
// If we have an enabled display pipe we save the passed information and
// assume it is the valid panel size..
// Later we query for proper EDID info if it exists, or figure something
// else out. (Default modes, etc.)
if ((lvds & DISPLAY_PIPE_ENABLED) != 0) {
if ((isSNB && (lvds & PCH_LVDS_DETECTED) != 0)
|| (!isSNB && (lvds & DISPLAY_PIPE_ENABLED) != 0)) {
save_lvds_mode();
gInfo->head_mode |= HEAD_MODE_LVDS_PANEL;
}
TRACE(("head detected: %#x\n", gInfo->head_mode));
TRACE(("adpa: %08lx, dova: %08lx, dovb: %08lx, lvds: %08lx\n",
read32(INTEL_DISPLAY_A_ANALOG_PORT),
read32(INTEL_DISPLAY_A_DIGITAL_PORT),
read32(INTEL_DISPLAY_B_DIGITAL_PORT), read32(INTEL_DISPLAY_LVDS_PORT)));
read32(isSNB ? PCH_DISPLAY_A_ANALOG_PORT : INTEL_DISPLAY_A_ANALOG_PORT),
read32(isSNB ? PCH_DISPLAY_A_DIGITAL_PORT
: INTEL_DISPLAY_A_DIGITAL_PORT),
read32(isSNB ? PCH_DISPLAY_B_DIGITAL_PORT
: INTEL_DISPLAY_B_DIGITAL_PORT), read32(lvdsRegister)));
status = create_mode_list();
if (status != B_OK) {
src/add-ons/accelerants/intel_extreme/dpms.cpp
+31 -21
View File
@@ -104,32 +104,35 @@ set_display_power_mode(uint32 mode)
{
uint32 monitorMode = 0;
bool isSNB = gInfo->shared_info->device_type.InGroup(INTEL_TYPE_SNB);
if (mode == B_DPMS_ON) {
uint32 pll = read32(INTEL_DISPLAY_A_PLL);
int targetRegister = isSNB ? PCH_DISPLAY_A_PLL : INTEL_DISPLAY_A_PLL;
uint32 pll = read32(targetRegister);
if ((pll & DISPLAY_PLL_ENABLED) == 0) {
// reactivate PLL
write32(INTEL_DISPLAY_A_PLL, pll);
read32(INTEL_DISPLAY_A_PLL);
write32(targetRegister, pll);
read32(targetRegister);
spin(150);
write32(INTEL_DISPLAY_A_PLL, pll | DISPLAY_PLL_ENABLED);
read32(INTEL_DISPLAY_A_PLL);
write32(targetRegister, pll | DISPLAY_PLL_ENABLED);
read32(targetRegister);
spin(150);
write32(INTEL_DISPLAY_A_PLL, pll | DISPLAY_PLL_ENABLED);
read32(INTEL_DISPLAY_A_PLL);
write32(targetRegister, pll | DISPLAY_PLL_ENABLED);
read32(targetRegister);
spin(150);
}
pll = read32(INTEL_DISPLAY_B_PLL);
targetRegister = isSNB ? PCH_DISPLAY_B_PLL : INTEL_DISPLAY_B_PLL;
pll = read32(targetRegister);
if ((pll & DISPLAY_PLL_ENABLED) == 0) {
// reactivate PLL
write32(INTEL_DISPLAY_B_PLL, pll);
read32(INTEL_DISPLAY_B_PLL);
write32(targetRegister, pll);
read32(targetRegister);
spin(150);
write32(INTEL_DISPLAY_B_PLL, pll | DISPLAY_PLL_ENABLED);
read32(INTEL_DISPLAY_B_PLL);
write32(targetRegister, pll | DISPLAY_PLL_ENABLED);
read32(targetRegister);
spin(150);
write32(INTEL_DISPLAY_B_PLL, pll | DISPLAY_PLL_ENABLED);
read32(INTEL_DISPLAY_B_PLL);
write32(targetRegister, pll | DISPLAY_PLL_ENABLED);
read32(targetRegister);
spin(150);
}
@@ -155,12 +158,16 @@ set_display_power_mode(uint32 mode)
}
if (gInfo->head_mode & HEAD_MODE_A_ANALOG) {
write32(INTEL_DISPLAY_A_ANALOG_PORT, (read32(INTEL_DISPLAY_A_ANALOG_PORT)
int targetRegister
= isSNB ? PCH_DISPLAY_A_ANALOG_PORT : INTEL_DISPLAY_A_ANALOG_PORT;
write32(targetRegister, (read32(targetRegister)
& ~(DISPLAY_MONITOR_MODE_MASK | DISPLAY_MONITOR_PORT_ENABLED))
| monitorMode | (mode != B_DPMS_OFF ? DISPLAY_MONITOR_PORT_ENABLED : 0));
}
if (gInfo->head_mode & HEAD_MODE_B_DIGITAL) {
write32(INTEL_DISPLAY_B_DIGITAL_PORT, (read32(INTEL_DISPLAY_B_DIGITAL_PORT)
int targetRegister
= isSNB ? PCH_DISPLAY_B_DIGITAL_PORT : INTEL_DISPLAY_B_DIGITAL_PORT;
write32(targetRegister, (read32(targetRegister)
& ~(DISPLAY_MONITOR_MODE_MASK | DISPLAY_MONITOR_PORT_ENABLED))
| (mode != B_DPMS_OFF ? DISPLAY_MONITOR_PORT_ENABLED : 0));
// TODO: monitorMode?
@@ -173,18 +180,21 @@ set_display_power_mode(uint32 mode)
}
if (mode == B_DPMS_OFF) {
write32(INTEL_DISPLAY_A_PLL, read32(INTEL_DISPLAY_A_PLL)
int targetRegister = isSNB ? PCH_DISPLAY_A_PLL : INTEL_DISPLAY_A_PLL;
write32(targetRegister, read32(targetRegister)
| DISPLAY_PLL_ENABLED);
write32(INTEL_DISPLAY_B_PLL, read32(INTEL_DISPLAY_B_PLL)
targetRegister = isSNB ? PCH_DISPLAY_B_PLL : INTEL_DISPLAY_B_PLL;
write32(targetRegister, read32(targetRegister)
| DISPLAY_PLL_ENABLED);
read32(INTEL_DISPLAY_B_PLL);
// flush the eventually cached PCI bus writes
read32(targetRegister);
// flush the possibly cached PCI bus writes
spin(150);
}
if ((gInfo->head_mode & HEAD_MODE_LVDS_PANEL) != 0)
// TODO: fix for SNB
if (!isSNB && (gInfo->head_mode & HEAD_MODE_LVDS_PANEL) != 0)
enable_lvds_panel(mode == B_DPMS_ON);
read32(INTEL_DISPLAY_A_BASE);