x86: enable data execution prevention

Set execute disable bit for any page that belongs to area with neither
B_EXECUTE_AREA nor B_KERNEL_EXECUTE_AREA set.

In order to take advanage of NX bit in 32 bit protected mode PAE must be
enabled. Thus, from now on it is also enabled when the CPU supports NX bit.

vm_page_fault() takes additional argument which indicates whether page fault
was caused by an illegal instruction fetch.

headers/private/kernel/arch/x86/arch_cpu.h

@@ -39,6 +39,11 @@
 
 #define IA32_MSR_EFER					0xc0000080
 
+// MSR EFER bits
+// reference
+#define IA32_MSR_EFER_SYSCALL			(1 << 0)
+#define IA32_MSR_EFER_NX				(1 << 11)
+
 // x86_64 MSRs.
 #define IA32_MSR_STAR					0xc0000081
 #define IA32_MSR_LSTAR					0xc0000082
@@ -131,6 +136,13 @@
 #define IA32_FEATURE_AMD_EXT_3DNOWEXT	(1 << 30) // 3DNow! extensions
 #define IA32_FEATURE_AMD_EXT_3DNOW		(1 << 31) // 3DNow!
 
+// some of the features from cpuid eax 0x80000001, edx register (AMD) are also
+// available on Intel processors
+#define IA32_FEATURES_INTEL_EXT			(IA32_FEATURE_AMD_EXT_SYSCALL		\
+											| IA32_FEATURE_AMD_EXT_NX		\
+											| IA32_FEATURE_AMD_EXT_RDTSCP	\
+											| IA32_FEATURE_AMD_EXT_LONG)
+
 // x86 defined features from cpuid eax 6, eax register
 // reference http://www.intel.com/Assets/en_US/PDF/appnote/241618.pdf (Table 5-11)
 #define IA32_FEATURE_DTS	(1 << 0) //Digital Thermal Sensor

headers/private/kernel/vm/vm_priv.h

@@ -28,7 +28,7 @@ extern "C" {
 
 // Should only be used by vm internals
 status_t vm_page_fault(addr_t address, addr_t faultAddress, bool isWrite,
-	bool isUser, addr_t *newip);
+	bool isExecute, bool isUser, addr_t *newip);
 void vm_unreserve_memory(size_t bytes);
 status_t vm_try_reserve_memory(size_t bytes, int priority, bigtime_t timeout);
 status_t vm_daemon_init(void);