pch_i2c: bail out if BAR isn't configured
Change-Id: If271dc01bade8a5fcf28c7a3e734d573c0008b04 Reviewed-on: https://review.haiku-os.org/c/haiku/+/4883 Reviewed-by: Adrien Destugues <[email protected]> Tested-by: Commit checker robot <[email protected]>
This commit is contained in:
committed by
waddlesplash
parent
789bcfd8de
commit
971ad09095
@@ -403,7 +403,7 @@ init_bus(device_node* node, void** bus_cookie)
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gDeviceManager->get_driver(parent, &driver, (void**)&bus);
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gDeviceManager->get_driver(parent, &driver, (void**)&bus);
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gDeviceManager->put_node(parent);
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gDeviceManager->put_node(parent);
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TRACE_ALWAYS("init_bus() addr 0x%" B_PRIxPHYSADDR " size 0x%" B_PRIxSIZE
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TRACE_ALWAYS("init_bus() addr 0x%" B_PRIxPHYSADDR " size 0x%" B_PRIx64
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" irq 0x%x\n", bus->base_addr, bus->map_size, bus->irq);
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" irq 0x%x\n", bus->base_addr, bus->map_size, bus->irq);
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bus->registersArea = map_physical_memory("PCHI2C memory mapped registers",
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bus->registersArea = map_physical_memory("PCHI2C memory mapped registers",
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@@ -412,7 +412,7 @@ init_bus(device_node* node, void** bus_cookie)
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(void **)&bus->registers);
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(void **)&bus->registers);
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// init bus
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// init bus
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bus->capabilities = read32(bus->registers + PCH_SUP_CAPABLITIES);
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bus->capabilities = read32(bus->registers + PCH_SUP_CAPABLITIES);
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TRACE_ALWAYS("init_bus() 0x%x (0x%" B_PRIx32 ")\n",
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TRACE_ALWAYS("init_bus() 0x%" B_PRIx32 " (0x%" B_PRIx32 ")\n",
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(bus->capabilities >> PCH_SUP_CAPABLITIES_TYPE_SHIFT)
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(bus->capabilities >> PCH_SUP_CAPABLITIES_TYPE_SHIFT)
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& PCH_SUP_CAPABLITIES_TYPE_MASK,
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& PCH_SUP_CAPABLITIES_TYPE_MASK,
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bus->capabilities);
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bus->capabilities);
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@@ -72,7 +72,7 @@ typedef enum {
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typedef struct {
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typedef struct {
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phys_addr_t base_addr;
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phys_addr_t base_addr;
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size_t map_size;
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uint64 map_size;
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uint8 irq;
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uint8 irq;
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i2c_bus sim;
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i2c_bus sim;
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@@ -131,12 +131,18 @@ init_device(device_node* node, void** device_cookie)
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pci->get_pci_info(device, pciInfo);
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pci->get_pci_info(device, pciInfo);
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bus->info.base_addr = pciInfo->u.h0.base_registers[0];
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bus->info.base_addr = pciInfo->u.h0.base_registers[0];
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bus->info.map_size = pciInfo->u.h0.base_register_sizes[0];
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if ((pciInfo->u.h0.base_register_flags[0] & PCI_address_type)
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if ((pciInfo->u.h0.base_register_flags[0] & PCI_address_type)
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== PCI_address_type_64) {
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== PCI_address_type_64) {
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bus->info.base_addr |= (uint64)pciInfo->u.h0.base_registers[1] << 32;
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bus->info.base_addr |= (uint64)pciInfo->u.h0.base_registers[1] << 32;
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bus->info.map_size |= (uint64)pciInfo->u.h0.base_register_sizes[1] << 32;
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}
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}
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bus->info.map_size = pciInfo->u.h0.base_register_sizes[0];
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if (bus->info.base_addr == 0) {
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ERROR("PCI BAR not assigned\n");
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free(bus);
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return B_ERROR;
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}
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// enable power
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// enable power
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pci->set_powerstate(device, PCI_pm_state_d0);
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pci->set_powerstate(device, PCI_pm_state_d0);
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