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Style fix gpu_state naming, cleanup

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* correct naming on gpu registers that effect MC idle state
* cleanup MC idle failure situation, we are stuck and
  need to try the changes anyway.
This commit is contained in:
Alexander von Gluck IV
2011-11-21 17:00:07 -06:00
parent 28e71fb070
commit 97b846e874
2 changed files with 30 additions and 36 deletions
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src/add-ons/accelerants/radeon_hd/accelerant.h
+6 -6
View File
@@ -26,12 +26,12 @@
struct gpu_state { struct gpu_state {
uint32 d1vga_control; uint32 d1vgaControl;
uint32 d2vga_control; uint32 d2vgaControl;
uint32 vga_render_control; uint32 vgaRenderControl;
uint32 vga_hdp_control; uint32 vgaHdpControl;
uint32 d1crtc_control; uint32 d1crtcControl;
uint32 d2crtc_control; uint32 d2crtcControl;
}; };
src/add-ons/accelerants/radeon_hd/gpu.cpp
+24 -30
View File
@@ -166,12 +166,12 @@ void
radeon_gpu_mc_halt(gpu_state *gpuState) radeon_gpu_mc_halt(gpu_state *gpuState)
{ {
// Backup current memory controller state // Backup current memory controller state
gpuState->d1vga_control = Read32(OUT, D1VGA_CONTROL); gpuState->d1vgaControl = Read32(OUT, D1VGA_CONTROL);
gpuState->d2vga_control = Read32(OUT, D2VGA_CONTROL); gpuState->d2vgaControl = Read32(OUT, D2VGA_CONTROL);
gpuState->vga_render_control = Read32(OUT, VGA_RENDER_CONTROL); gpuState->vgaRenderControl = Read32(OUT, VGA_RENDER_CONTROL);
gpuState->vga_hdp_control = Read32(OUT, VGA_HDP_CONTROL); gpuState->vgaHdpControl = Read32(OUT, VGA_HDP_CONTROL);
gpuState->d1crtc_control = Read32(OUT, D1CRTC_CONTROL); gpuState->d1crtcControl = Read32(OUT, D1CRTC_CONTROL);
gpuState->d2crtc_control = Read32(OUT, D2CRTC_CONTROL); gpuState->d2crtcControl = Read32(OUT, D2CRTC_CONTROL);
// halt all memory controller actions // halt all memory controller actions
Write32(OUT, D2CRTC_UPDATE_LOCK, 0); Write32(OUT, D2CRTC_UPDATE_LOCK, 0);
@@ -197,19 +197,19 @@ radeon_gpu_mc_resume(gpu_state *gpuState)
Write32(OUT, VGA_MEMORY_BASE_ADDRESS, gInfo->fb.vramStart); Write32(OUT, VGA_MEMORY_BASE_ADDRESS, gInfo->fb.vramStart);
// Unlock host access // Unlock host access
Write32(OUT, VGA_HDP_CONTROL, gpuState->vga_hdp_control); Write32(OUT, VGA_HDP_CONTROL, gpuState->vgaHdpControl);
snooze(1); snooze(1);
// Restore memory controller state // Restore memory controller state
Write32(OUT, D1VGA_CONTROL, gpuState->d1vga_control); Write32(OUT, D1VGA_CONTROL, gpuState->d1vgaControl);
Write32(OUT, D2VGA_CONTROL, gpuState->d2vga_control); Write32(OUT, D2VGA_CONTROL, gpuState->d2vgaControl);
Write32(OUT, D1CRTC_UPDATE_LOCK, 1); Write32(OUT, D1CRTC_UPDATE_LOCK, 1);
Write32(OUT, D2CRTC_UPDATE_LOCK, 1); Write32(OUT, D2CRTC_UPDATE_LOCK, 1);
Write32(OUT, D1CRTC_CONTROL, gpuState->d1crtc_control); Write32(OUT, D1CRTC_CONTROL, gpuState->d1crtcControl);
Write32(OUT, D2CRTC_CONTROL, gpuState->d2crtc_control); Write32(OUT, D2CRTC_CONTROL, gpuState->d2crtcControl);
Write32(OUT, D1CRTC_UPDATE_LOCK, 0); Write32(OUT, D1CRTC_UPDATE_LOCK, 0);
Write32(OUT, D2CRTC_UPDATE_LOCK, 0); Write32(OUT, D2CRTC_UPDATE_LOCK, 0);
Write32(OUT, VGA_RENDER_CONTROL, gpuState->vga_render_control); Write32(OUT, VGA_RENDER_CONTROL, gpuState->vgaRenderControl);
} }
@@ -262,9 +262,8 @@ radeon_gpu_mc_setup_r600()
uint32 idleState = radeon_gpu_mc_idlecheck(); uint32 idleState = radeon_gpu_mc_idlecheck();
if (idleState > 0) { if (idleState > 0) {
ERROR("%s: Cannot modify non-idle MC! idleState: 0x%" B_PRIX32 "\n", ERROR("%s: Modifying non-idle Memory Controller! "
__func__, idleState); " idlestate: 0x%" B_PRIX32 "\n", __func__, idleState);
//return B_ERROR;
} }
// TODO: Memory Controller AGP // TODO: Memory Controller AGP
@@ -293,9 +292,8 @@ radeon_gpu_mc_setup_r600()
idleState = radeon_gpu_mc_idlecheck(); idleState = radeon_gpu_mc_idlecheck();
if (idleState > 0) { if (idleState > 0) {
ERROR("%s: Cannot modify non-idle MC! idleState: 0x%" B_PRIX32 "\n", ERROR("%s: Modifying non-idle Memory Controller! "
__func__, idleState); " idlestate: 0x%" B_PRIX32 "\n", __func__, idleState);
//return B_ERROR;
} }
radeon_gpu_mc_resume(&gpuState); radeon_gpu_mc_resume(&gpuState);
@@ -329,9 +327,8 @@ radeon_gpu_mc_setup_r700()
uint32 idleState = radeon_gpu_mc_idlecheck(); uint32 idleState = radeon_gpu_mc_idlecheck();
if (idleState > 0) { if (idleState > 0) {
ERROR("%s: Cannot modify non-idle MC! idleState: 0x%" B_PRIX32 "\n", ERROR("%s: Modifying non-idle Memory Controller! "
__func__, idleState); " idlestate: 0x%" B_PRIX32 "\n", __func__, idleState);
//return B_ERROR;
} }
Write32(OUT, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); Write32(OUT, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
@@ -362,9 +359,8 @@ radeon_gpu_mc_setup_r700()
idleState = radeon_gpu_mc_idlecheck(); idleState = radeon_gpu_mc_idlecheck();
if (idleState > 0) { if (idleState > 0) {
ERROR("%s: Cannot modify non-idle MC! idleState: 0x%" B_PRIX32 "\n", ERROR("%s: Modifying non-idle Memory Controller! "
__func__, idleState); " idlestate: 0x%" B_PRIX32 "\n", __func__, idleState);
//return B_ERROR;
} }
radeon_gpu_mc_resume(&gpuState); radeon_gpu_mc_resume(&gpuState);
@@ -396,9 +392,8 @@ radeon_gpu_mc_setup_evergreen()
uint32 idleState = radeon_gpu_mc_idlecheck(); uint32 idleState = radeon_gpu_mc_idlecheck();
if (idleState > 0) { if (idleState > 0) {
ERROR("%s: Cannot modify non-idle MC! idleState: 0x%" B_PRIX32 "\n", ERROR("%s: Modifying non-idle Memory Controller! "
__func__, idleState); " idlestate: 0x%" B_PRIX32 "\n", __func__, idleState);
//return B_ERROR;
} }
Write32(OUT, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE); Write32(OUT, VGA_HDP_CONTROL, VGA_MEMORY_DISABLE);
@@ -440,9 +435,8 @@ radeon_gpu_mc_setup_evergreen()
idleState = radeon_gpu_mc_idlecheck(); idleState = radeon_gpu_mc_idlecheck();
if (idleState > 0) { if (idleState > 0) {
ERROR("%s: Cannot modify non-idle MC! idleState: 0x%" B_PRIX32 "\n", ERROR("%s: Modifying non-idle Memory Controller! "
__func__, idleState); " idlestate: 0x%" B_PRIX32 "\n", __func__, idleState);
//return B_ERROR;
} }
radeon_gpu_mc_resume(&gpuState); radeon_gpu_mc_resume(&gpuState);