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Avoid undefined behavior by using unsigned int instead of int.

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* 1 << 31, 2 << 30, 3 << 30 replaced by 1U << 31, 2U << 30 or 3U << 30.
This commit is contained in:
Jérôme Duval
2013-12-03 18:40:25 +01:00
parent f36e1414b7
commit 97f865f72a
5 changed files with 73 additions and 73 deletions
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src/add-ons/kernel/busses/scsi/ahci/ahci_defs.h
+2 -2
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@@ -21,7 +21,7 @@ extern "C" {
enum { enum {
CAP_S64A = (1 << 31), // Supports 64-bit Addressing CAP_S64A = (1U << 31), // Supports 64-bit Addressing
CAP_SNCQ = (1 << 30), // Supports Native Command Queuing CAP_SNCQ = (1 << 30), // Supports Native Command Queuing
CAP_SSNTF = (1 << 29), // Supports SNotification Register CAP_SSNTF = (1 << 29), // Supports SNotification Register
CAP_SMPS = (1 << 28), // Supports Mechanical Presence Switch CAP_SMPS = (1 << 28), // Supports Mechanical Presence Switch
@@ -49,7 +49,7 @@ enum {
enum { enum {
GHC_AE = (1 << 31), // AHCI Enable GHC_AE = (1U << 31), // AHCI Enable
GHC_MRSM = (1 << 2), // MSI Revert to Single Message GHC_MRSM = (1 << 2), // MSI Revert to Single Message
GHC_IE = (1 << 1), // Interrupt Enable GHC_IE = (1 << 1), // Interrupt Enable
GHC_HR = (1 << 0), // HBA Reset **RW1** GHC_HR = (1 << 0), // HBA Reset **RW1**
src/add-ons/kernel/busses/usb/ehci_hardware.h
+2 -2
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@@ -213,7 +213,7 @@ typedef struct ehci_qtd {
} _PACKED ehci_qtd; } _PACKED ehci_qtd;
#define EHCI_QTD_DATA_TOGGLE (1 << 31) #define EHCI_QTD_DATA_TOGGLE (1U << 31)
#define EHCI_QTD_BYTES_SHIFT 16 #define EHCI_QTD_BYTES_SHIFT 16
#define EHCI_QTD_BYTES_MASK 0x7fff #define EHCI_QTD_BYTES_MASK 0x7fff
#define EHCI_QTD_IOC (1 << 15) #define EHCI_QTD_IOC (1 << 15)
@@ -337,7 +337,7 @@ typedef struct {
#define EHCI_QH_OL_NAK_SHIFT 1 #define EHCI_QH_OL_NAK_SHIFT 1
#define EHCI_QH_OL_NAK_MASK 0x0f #define EHCI_QH_OL_NAK_MASK 0x0f
#define EHCI_QH_OL_TOGGLE_INDEX 2 // Data Toggle #define EHCI_QH_OL_TOGGLE_INDEX 2 // Data Toggle
#define EHCI_QH_OL_TOGGLE (1 << 31) #define EHCI_QH_OL_TOGGLE (1U << 31)
#define EHCI_QH_OL_IOC_INDEX 2 // Interrupt on Complete #define EHCI_QH_OL_IOC_INDEX 2 // Interrupt on Complete
#define EHCI_QH_OL_IOC (1 << 15) #define EHCI_QH_OL_IOC (1 << 15)
#define EHCI_QH_OL_ERRC_INDEX 2 // Error Counter #define EHCI_QH_OL_ERRC_INDEX 2 // Error Counter
src/add-ons/kernel/drivers/audio/hda/hda_controller_defs.h
+2 -2
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@@ -34,11 +34,11 @@
#define HDAC_STATE_STATUS 0x0e // 16bits, STATESTS #define HDAC_STATE_STATUS 0x0e // 16bits, STATESTS
#define HDAC_INTR_CONTROL 0x20 // 32bits, INTCTL #define HDAC_INTR_CONTROL 0x20 // 32bits, INTCTL
#define INTR_CONTROL_GLOBAL_ENABLE (1 << 31) #define INTR_CONTROL_GLOBAL_ENABLE (1U << 31)
#define INTR_CONTROL_CONTROLLER_ENABLE (1 << 30) #define INTR_CONTROL_CONTROLLER_ENABLE (1 << 30)
#define HDAC_INTR_STATUS 0x24 // 32bits, INTSTS #define HDAC_INTR_STATUS 0x24 // 32bits, INTSTS
#define INTR_STATUS_GLOBAL (1 << 31) #define INTR_STATUS_GLOBAL (1U << 31)
#define INTR_STATUS_CONTROLLER (1 << 30) #define INTR_STATUS_CONTROLLER (1 << 30)
#define INTR_STATUS_STREAM_MASK 0x3fffffff #define INTR_STATUS_STREAM_MASK 0x3fffffff
src/add-ons/media/media-add-ons/radeon/Radeon.h
+1 -1
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@@ -238,7 +238,7 @@ enum radeon_register {
C_RADEON_CAP0_VBI_HORZ_DOWN = BITS(31:30), C_RADEON_CAP0_VBI_HORZ_DOWN = BITS(31:30),
C_RADEON_CAP0_VBI_HORZ_DOWN_1X = 0 << 30, C_RADEON_CAP0_VBI_HORZ_DOWN_1X = 0 << 30,
C_RADEON_CAP0_VBI_HORZ_DOWN_2X = 1 << 30, C_RADEON_CAP0_VBI_HORZ_DOWN_2X = 1 << 30,
C_RADEON_CAP0_VBI_HORZ_DOWN_4X = 2 << 30, C_RADEON_CAP0_VBI_HORZ_DOWN_4X = 2U << 30,
C_RADEON_CAP0_ANC0_OFFSET = 0x095C, C_RADEON_CAP0_ANC0_OFFSET = 0x095C,
C_RADEON_CAP0_ANC1_OFFSET = 0x0960, C_RADEON_CAP0_ANC1_OFFSET = 0x0960,
src/add-ons/media/media-add-ons/radeon/TheatreReg.h
+2 -2
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@@ -917,8 +917,8 @@ enum theater_register {
VIN_REF_CLK_SEL = BITS(31:30), // VIN reference source select VIN_REF_CLK_SEL = BITS(31:30), // VIN reference source select
VIN_REF_CLK = 0 << 30, // Reference clock VIN_REF_CLK = 0 << 30, // Reference clock
VIN_SEC_REF_CLK = 1 << 30, // Secondary Reference Clock VIN_SEC_REF_CLK = 1 << 30, // Secondary Reference Clock
VIN_L54_CLK = 2 << 30, // L54 PLL Clock VIN_L54_CLK = 2U << 30, // L54 PLL Clock
VIN_SLIP_L54_CLK = 3 << 30, // Slippable L54 PLL Clock VIN_SLIP_L54_CLK = 3U << 30, // Slippable L54 PLL Clock
VIP_VIN_PLL_FINE_CNTL = 0x00d8, VIP_VIN_PLL_FINE_CNTL = 0x00d8,
VIN_M1 = BITS(10:0), VIN_M1 = BITS(10:0),