Avoid undefined behavior by using unsigned int instead of int.
* 1 << 31, 2 << 30, 3 << 30 replaced by 1U << 31, 2U << 30 or 3U << 30.
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@@ -21,7 +21,7 @@ extern "C" {
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enum {
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CAP_S64A = (1 << 31), // Supports 64-bit Addressing
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CAP_S64A = (1U << 31), // Supports 64-bit Addressing
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CAP_SNCQ = (1 << 30), // Supports Native Command Queuing
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CAP_SSNTF = (1 << 29), // Supports SNotification Register
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CAP_SMPS = (1 << 28), // Supports Mechanical Presence Switch
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@@ -49,7 +49,7 @@ enum {
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enum {
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GHC_AE = (1 << 31), // AHCI Enable
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GHC_AE = (1U << 31), // AHCI Enable
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GHC_MRSM = (1 << 2), // MSI Revert to Single Message
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GHC_IE = (1 << 1), // Interrupt Enable
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GHC_HR = (1 << 0), // HBA Reset **RW1**
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@@ -213,7 +213,7 @@ typedef struct ehci_qtd {
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} _PACKED ehci_qtd;
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#define EHCI_QTD_DATA_TOGGLE (1 << 31)
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#define EHCI_QTD_DATA_TOGGLE (1U << 31)
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#define EHCI_QTD_BYTES_SHIFT 16
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#define EHCI_QTD_BYTES_MASK 0x7fff
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#define EHCI_QTD_IOC (1 << 15)
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@@ -337,7 +337,7 @@ typedef struct {
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#define EHCI_QH_OL_NAK_SHIFT 1
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#define EHCI_QH_OL_NAK_MASK 0x0f
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#define EHCI_QH_OL_TOGGLE_INDEX 2 // Data Toggle
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#define EHCI_QH_OL_TOGGLE (1 << 31)
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#define EHCI_QH_OL_TOGGLE (1U << 31)
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#define EHCI_QH_OL_IOC_INDEX 2 // Interrupt on Complete
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#define EHCI_QH_OL_IOC (1 << 15)
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#define EHCI_QH_OL_ERRC_INDEX 2 // Error Counter
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@@ -34,11 +34,11 @@
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#define HDAC_STATE_STATUS 0x0e // 16bits, STATESTS
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#define HDAC_INTR_CONTROL 0x20 // 32bits, INTCTL
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#define INTR_CONTROL_GLOBAL_ENABLE (1 << 31)
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#define INTR_CONTROL_GLOBAL_ENABLE (1U << 31)
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#define INTR_CONTROL_CONTROLLER_ENABLE (1 << 30)
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#define HDAC_INTR_STATUS 0x24 // 32bits, INTSTS
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#define INTR_STATUS_GLOBAL (1 << 31)
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#define INTR_STATUS_GLOBAL (1U << 31)
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#define INTR_STATUS_CONTROLLER (1 << 30)
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#define INTR_STATUS_STREAM_MASK 0x3fffffff
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@@ -238,7 +238,7 @@ enum radeon_register {
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C_RADEON_CAP0_VBI_HORZ_DOWN = BITS(31:30),
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C_RADEON_CAP0_VBI_HORZ_DOWN_1X = 0 << 30,
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C_RADEON_CAP0_VBI_HORZ_DOWN_2X = 1 << 30,
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C_RADEON_CAP0_VBI_HORZ_DOWN_4X = 2 << 30,
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C_RADEON_CAP0_VBI_HORZ_DOWN_4X = 2U << 30,
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C_RADEON_CAP0_ANC0_OFFSET = 0x095C,
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C_RADEON_CAP0_ANC1_OFFSET = 0x0960,
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@@ -917,8 +917,8 @@ enum theater_register {
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VIN_REF_CLK_SEL = BITS(31:30), // VIN reference source select
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VIN_REF_CLK = 0 << 30, // Reference clock
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VIN_SEC_REF_CLK = 1 << 30, // Secondary Reference Clock
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VIN_L54_CLK = 2 << 30, // L54 PLL Clock
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VIN_SLIP_L54_CLK = 3 << 30, // Slippable L54 PLL Clock
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VIN_L54_CLK = 2U << 30, // L54 PLL Clock
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VIN_SLIP_L54_CLK = 3U << 30, // Slippable L54 PLL Clock
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VIP_VIN_PLL_FINE_CNTL = 0x00d8,
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VIN_M1 = BITS(10:0),
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