From 994794f2d48a45038444772109096a6abf4c07c3 Mon Sep 17 00:00:00 2001 From: Rudolf Cornelissen Date: Sat, 23 Oct 2021 17:10:39 +0000 Subject: [PATCH] intel extreme: skylake sets color, base and address, no resolution and refresh yet --- .../graphics/intel_extreme/intel_extreme.h | 8 +++++ .../accelerants/intel_extreme/Pipes.cpp | 17 ++++++--- .../accelerants/intel_extreme/engine.cpp | 5 +++ .../accelerants/intel_extreme/mode.cpp | 35 +++++++++++++++---- .../kernel/busses/agp_gart/intel_gart.cpp | 2 +- .../drivers/graphics/intel_extreme/driver.cpp | 1 + 6 files changed, 57 insertions(+), 11 deletions(-) diff --git a/headers/private/graphics/intel_extreme/intel_extreme.h b/headers/private/graphics/intel_extreme/intel_extreme.h index c48c963568..99dc9eaa09 100644 --- a/headers/private/graphics/intel_extreme/intel_extreme.h +++ b/headers/private/graphics/intel_extreme/intel_extreme.h @@ -762,6 +762,14 @@ struct intel_free_graphics_memory { #define DISPLAY_CONTROL_RGB15 (4UL << 26) #define DISPLAY_CONTROL_RGB16 (5UL << 26) #define DISPLAY_CONTROL_RGB32 (6UL << 26) +#define DISPLAY_CONTROL_RGB64 (0x0cUL << 26) +// Skylake +#define DISPLAY_CONTROL_COLOR_MASK_SKY (0x0fUL << 24) +#define DISPLAY_CONTROL_CMAP8_SKY (0x0cUL << 24) +#define DISPLAY_CONTROL_RGB15_SKY (0x0eUL << 24) +#define DISPLAY_CONTROL_RGB16_SKY (0x0eUL << 24) +#define DISPLAY_CONTROL_RGB32_SKY (0x04UL << 24) +#define DISPLAY_CONTROL_RGB64_SKY (0x06UL << 24) // INTEL_DISPLAY_A_PIPE_CONTROL ILK+ #define INTEL_PIPE_DITHER_TYPE_MASK (0x0000000c) diff --git a/src/add-ons/accelerants/intel_extreme/Pipes.cpp b/src/add-ons/accelerants/intel_extreme/Pipes.cpp index abf7043de4..985e0f31d7 100644 --- a/src/add-ons/accelerants/intel_extreme/Pipes.cpp +++ b/src/add-ons/accelerants/intel_extreme/Pipes.cpp @@ -38,12 +38,21 @@ void program_pipe_color_modes(uint32 colorMode) { // All pipes get the same color mode - write32(INTEL_DISPLAY_A_CONTROL, (read32(INTEL_DISPLAY_A_CONTROL) + if (gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_LAKE)) { + write32(INTEL_DISPLAY_A_CONTROL, (read32(INTEL_DISPLAY_A_CONTROL) + & ~(DISPLAY_CONTROL_COLOR_MASK_SKY | DISPLAY_CONTROL_GAMMA)) + | colorMode); + write32(INTEL_DISPLAY_B_CONTROL, (read32(INTEL_DISPLAY_B_CONTROL) + & ~(DISPLAY_CONTROL_COLOR_MASK_SKY | DISPLAY_CONTROL_GAMMA)) + | colorMode); + } else { + write32(INTEL_DISPLAY_A_CONTROL, (read32(INTEL_DISPLAY_A_CONTROL) & ~(DISPLAY_CONTROL_COLOR_MASK | DISPLAY_CONTROL_GAMMA)) - | colorMode); - write32(INTEL_DISPLAY_B_CONTROL, (read32(INTEL_DISPLAY_B_CONTROL) + | colorMode); + write32(INTEL_DISPLAY_B_CONTROL, (read32(INTEL_DISPLAY_B_CONTROL) & ~(DISPLAY_CONTROL_COLOR_MASK | DISPLAY_CONTROL_GAMMA)) - | colorMode); + | colorMode); + } } diff --git a/src/add-ons/accelerants/intel_extreme/engine.cpp b/src/add-ons/accelerants/intel_extreme/engine.cpp index 231fb78d80..a574f9a6ac 100644 --- a/src/add-ons/accelerants/intel_extreme/engine.cpp +++ b/src/add-ons/accelerants/intel_extreme/engine.cpp @@ -232,6 +232,11 @@ intel_wait_engine_idle(void) { CALLED(); + // Skylake acc engine not yet functional (stalls) + if (gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_LAKE)) { + return; + } + { QueueCommands queue(gInfo->shared_info->primary_ring_buffer); queue.PutFlush(); diff --git a/src/add-ons/accelerants/intel_extreme/mode.cpp b/src/add-ons/accelerants/intel_extreme/mode.cpp index f864c5b279..a1a23decfb 100644 --- a/src/add-ons/accelerants/intel_extreme/mode.cpp +++ b/src/add-ons/accelerants/intel_extreme/mode.cpp @@ -48,23 +48,39 @@ get_color_space_format(const display_mode &mode, uint32 &colorMode, switch (mode.space) { case B_RGB32_LITTLE: - colorMode = DISPLAY_CONTROL_RGB32; + if (gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_LAKE)) { + colorMode = DISPLAY_CONTROL_RGB32_SKY; + } else { + colorMode = DISPLAY_CONTROL_RGB32; + } bytesPerPixel = 4; bitsPerPixel = 32; break; case B_RGB16_LITTLE: - colorMode = DISPLAY_CONTROL_RGB16; + if (gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_LAKE)) { + colorMode = DISPLAY_CONTROL_RGB16_SKY; + } else { + colorMode = DISPLAY_CONTROL_RGB16; + } bytesPerPixel = 2; bitsPerPixel = 16; break; case B_RGB15_LITTLE: - colorMode = DISPLAY_CONTROL_RGB15; + if (gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_LAKE)) { + colorMode = DISPLAY_CONTROL_RGB15_SKY; + } else { + colorMode = DISPLAY_CONTROL_RGB15; + } bytesPerPixel = 2; bitsPerPixel = 15; break; case B_CMAP8: default: - colorMode = DISPLAY_CONTROL_CMAP8; + if (gInfo->shared_info->device_type.InFamily(INTEL_FAMILY_LAKE)) { + colorMode = DISPLAY_CONTROL_CMAP8_SKY; + } else { + colorMode = DISPLAY_CONTROL_CMAP8; + } bytesPerPixel = 1; bitsPerPixel = 8; break; @@ -121,8 +137,10 @@ set_frame_buffer_registers(uint32 offset) || sharedInfo.device_type.InGroup(INTEL_GROUP_G4x) || sharedInfo.device_type.InGroup(INTEL_GROUP_ILK) || sharedInfo.device_type.InFamily(INTEL_FAMILY_SER5) + || sharedInfo.device_type.InFamily(INTEL_FAMILY_LAKE) || sharedInfo.device_type.InFamily(INTEL_FAMILY_SOC0)) { if (sharedInfo.device_type.InGroup(INTEL_GROUP_HAS)) { +// || sharedInfo.device_type.InGroup(INTEL_GROUP_SKY)) { write32(INTEL_DISPLAY_A_OFFSET_HAS + offset, ((uint32)mode.v_display_start << 16) | (uint32)mode.h_display_start); @@ -463,8 +481,13 @@ intel_set_display_mode(display_mode* mode) // Always set both pipes, just in case // TODO rework this when we get multiple head support with different // resolutions - write32(INTEL_DISPLAY_A_BYTES_PER_ROW, bytesPerRow); - write32(INTEL_DISPLAY_B_BYTES_PER_ROW, bytesPerRow); + if (sharedInfo.device_type.InFamily(INTEL_FAMILY_LAKE)) { + write32(INTEL_DISPLAY_A_BYTES_PER_ROW, bytesPerRow >> 6); + write32(INTEL_DISPLAY_B_BYTES_PER_ROW, bytesPerRow >> 6); + } else { + write32(INTEL_DISPLAY_A_BYTES_PER_ROW, bytesPerRow); + write32(INTEL_DISPLAY_B_BYTES_PER_ROW, bytesPerRow); + } // update shared info sharedInfo.current_mode = target; diff --git a/src/add-ons/kernel/busses/agp_gart/intel_gart.cpp b/src/add-ons/kernel/busses/agp_gart/intel_gart.cpp index 7ea83e009f..6ee5165454 100644 --- a/src/add-ons/kernel/busses/agp_gart/intel_gart.cpp +++ b/src/add-ons/kernel/busses/agp_gart/intel_gart.cpp @@ -132,7 +132,7 @@ const struct supported_device { {0x1904, 0x190a, INTEL_MODEL_SKYS, "Skylake GT1"}, {0x1904, 0x190b, INTEL_MODEL_SKY, "Skylake GT1"}, {0x1904, 0x190e, INTEL_MODEL_SKYM, "Skylake GT1"}, - {0x1904, 0x1912, INTEL_MODEL_SKY, "Skylake GT2"}, + {0x191f, 0x1912, INTEL_MODEL_SKY, "Skylake GT2"}, // confirmed {0x1904, 0x1916, INTEL_MODEL_SKYM, "Skylake GT2"}, {0x1904, 0x191a, INTEL_MODEL_SKYS, "Skylake GT2"}, {0x1904, 0x191b, INTEL_MODEL_SKY, "Skylake GT2"}, diff --git a/src/add-ons/kernel/drivers/graphics/intel_extreme/driver.cpp b/src/add-ons/kernel/drivers/graphics/intel_extreme/driver.cpp index 8b6a9cf999..241e198346 100644 --- a/src/add-ons/kernel/drivers/graphics/intel_extreme/driver.cpp +++ b/src/add-ons/kernel/drivers/graphics/intel_extreme/driver.cpp @@ -105,6 +105,7 @@ const struct supported_device { {0x0d26, INTEL_MODEL_HASM, "Haswell Mobile"}, {0x0a16, INTEL_MODEL_HASM, "Haswell Mobile"}, + {0x1912, INTEL_MODEL_SKY, "Skylake GT2"}, // testing.. #if 0 // The driver does not make any attempt to handle this modern hardware. // Better let VESA/UEFI do it.