drivers: Remove Intel Enhanced SpeedStep driver
In current state this driver is useless anyway. It's not MP safe. The P-state values stored in hardcoded tables are only for processors on which we can't use SpeedStep, because of lack of invariant TSC. Proper driver should get P-states from ACPI, ensure that the CPU offers invariant TSC and obviouslt be MP safe.
This commit is contained in:
Pawel Dziepak
@@ -61,7 +61,6 @@ if $(TARGET_ARCH) = x86 || $(TARGET_ARCH) = x86_64 {
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# drivers
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# drivers
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AddNewDriversToPackage disk scsi : scsi_cd scsi_disk ;
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AddNewDriversToPackage disk scsi : scsi_cd scsi_disk ;
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AddNewDriversToPackage disk virtual : virtio_block ;
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AddNewDriversToPackage disk virtual : virtio_block ;
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AddNewDriversToPackage power : enhanced_speedstep@x86 ;
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AddNewDriversToPackage power : acpi_battery@x86 ;
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AddNewDriversToPackage power : acpi_battery@x86 ;
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#AddNewDriversToPackage display : display_controls@x86 ;
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#AddNewDriversToPackage display : display_controls@x86 ;
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@@ -60,7 +60,6 @@ if $(TARGET_ARCH) = x86 || $(TARGET_ARCH) = x86_64 {
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# drivers
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# drivers
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AddNewDriversToPackage disk scsi : scsi_cd scsi_disk ;
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AddNewDriversToPackage disk scsi : scsi_cd scsi_disk ;
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AddNewDriversToPackage disk virtual : virtio_block ;
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AddNewDriversToPackage disk virtual : virtio_block ;
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AddNewDriversToPackage power : enhanced_speedstep@x86 ;
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AddNewDriversToPackage power : acpi_battery@x86 ;
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AddNewDriversToPackage power : acpi_battery@x86 ;
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#AddNewDriversToPackage display : display_controls@x86 ;
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#AddNewDriversToPackage display : display_controls@x86 ;
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@@ -4,5 +4,4 @@ SubInclude HAIKU_TOP src add-ons kernel drivers power acpi_battery ;
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SubInclude HAIKU_TOP src add-ons kernel drivers power acpi_button ;
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SubInclude HAIKU_TOP src add-ons kernel drivers power acpi_button ;
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SubInclude HAIKU_TOP src add-ons kernel drivers power acpi_lid ;
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SubInclude HAIKU_TOP src add-ons kernel drivers power acpi_lid ;
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SubInclude HAIKU_TOP src add-ons kernel drivers power acpi_thermal ;
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SubInclude HAIKU_TOP src add-ons kernel drivers power acpi_thermal ;
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SubInclude HAIKU_TOP src add-ons kernel drivers power enhanced_speedstep ;
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SubInclude HAIKU_TOP src add-ons kernel drivers power x86_cpuidle ;
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SubInclude HAIKU_TOP src add-ons kernel drivers power x86_cpuidle ;
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@@ -1,18 +0,0 @@
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SubDir HAIKU_TOP src add-ons kernel drivers power enhanced_speedstep ;
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SetSubDirSupportedPlatformsBeOSCompatible ;
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if $(TARGET_PLATFORM) != haiku {
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# Needed for <ACPI.h>. Unfortunately we also get the other headers there,
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# that we don't really want.
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UsePublicHeaders drivers ;
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}
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UsePrivateHeaders kernel ;
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KernelAddon enhanced_speedstep :
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enhanced_speedstep.cpp
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frequency.cpp
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;
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Depends acpi_enhanced_speedstep : acpi ;
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@@ -1,407 +0,0 @@
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/*
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* Copyright 2009, Haiku, Inc. All Rights Reserved.
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* Distributed under the terms of the MIT License.
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*
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* Authors:
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* Clemens Zeidler, [email protected]
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*/
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#include <KernelExport.h>
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#include <Drivers.h>
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#include <Errors.h>
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#include <string.h>
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#include <stdio.h>
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#include <stdlib.h>
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#include <kernel/arch/x86/arch_cpu.h>
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#include <ACPI.h>
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#include "enhanced_speedstep.h"
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#include <condition_variable.h>
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#include "frequency.h"
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#define EST_MODULE_NAME "drivers/power/enhanced_speedstep/driver_v1"
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#define EST_DEVICE_MODULE_NAME "drivers/power/enhanced_speedstep/device_v1"
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/* Base Namespace devices are published to */
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#define EST_BASENAME "power/enhanced_speedstep/%d"
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// name of pnp generator of path ids
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#define EST_PATHID_GENERATOR "enhanced_speedstep/path_id"
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static device_manager_info *sDeviceManager;
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static ConditionVariable sFrequencyCondition;
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static int32 sCurrentID;
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static status_t
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est_read(void* _cookie, off_t position, void *buffer, size_t* numBytes)
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{
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if (*numBytes < 1)
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return B_IO_ERROR;
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est_cookie *device = (est_cookie *)_cookie;
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if (position == 0) {
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size_t max_len = *numBytes;
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char *str = (char *)buffer;
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snprintf(str, max_len, "CPU Frequency states:\n");
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max_len-= strlen(str);
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str += strlen(str);
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freq_info *freqsInfo = device->available_states;
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freq_info *f;
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for (f = freqsInfo; f->frequency != 0; f++) {
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snprintf(str, max_len, " Frequency %hu, Volts %hu, Power %i, "
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"Latency %i, id %hu\n", f->frequency, f->volts, f->power, f->id,
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EST_TRANS_LAT);
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max_len-= strlen(str);
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str += strlen(str);
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}
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freq_info *f2 = est_get_current(freqsInfo);
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if (f2) {
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snprintf(str, max_len, "\nCurrent State: Frequency %hu, Volts %hu, "
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"Power %i, Latency %i\n", f2->frequency, f2->volts, f2->power,
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EST_TRANS_LAT);
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}
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*numBytes = strlen((char *)buffer);
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} else {
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*numBytes = 0;
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}
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return B_OK;
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}
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static status_t
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est_write(void* cookie, off_t position, const void* buffer, size_t* numBytes)
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{
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return B_ERROR;
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}
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status_t
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est_control(void* _cookie, uint32 op, void* arg, size_t len)
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{
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est_cookie* device = (est_cookie*)_cookie;
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status_t err = B_ERROR;
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uint32* magicId;
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uint16* id;
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freq_info* freqInfo = NULL;
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switch (op) {
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case IDENTIFY_DEVICE:
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if (len < sizeof(uint32))
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return B_IO_ERROR;
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magicId = (uint32*)arg;
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*magicId = kMagicFreqID;
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err = B_OK;
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break;
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case GET_CPU_FREQ_STATES:
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if (len < sizeof(freq_info) * (device->number_states + 1))
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return B_IO_ERROR;
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freqInfo = (freq_info*)arg;
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user_memcpy(freqInfo, device->available_states,
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sizeof(freq_info) * (device->number_states + 1));
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err = B_OK;
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break;
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case GET_CURENT_CPU_FREQ_STATE:
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if (len < sizeof(uint16))
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return B_IO_ERROR;
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freqInfo = est_get_current(device->available_states);
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if (!freqInfo)
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return B_ERROR;
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atomic_set(&sCurrentID, freqInfo->id);
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*((uint16*)arg) = freqInfo->id;
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err = B_OK;
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break;
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case SET_CPU_FREQ_STATE:
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if (len < sizeof(uint16))
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return B_IO_ERROR;
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id = (uint16*)arg;
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err = est_set_id16(*id);
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if (err == B_OK) {
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atomic_set(&sCurrentID, *id);
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sFrequencyCondition.NotifyAll();
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}
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break;
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case WATCH_CPU_FREQ:
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if (len < sizeof(uint16))
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return B_IO_ERROR;
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sFrequencyCondition.Wait();
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if (atomic_get(&(device->stop_watching))) {
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atomic_set(&(device->stop_watching), 0);
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err = B_ERROR;
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} else {
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*((uint16*)arg) = atomic_get(&sCurrentID);
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err = B_OK;
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}
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break;
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case STOP_WATCHING_CPU_FREQ:
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atomic_set(&(device->stop_watching), 1);
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sFrequencyCondition.NotifyAll();
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err = B_OK;
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break;
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}
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return err;
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}
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static status_t
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est_open(void *initCookie, const char *path, int flags, void** cookie)
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{
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TRACE("est: open\n");
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est_cookie *device;
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device = (est_cookie *)calloc(1, sizeof(est_cookie));
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if (device == NULL)
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return B_NO_MEMORY;
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*cookie = device;
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device_node *node = (device_node *)initCookie;
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device->node = node;
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device_node *parent;
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parent = sDeviceManager->get_parent_node(node);
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sDeviceManager->get_driver(parent, (driver_module_info **)&device->acpi,
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(void **)&device->acpi_cookie);
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sDeviceManager->put_node(parent);
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device->stop_watching = 0;
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// enable enhanced speedstep
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uint64 msrMisc = x86_read_msr(MSR_MISC);
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if ((msrMisc & MSR_EST_ENABLED) == 0) {
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TRACE("est: enable enhanced speedstep\n");
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x86_write_msr(MSR_MISC, msrMisc | MSR_EST_ENABLED);
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uint64 msrMisc = x86_read_msr(MSR_MISC);
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if ((msrMisc & MSR_EST_ENABLED) == 0) {
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TRACE("est: enable enhanced speedstep failed\n");
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return B_ERROR;
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}
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}
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// get freq_info
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if (est_get_info(&(device->available_states)) != B_OK)
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return B_ERROR;
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freq_info *freqsInfo = device->available_states;
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// count number of states
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TRACE("est: frequency info:\n");
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freq_info *f;
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device->number_states = 0;
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for (f = freqsInfo; f->frequency != 0; f++) {
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TRACE("est: Frequency %u, Volts %u, Power %i, Latency %u, id %u\n",
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f->frequency, f->volts, f->power, f->id, EST_TRANS_LAT);
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device->number_states++;
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}
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// print current frequency
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freq_info *f2 = est_get_current(freqsInfo);
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if (f2) {
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TRACE("est: Current Frequency %u, Volts %u, Power %i, Latency %u\n",
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f2->frequency, f2->volts, f2->power, EST_TRANS_LAT);
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}
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return B_OK;
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}
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static status_t
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est_close(void* cookie)
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{
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est_cookie *device = (est_cookie*)cookie;
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free(device);
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return B_OK;
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}
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static status_t
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est_free(void* cookie)
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{
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return B_OK;
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}
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// #pragma mark - driver module API
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static float
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est_support(device_node *parent)
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{
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// make sure parent is really the ACPI bus manager
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const char *bus;
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if (sDeviceManager->get_attr_string(parent, B_DEVICE_BUS, &bus, false))
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return -1;
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if (strcmp(bus, "acpi"))
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return 0.0;
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// check whether it's really a cpu Device
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uint32 deviceType;
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if (sDeviceManager->get_attr_uint32(parent, ACPI_DEVICE_TYPE_ITEM,
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&deviceType, false) != B_OK
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|| deviceType != ACPI_TYPE_PROCESSOR) {
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return 0.0;
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}
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// check if cpu support est
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uint32 cpuNum = 0;
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system_info sysInfo;
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if (get_system_info(&sysInfo) != B_OK)
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return 0.0;
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TRACE("est: cpu_type: %u vendor %u model %u\n", sysInfo.cpu_type,
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sysInfo.cpu_type & B_CPU_x86_VENDOR_MASK, sysInfo.cpu_type & 0x00FF);
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if ((sysInfo.cpu_type & B_CPU_x86_VENDOR_MASK) != B_CPU_INTEL_x86)
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return 0.0;
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// TODO: Make the code SMP safe!
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if (sysInfo.cpu_count > 1)
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return 0.0;
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cpuid_info info;
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if (get_cpuid(&info, 1, cpuNum) != B_OK)
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return 0.0;
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TRACE("est: extended_features: %i\n", int(info.eax_1.extended_features));
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// check for enhanced speedstep
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if ((info.eax_1.extended_features & IA32_FEATURE_EXT_EST) == 0)
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return 0.0;
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TRACE("est: supported\n");
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return 0.6;
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}
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static status_t
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est_register_device(device_node *node)
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{
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device_attr attrs[] = {
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{ B_DEVICE_PRETTY_NAME, B_STRING_TYPE,
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{ string: "ACPI Enhanced Speedstep" }},
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{ NULL }
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};
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return sDeviceManager->register_node(node, EST_MODULE_NAME, attrs,
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NULL, NULL);
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}
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static status_t
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est_init_driver(device_node *node, void **_driverCookie)
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{
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*_driverCookie = node;
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sFrequencyCondition.Init(NULL, "frequency cv");
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sCurrentID = -1;
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return B_OK;
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}
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static void
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est_uninit_driver(void *driverCookie)
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{
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}
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static status_t
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est_register_child_devices(void *_cookie)
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{
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device_node *node = (device_node*)_cookie;
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|
||||||
int pathID = sDeviceManager->create_id(EST_PATHID_GENERATOR);
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||||||
if (pathID < 0) {
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||||||
TRACE("est_register_child_devices: couldn't create a path_id\n");
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||||||
return B_ERROR;
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|
||||||
}
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|
||||||
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|
||||||
char name[128];
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|
||||||
snprintf(name, sizeof(name), EST_BASENAME, pathID);
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|
||||||
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|
||||||
return sDeviceManager->publish_device(node, name, EST_DEVICE_MODULE_NAME);
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|
||||||
}
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|
||||||
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|
||||||
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|
||||||
static status_t
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|
||||||
est_init_device(void *driverCookie, void **cookie)
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|
||||||
{
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|
||||||
// driverCookie is the device node
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|
||||||
*cookie = driverCookie;
|
|
||||||
return B_OK;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
static void
|
|
||||||
est_uninit_device(void *_cookie)
|
|
||||||
{
|
|
||||||
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
|
|
||||||
module_dependency module_dependencies[] = {
|
|
||||||
{ B_DEVICE_MANAGER_MODULE_NAME, (module_info **)&sDeviceManager },
|
|
||||||
{}
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
driver_module_info est_driver_module = {
|
|
||||||
{
|
|
||||||
EST_MODULE_NAME,
|
|
||||||
0,
|
|
||||||
NULL
|
|
||||||
},
|
|
||||||
|
|
||||||
est_support,
|
|
||||||
est_register_device,
|
|
||||||
est_init_driver,
|
|
||||||
est_uninit_driver,
|
|
||||||
est_register_child_devices,
|
|
||||||
NULL, // rescan
|
|
||||||
NULL, // removed
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
struct device_module_info est_device_module = {
|
|
||||||
{
|
|
||||||
EST_DEVICE_MODULE_NAME,
|
|
||||||
0,
|
|
||||||
NULL
|
|
||||||
},
|
|
||||||
|
|
||||||
est_init_device,
|
|
||||||
est_uninit_device,
|
|
||||||
NULL,
|
|
||||||
|
|
||||||
est_open,
|
|
||||||
est_close,
|
|
||||||
est_free,
|
|
||||||
est_read,
|
|
||||||
est_write,
|
|
||||||
NULL,
|
|
||||||
est_control,
|
|
||||||
|
|
||||||
NULL,
|
|
||||||
NULL
|
|
||||||
};
|
|
||||||
|
|
||||||
module_info *modules[] = {
|
|
||||||
(module_info *)&est_driver_module,
|
|
||||||
(module_info *)&est_device_module,
|
|
||||||
NULL
|
|
||||||
};
|
|
||||||
@@ -1,29 +0,0 @@
|
|||||||
#ifndef _EST_H
|
|
||||||
#define _EST_H
|
|
||||||
|
|
||||||
#include <KernelExport.h>
|
|
||||||
#include <ACPI.h>
|
|
||||||
|
|
||||||
#include "frequency.h"
|
|
||||||
|
|
||||||
// Model Specific Register
|
|
||||||
#define MSR_MISC 0x1a0
|
|
||||||
#define MSR_EST_ENABLED (1<<16)
|
|
||||||
|
|
||||||
|
|
||||||
struct est_cookie {
|
|
||||||
// this three variables are not needed yet but helpfull when extend this
|
|
||||||
// driver to use acpi
|
|
||||||
device_node *node;
|
|
||||||
acpi_device_module_info *acpi;
|
|
||||||
acpi_device acpi_cookie;
|
|
||||||
|
|
||||||
// array of states don't delete it
|
|
||||||
freq_info* available_states;
|
|
||||||
uint8 number_states;
|
|
||||||
|
|
||||||
int32 stop_watching;
|
|
||||||
};
|
|
||||||
|
|
||||||
|
|
||||||
#endif /* _EST_H */
|
|
||||||
@@ -1,202 +0,0 @@
|
|||||||
/*
|
|
||||||
* Copyright 2009, Haiku, Inc. All Rights Reserved.
|
|
||||||
* Distributed under the terms of the MIT License.
|
|
||||||
*
|
|
||||||
* Authors:
|
|
||||||
* Clemens Zeidler, [email protected]
|
|
||||||
*/
|
|
||||||
|
|
||||||
|
|
||||||
#include "frequency.h"
|
|
||||||
|
|
||||||
#include <arch/x86/arch_cpu.h>
|
|
||||||
|
|
||||||
#include <stdio.h>
|
|
||||||
#include <stdlib.h>
|
|
||||||
#include <string.h>
|
|
||||||
|
|
||||||
|
|
||||||
void
|
|
||||||
est_get_id16(uint16* _id16)
|
|
||||||
{
|
|
||||||
*_id16 = x86_read_msr(MSR_GET_FREQ_STATE) & 0xffff;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
status_t
|
|
||||||
est_set_id16(uint16 id16, bool needCheck)
|
|
||||||
{
|
|
||||||
uint64 msr;
|
|
||||||
|
|
||||||
// Read the current register, mask out the old, set the new id.
|
|
||||||
msr = x86_read_msr(MSR_GET_FREQ_STATE);
|
|
||||||
msr = (msr & ~0xffff) | id16;
|
|
||||||
x86_write_msr(MSR_SET_FREQ_STATE, msr);
|
|
||||||
|
|
||||||
if (needCheck) {
|
|
||||||
// Wait a short while for the new setting. XXX Is this necessary?
|
|
||||||
snooze(EST_TRANS_LAT);
|
|
||||||
|
|
||||||
uint16 newID16;
|
|
||||||
est_get_id16(&newID16);
|
|
||||||
if (newID16 != id16)
|
|
||||||
return B_ERROR;
|
|
||||||
TRACE("EST: set frequency ok, id %i\n", id16);
|
|
||||||
}
|
|
||||||
return B_OK;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
freq_info*
|
|
||||||
est_get_current(freq_info* list)
|
|
||||||
{
|
|
||||||
// Try a few times to get a valid value. Sometimes, if the CPU
|
|
||||||
// is in the middle of an asynchronous transition (i.e., P4TCC),
|
|
||||||
// we get a temporary invalid result.
|
|
||||||
for (uint32 i = 0; i < 5; i++) {
|
|
||||||
uint16 id16;
|
|
||||||
est_get_id16(&id16);
|
|
||||||
|
|
||||||
for (freq_info* info = list; info->id != 0; info++) {
|
|
||||||
if (info->id == id16)
|
|
||||||
return info;
|
|
||||||
}
|
|
||||||
|
|
||||||
snooze(100);
|
|
||||||
}
|
|
||||||
return NULL;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
status_t
|
|
||||||
est_get_info(freq_info** _frequencyInfos)
|
|
||||||
{
|
|
||||||
uint64 msr = x86_read_msr(MSR_GET_FREQ_STATE);
|
|
||||||
status_t status = est_table_info(msr, _frequencyInfos);
|
|
||||||
if (status != B_OK) {
|
|
||||||
TRACE("EST: Get frequency table from model specific register\n");
|
|
||||||
status = est_msr_info(msr, _frequencyInfos);
|
|
||||||
}
|
|
||||||
|
|
||||||
if (status != B_OK) {
|
|
||||||
TRACE("est: CPU supports Enhanced Speedstep, but is not recognized.\n");
|
|
||||||
return status;
|
|
||||||
}
|
|
||||||
|
|
||||||
return B_OK;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
status_t
|
|
||||||
est_table_info(uint64 msr, freq_info** _frequencyInfos)
|
|
||||||
{
|
|
||||||
// Find a table which matches (vendor, id32).
|
|
||||||
system_info info;
|
|
||||||
if (get_system_info(&info) != B_OK)
|
|
||||||
return B_ERROR;
|
|
||||||
|
|
||||||
ss_cpu_info* cpuInfo;
|
|
||||||
uint32 id = msr >> 32;
|
|
||||||
for (cpuInfo = ESTprocs; cpuInfo->id32 != 0; cpuInfo++) {
|
|
||||||
if (cpuInfo->vendor_id == uint32(info.cpu_type & B_CPU_x86_VENDOR_MASK)
|
|
||||||
&& cpuInfo->id32 == id)
|
|
||||||
break;
|
|
||||||
}
|
|
||||||
if (cpuInfo->id32 == 0)
|
|
||||||
return B_ERROR;
|
|
||||||
|
|
||||||
// Make sure the current setpoint is valid.
|
|
||||||
if (est_get_current(cpuInfo->freqtab) == NULL) {
|
|
||||||
TRACE("current setting not found in table\n");
|
|
||||||
return B_ERROR;
|
|
||||||
}
|
|
||||||
|
|
||||||
*_frequencyInfos = cpuInfo->freqtab;
|
|
||||||
return B_OK;
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
bool
|
|
||||||
bus_speed_ok(int bus)
|
|
||||||
{
|
|
||||||
switch (bus) {
|
|
||||||
case 100:
|
|
||||||
case 133:
|
|
||||||
case 166:
|
|
||||||
case 333:
|
|
||||||
return true;
|
|
||||||
default:
|
|
||||||
return false;
|
|
||||||
}
|
|
||||||
}
|
|
||||||
|
|
||||||
|
|
||||||
/*! Flesh out a simple rate table containing the high and low frequencies
|
|
||||||
based on the current clock speed and the upper 32 bits of the MSR.
|
|
||||||
*/
|
|
||||||
status_t
|
|
||||||
est_msr_info(uint64 msr, freq_info** _frequencyInfos)
|
|
||||||
{
|
|
||||||
// Figure out the bus clock.
|
|
||||||
system_info info;
|
|
||||||
if (get_system_info(&info) != B_OK)
|
|
||||||
return B_ERROR;
|
|
||||||
|
|
||||||
int32 freq = info.cpu_clock_speed / 1000000;
|
|
||||||
uint16 id = msr >> 32;
|
|
||||||
int32 bus = 0;
|
|
||||||
if (id >> 8)
|
|
||||||
bus = freq / (id >> 8);
|
|
||||||
|
|
||||||
TRACE("est: Guessed bus clock (high) of %d MHz\n", int(bus));
|
|
||||||
if (!bus_speed_ok(bus)) {
|
|
||||||
// We may be running on the low frequency.
|
|
||||||
id = msr >> 48;
|
|
||||||
if (id >> 8)
|
|
||||||
bus = freq / (id >> 8);
|
|
||||||
TRACE("est: Guessed bus clock (low) of %d MHz\n", int(bus));
|
|
||||||
if (!bus_speed_ok(bus))
|
|
||||||
return B_ERROR;
|
|
||||||
|
|
||||||
// Calculate high frequency.
|
|
||||||
id = msr >> 32;
|
|
||||||
freq = ((id >> 8) & 0xff) * bus;
|
|
||||||
}
|
|
||||||
|
|
||||||
// Fill out a new freq table containing just the high and low freqs.
|
|
||||||
freq_info* frequencyInfo = (freq_info*)malloc(sizeof(freq_info) * 3);
|
|
||||||
if (frequencyInfo == NULL)
|
|
||||||
return B_NO_MEMORY;
|
|
||||||
|
|
||||||
memset(frequencyInfo, 0, sizeof(freq_info) * 3);
|
|
||||||
|
|
||||||
// First, the high frequency.
|
|
||||||
int32 volts = id & 0xff;
|
|
||||||
if (volts != 0) {
|
|
||||||
volts <<= 4;
|
|
||||||
volts += 700;
|
|
||||||
}
|
|
||||||
frequencyInfo[0].frequency = freq;
|
|
||||||
frequencyInfo[0].volts = volts;
|
|
||||||
frequencyInfo[0].id = id;
|
|
||||||
frequencyInfo[0].power = CPUFREQ_VAL_UNKNOWN;
|
|
||||||
TRACE("Guessed high setting of %d MHz @ %d Mv\n", int(freq), int(volts));
|
|
||||||
|
|
||||||
// Second, the low frequency.
|
|
||||||
id = msr >> 48;
|
|
||||||
freq = ((id >> 8) & 0xff) * bus;
|
|
||||||
volts = id & 0xff;
|
|
||||||
if (volts != 0) {
|
|
||||||
volts <<= 4;
|
|
||||||
volts += 700;
|
|
||||||
}
|
|
||||||
frequencyInfo[1].frequency = freq;
|
|
||||||
frequencyInfo[1].volts = volts;
|
|
||||||
frequencyInfo[1].id = id;
|
|
||||||
frequencyInfo[1].power = CPUFREQ_VAL_UNKNOWN;
|
|
||||||
TRACE("Guessed low setting of %d MHz @ %d Mv\n", int(freq), int(volts));
|
|
||||||
|
|
||||||
// Table is already terminated due to M_ZERO.
|
|
||||||
*_frequencyInfos = frequencyInfo;
|
|
||||||
return B_OK;
|
|
||||||
}
|
|
||||||
@@ -1,852 +0,0 @@
|
|||||||
#ifndef FREQ_TABLE_H
|
|
||||||
#define FREQ_TABLE_H
|
|
||||||
|
|
||||||
#include <OS.h>
|
|
||||||
#include <KernelExport.h>
|
|
||||||
#include <Errors.h>
|
|
||||||
|
|
||||||
#include "device/power_managment.h"
|
|
||||||
|
|
||||||
#define TRACE_EST
|
|
||||||
#ifdef TRACE_EST
|
|
||||||
# define TRACE(x...) dprintf(x)
|
|
||||||
#else
|
|
||||||
# define TRACE(x...)
|
|
||||||
#endif
|
|
||||||
|
|
||||||
// this code is taken from freeBSD
|
|
||||||
|
|
||||||
#define MSR_GET_FREQ_STATE 0x198
|
|
||||||
#define MSR_SET_FREQ_STATE 0x199
|
|
||||||
|
|
||||||
/* Estimate in microseconds of latency for performing a transition. */
|
|
||||||
#define EST_TRANS_LAT 1000
|
|
||||||
|
|
||||||
/* Identifying characteristics of a processor and supported frequencies. */
|
|
||||||
typedef struct {
|
|
||||||
const uint32 vendor_id;
|
|
||||||
uint32 id32;
|
|
||||||
freq_info *freqtab;
|
|
||||||
} ss_cpu_info;
|
|
||||||
|
|
||||||
|
|
||||||
status_t est_get_info(freq_info **freqsInfo);
|
|
||||||
status_t est_table_info(uint64 msr, freq_info **freqs);
|
|
||||||
status_t est_msr_info(uint64 msr, freq_info **freqs);
|
|
||||||
|
|
||||||
freq_info* est_get_current(freq_info *freq_list);
|
|
||||||
void est_get_id16(uint16 *id16_p);
|
|
||||||
status_t est_set_id16(uint16 id16, bool need_check = false);
|
|
||||||
|
|
||||||
/* Convert MHz and mV into IDs for passing to the MSR. */
|
|
||||||
#define ID16(MHz, mV, bus_clk) \
|
|
||||||
(((MHz / bus_clk) << 8) | ((mV ? mV - 700 : 0) >> 4))
|
|
||||||
#define ID32(MHz_hi, mV_hi, MHz_lo, mV_lo, bus_clk) \
|
|
||||||
((ID16(MHz_lo, mV_lo, bus_clk) << 16) | (ID16(MHz_hi, mV_hi, bus_clk)))
|
|
||||||
|
|
||||||
/* Format for storing IDs in our table. */
|
|
||||||
#define CPUFREQ_VAL_UNKNOWN (-1)
|
|
||||||
#define CPU_VENDOR_INTEL B_CPU_INTEL_x86
|
|
||||||
#define CPU_VENDOR_CENTAUR B_CPU_VIA_IDT_x86
|
|
||||||
|
|
||||||
#define FREQ_INFO_PWR(MHz, mV, bus_clk, mW) \
|
|
||||||
{ MHz, mV, ID16(MHz, mV, bus_clk), mW }
|
|
||||||
#define FREQ_INFO(MHz, mV, bus_clk) \
|
|
||||||
FREQ_INFO_PWR(MHz, mV, bus_clk, CPUFREQ_VAL_UNKNOWN)
|
|
||||||
#define INTEL(tab, zhi, vhi, zlo, vlo, bus_clk) \
|
|
||||||
{ CPU_VENDOR_INTEL, ID32(zhi, vhi, zlo, vlo, bus_clk), tab }
|
|
||||||
#define CENTAUR(tab, zhi, vhi, zlo, vlo, bus_clk) \
|
|
||||||
{ CPU_VENDOR_CENTAUR, ID32(zhi, vhi, zlo, vlo, bus_clk), tab }
|
|
||||||
|
|
||||||
/* Default bus clock value for Centrino processors. */
|
|
||||||
#define INTEL_BUS_CLK 100
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Frequency (MHz) and voltage (mV) settings. Data from the
|
|
||||||
* Intel Pentium M Processor Datasheet (Order Number 252612), Table 5.
|
|
||||||
*
|
|
||||||
* Dothan processors have multiple VID#s with different settings for
|
|
||||||
* each VID#. Since we can't uniquely identify this info
|
|
||||||
* without undisclosed methods from Intel, we can't support newer
|
|
||||||
* processors with this table method. If ACPI Px states are supported,
|
|
||||||
* we get info from them.
|
|
||||||
*/
|
|
||||||
static freq_info PM17_130[] = {
|
|
||||||
/* 130nm 1.70GHz Pentium M */
|
|
||||||
FREQ_INFO(1700, 1484, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1400, 1308, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1200, 1228, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 1004, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 956, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info PM16_130[] = {
|
|
||||||
/* 130nm 1.60GHz Pentium M */
|
|
||||||
FREQ_INFO(1600, 1484, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1400, 1420, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1200, 1276, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 1164, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 956, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info PM15_130[] = {
|
|
||||||
/* 130nm 1.50GHz Pentium M */
|
|
||||||
FREQ_INFO(1500, 1484, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1400, 1452, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1200, 1356, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 1228, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 1116, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 956, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info PM14_130[] = {
|
|
||||||
/* 130nm 1.40GHz Pentium M */
|
|
||||||
FREQ_INFO(1400, 1484, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1200, 1436, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 1308, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 1180, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 956, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info PM13_130[] = {
|
|
||||||
/* 130nm 1.30GHz Pentium M */
|
|
||||||
FREQ_INFO(1300, 1388, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1200, 1356, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 1292, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 1260, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 956, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info PM13_LV_130[] = {
|
|
||||||
/* 130nm 1.30GHz Low Voltage Pentium M */
|
|
||||||
FREQ_INFO(1300, 1180, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1100, 1100, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 1020, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 900, 1004, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 988, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 956, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info PM12_LV_130[] = {
|
|
||||||
/* 130 nm 1.20GHz Low Voltage Pentium M */
|
|
||||||
FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1100, 1164, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 900, 1020, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 1004, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 956, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info PM11_LV_130[] = {
|
|
||||||
/* 130 nm 1.10GHz Low Voltage Pentium M */
|
|
||||||
FREQ_INFO(1100, 1180, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 1164, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 900, 1100, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 1020, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 956, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info PM11_ULV_130[] = {
|
|
||||||
/* 130 nm 1.10GHz Ultra Low Voltage Pentium M */
|
|
||||||
FREQ_INFO(1100, 1004, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 988, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 900, 972, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 956, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 844, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info PM10_ULV_130[] = {
|
|
||||||
/* 130 nm 1.00GHz Ultra Low Voltage Pentium M */
|
|
||||||
FREQ_INFO(1000, 1004, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 900, 988, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 972, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 844, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 0, 0, 1),
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* Data from "Intel Pentium M Processor on 90nm Process with
|
|
||||||
* 2-MB L2 Cache Datasheet", Order Number 302189, Table 5.
|
|
||||||
*/
|
|
||||||
static freq_info PM_765A_90[] = {
|
|
||||||
/* 90 nm 2.10GHz Pentium M, VID #A */
|
|
||||||
FREQ_INFO(2100, 1340, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1800, 1276, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1600, 1228, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 988, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info PM_765B_90[] = {
|
|
||||||
/* 90 nm 2.10GHz Pentium M, VID #B */
|
|
||||||
FREQ_INFO(2100, 1324, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1800, 1260, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1600, 1212, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 988, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info PM_765C_90[] = {
|
|
||||||
/* 90 nm 2.10GHz Pentium M, VID #C */
|
|
||||||
FREQ_INFO(2100, 1308, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1800, 1244, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1600, 1212, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1400, 1164, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1200, 1116, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 988, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info PM_765E_90[] = {
|
|
||||||
/* 90 nm 2.10GHz Pentium M, VID #E */
|
|
||||||
FREQ_INFO(2100, 1356, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1800, 1292, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1600, 1244, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1400, 1196, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1200, 1148, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 988, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info PM_755A_90[] = {
|
|
||||||
/* 90 nm 2.00GHz Pentium M, VID #A */
|
|
||||||
FREQ_INFO(2000, 1340, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1800, 1292, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1600, 1244, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1400, 1196, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1200, 1148, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 988, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info PM_755B_90[] = {
|
|
||||||
/* 90 nm 2.00GHz Pentium M, VID #B */
|
|
||||||
FREQ_INFO(2000, 1324, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1800, 1276, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1600, 1228, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 988, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info PM_755C_90[] = {
|
|
||||||
/* 90 nm 2.00GHz Pentium M, VID #C */
|
|
||||||
FREQ_INFO(2000, 1308, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1800, 1276, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1600, 1228, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 988, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info PM_755D_90[] = {
|
|
||||||
/* 90 nm 2.00GHz Pentium M, VID #D */
|
|
||||||
FREQ_INFO(2000, 1276, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1800, 1244, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1600, 1196, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1400, 1164, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1200, 1116, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 988, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info PM_745A_90[] = {
|
|
||||||
/* 90 nm 1.80GHz Pentium M, VID #A */
|
|
||||||
FREQ_INFO(1800, 1340, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1600, 1292, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1400, 1228, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 988, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info PM_745B_90[] = {
|
|
||||||
/* 90 nm 1.80GHz Pentium M, VID #B */
|
|
||||||
FREQ_INFO(1800, 1324, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1600, 1276, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1400, 1212, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 988, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info PM_745C_90[] = {
|
|
||||||
/* 90 nm 1.80GHz Pentium M, VID #C */
|
|
||||||
FREQ_INFO(1800, 1308, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1600, 1260, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1400, 1212, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1200, 1148, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 988, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info PM_745D_90[] = {
|
|
||||||
/* 90 nm 1.80GHz Pentium M, VID #D */
|
|
||||||
FREQ_INFO(1800, 1276, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1600, 1228, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1400, 1180, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1200, 1132, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 1084, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 1036, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 988, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info PM_735A_90[] = {
|
|
||||||
/* 90 nm 1.70GHz Pentium M, VID #A */
|
|
||||||
FREQ_INFO(1700, 1340, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1400, 1244, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 988, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info PM_735B_90[] = {
|
|
||||||
/* 90 nm 1.70GHz Pentium M, VID #B */
|
|
||||||
FREQ_INFO(1700, 1324, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1400, 1244, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 988, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info PM_735C_90[] = {
|
|
||||||
/* 90 nm 1.70GHz Pentium M, VID #C */
|
|
||||||
FREQ_INFO(1700, 1308, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1400, 1228, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 988, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info PM_735D_90[] = {
|
|
||||||
/* 90 nm 1.70GHz Pentium M, VID #D */
|
|
||||||
FREQ_INFO(1700, 1276, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1400, 1212, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1200, 1148, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 1100, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 988, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info PM_725A_90[] = {
|
|
||||||
/* 90 nm 1.60GHz Pentium M, VID #A */
|
|
||||||
FREQ_INFO(1600, 1340, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1400, 1276, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1200, 1212, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 1132, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 988, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info PM_725B_90[] = {
|
|
||||||
/* 90 nm 1.60GHz Pentium M, VID #B */
|
|
||||||
FREQ_INFO(1600, 1324, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1400, 1260, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1200, 1196, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 1132, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 988, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info PM_725C_90[] = {
|
|
||||||
/* 90 nm 1.60GHz Pentium M, VID #C */
|
|
||||||
FREQ_INFO(1600, 1308, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1400, 1244, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 988, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info PM_725D_90[] = {
|
|
||||||
/* 90 nm 1.60GHz Pentium M, VID #D */
|
|
||||||
FREQ_INFO(1600, 1276, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1400, 1228, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1200, 1164, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 988, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info PM_715A_90[] = {
|
|
||||||
/* 90 nm 1.50GHz Pentium M, VID #A */
|
|
||||||
FREQ_INFO(1500, 1340, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1200, 1228, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 1148, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 988, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info PM_715B_90[] = {
|
|
||||||
/* 90 nm 1.50GHz Pentium M, VID #B */
|
|
||||||
FREQ_INFO(1500, 1324, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1200, 1212, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 1148, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 988, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info PM_715C_90[] = {
|
|
||||||
/* 90 nm 1.50GHz Pentium M, VID #C */
|
|
||||||
FREQ_INFO(1500, 1308, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1200, 1212, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 1132, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 1068, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 988, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info PM_715D_90[] = {
|
|
||||||
/* 90 nm 1.50GHz Pentium M, VID #D */
|
|
||||||
FREQ_INFO(1500, 1276, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1200, 1180, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 1116, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 1052, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 988, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info PM_778_90[] = {
|
|
||||||
/* 90 nm 1.60GHz Low Voltage Pentium M */
|
|
||||||
FREQ_INFO(1600, 1116, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1500, 1116, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1400, 1100, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1300, 1084, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1200, 1068, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1100, 1052, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 1052, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 900, 1036, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 1020, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 988, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info PM_758_90[] = {
|
|
||||||
/* 90 nm 1.50GHz Low Voltage Pentium M */
|
|
||||||
FREQ_INFO(1500, 1116, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1400, 1116, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1300, 1100, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1200, 1084, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1100, 1068, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 1052, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 900, 1036, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 1020, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 988, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info PM_738_90[] = {
|
|
||||||
/* 90 nm 1.40GHz Low Voltage Pentium M */
|
|
||||||
FREQ_INFO(1400, 1116, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1300, 1116, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1200, 1100, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1100, 1068, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 1052, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 900, 1036, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 1020, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 988, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info PM_773G_90[] = {
|
|
||||||
/* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #G */
|
|
||||||
FREQ_INFO(1300, 956, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1200, 940, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1100, 924, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 908, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 900, 876, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 860, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 812, INTEL_BUS_CLK),
|
|
||||||
};
|
|
||||||
static freq_info PM_773H_90[] = {
|
|
||||||
/* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #H */
|
|
||||||
FREQ_INFO(1300, 940, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1200, 924, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1100, 908, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 892, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 900, 876, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 860, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 812, INTEL_BUS_CLK),
|
|
||||||
};
|
|
||||||
static freq_info PM_773I_90[] = {
|
|
||||||
/* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #I */
|
|
||||||
FREQ_INFO(1300, 924, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1200, 908, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1100, 892, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 876, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 900, 860, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 844, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 812, INTEL_BUS_CLK),
|
|
||||||
};
|
|
||||||
static freq_info PM_773J_90[] = {
|
|
||||||
/* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #J */
|
|
||||||
FREQ_INFO(1300, 908, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1200, 908, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1100, 892, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 876, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 900, 860, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 844, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 812, INTEL_BUS_CLK),
|
|
||||||
};
|
|
||||||
static freq_info PM_773K_90[] = {
|
|
||||||
/* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #K */
|
|
||||||
FREQ_INFO(1300, 892, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1200, 892, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1100, 876, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 860, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 900, 860, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 844, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 812, INTEL_BUS_CLK),
|
|
||||||
};
|
|
||||||
static freq_info PM_773L_90[] = {
|
|
||||||
/* 90 nm 1.30GHz Ultra Low Voltage Pentium M, VID #L */
|
|
||||||
FREQ_INFO(1300, 876, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1200, 876, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1100, 860, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 860, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 900, 844, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 844, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 812, INTEL_BUS_CLK),
|
|
||||||
};
|
|
||||||
static freq_info PM_753G_90[] = {
|
|
||||||
/* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #G */
|
|
||||||
FREQ_INFO(1200, 956, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1100, 940, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 908, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 900, 892, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 860, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 812, INTEL_BUS_CLK),
|
|
||||||
};
|
|
||||||
static freq_info PM_753H_90[] = {
|
|
||||||
/* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #H */
|
|
||||||
FREQ_INFO(1200, 940, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1100, 924, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 908, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 900, 876, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 860, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 812, INTEL_BUS_CLK),
|
|
||||||
};
|
|
||||||
static freq_info PM_753I_90[] = {
|
|
||||||
/* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #I */
|
|
||||||
FREQ_INFO(1200, 924, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1100, 908, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 892, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 900, 876, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 860, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 812, INTEL_BUS_CLK),
|
|
||||||
};
|
|
||||||
static freq_info PM_753J_90[] = {
|
|
||||||
/* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #J */
|
|
||||||
FREQ_INFO(1200, 908, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1100, 892, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 876, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 900, 860, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 844, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 812, INTEL_BUS_CLK),
|
|
||||||
};
|
|
||||||
static freq_info PM_753K_90[] = {
|
|
||||||
/* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #K */
|
|
||||||
FREQ_INFO(1200, 892, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1100, 892, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 876, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 900, 860, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 844, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 812, INTEL_BUS_CLK),
|
|
||||||
};
|
|
||||||
static freq_info PM_753L_90[] = {
|
|
||||||
/* 90 nm 1.20GHz Ultra Low Voltage Pentium M, VID #L */
|
|
||||||
FREQ_INFO(1200, 876, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1100, 876, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 860, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 900, 844, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 844, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 812, INTEL_BUS_CLK),
|
|
||||||
};
|
|
||||||
|
|
||||||
static freq_info PM_733JG_90[] = {
|
|
||||||
/* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #G */
|
|
||||||
FREQ_INFO(1100, 956, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 940, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 900, 908, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 876, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 812, INTEL_BUS_CLK),
|
|
||||||
};
|
|
||||||
static freq_info PM_733JH_90[] = {
|
|
||||||
/* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #H */
|
|
||||||
FREQ_INFO(1100, 940, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 924, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 900, 892, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 876, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 812, INTEL_BUS_CLK),
|
|
||||||
};
|
|
||||||
static freq_info PM_733JI_90[] = {
|
|
||||||
/* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #I */
|
|
||||||
FREQ_INFO(1100, 924, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 908, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 900, 892, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 860, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 812, INTEL_BUS_CLK),
|
|
||||||
};
|
|
||||||
static freq_info PM_733JJ_90[] = {
|
|
||||||
/* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #J */
|
|
||||||
FREQ_INFO(1100, 908, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 892, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 900, 876, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 860, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 812, INTEL_BUS_CLK),
|
|
||||||
};
|
|
||||||
static freq_info PM_733JK_90[] = {
|
|
||||||
/* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #K */
|
|
||||||
FREQ_INFO(1100, 892, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 876, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 900, 860, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 844, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 812, INTEL_BUS_CLK),
|
|
||||||
};
|
|
||||||
static freq_info PM_733JL_90[] = {
|
|
||||||
/* 90 nm 1.10GHz Ultra Low Voltage Pentium M, VID #L */
|
|
||||||
FREQ_INFO(1100, 876, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 876, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 900, 860, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 844, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 812, INTEL_BUS_CLK),
|
|
||||||
};
|
|
||||||
static freq_info PM_733_90[] = {
|
|
||||||
/* 90 nm 1.10GHz Ultra Low Voltage Pentium M */
|
|
||||||
FREQ_INFO(1100, 940, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO(1000, 924, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 900, 892, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 876, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 812, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info PM_723_90[] = {
|
|
||||||
/* 90 nm 1.00GHz Ultra Low Voltage Pentium M */
|
|
||||||
FREQ_INFO(1000, 940, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 900, 908, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 800, 876, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 600, 812, INTEL_BUS_CLK),
|
|
||||||
FREQ_INFO( 0, 0, 1),
|
|
||||||
};
|
|
||||||
|
|
||||||
/*
|
|
||||||
* VIA C7-M 500 MHz FSB, 400 MHz FSB, and ULV variants.
|
|
||||||
* Data from the "VIA C7-M Processor BIOS Writer's Guide (v2.17)" datasheet.
|
|
||||||
*/
|
|
||||||
static freq_info C7M_795[] = {
|
|
||||||
/* 2.00GHz Centaur C7-M 533 Mhz FSB */
|
|
||||||
FREQ_INFO_PWR(2000, 1148, 133, 20000),
|
|
||||||
FREQ_INFO_PWR(1867, 1132, 133, 18000),
|
|
||||||
FREQ_INFO_PWR(1600, 1100, 133, 15000),
|
|
||||||
FREQ_INFO_PWR(1467, 1052, 133, 13000),
|
|
||||||
FREQ_INFO_PWR(1200, 1004, 133, 10000),
|
|
||||||
FREQ_INFO_PWR( 800, 844, 133, 7000),
|
|
||||||
FREQ_INFO_PWR( 667, 844, 133, 6000),
|
|
||||||
FREQ_INFO_PWR( 533, 844, 133, 5000),
|
|
||||||
FREQ_INFO(0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info C7M_785[] = {
|
|
||||||
/* 1.80GHz Centaur C7-M 533 Mhz FSB */
|
|
||||||
FREQ_INFO_PWR(1867, 1148, 133, 18000),
|
|
||||||
FREQ_INFO_PWR(1600, 1100, 133, 15000),
|
|
||||||
FREQ_INFO_PWR(1467, 1052, 133, 13000),
|
|
||||||
FREQ_INFO_PWR(1200, 1004, 133, 10000),
|
|
||||||
FREQ_INFO_PWR( 800, 844, 133, 7000),
|
|
||||||
FREQ_INFO_PWR( 667, 844, 133, 6000),
|
|
||||||
FREQ_INFO_PWR( 533, 844, 133, 5000),
|
|
||||||
FREQ_INFO(0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info C7M_765[] = {
|
|
||||||
/* 1.60GHz Centaur C7-M 533 Mhz FSB */
|
|
||||||
FREQ_INFO_PWR(1600, 1084, 133, 15000),
|
|
||||||
FREQ_INFO_PWR(1467, 1052, 133, 13000),
|
|
||||||
FREQ_INFO_PWR(1200, 1004, 133, 10000),
|
|
||||||
FREQ_INFO_PWR( 800, 844, 133, 7000),
|
|
||||||
FREQ_INFO_PWR( 667, 844, 133, 6000),
|
|
||||||
FREQ_INFO_PWR( 533, 844, 133, 5000),
|
|
||||||
FREQ_INFO(0, 0, 1),
|
|
||||||
};
|
|
||||||
|
|
||||||
static freq_info C7M_794[] = {
|
|
||||||
/* 2.00GHz Centaur C7-M 400 Mhz FSB */
|
|
||||||
FREQ_INFO_PWR(2000, 1148, 100, 20000),
|
|
||||||
FREQ_INFO_PWR(1800, 1132, 100, 18000),
|
|
||||||
FREQ_INFO_PWR(1600, 1100, 100, 15000),
|
|
||||||
FREQ_INFO_PWR(1400, 1052, 100, 13000),
|
|
||||||
FREQ_INFO_PWR(1000, 1004, 100, 10000),
|
|
||||||
FREQ_INFO_PWR( 800, 844, 100, 7000),
|
|
||||||
FREQ_INFO_PWR( 600, 844, 100, 6000),
|
|
||||||
FREQ_INFO_PWR( 400, 844, 100, 5000),
|
|
||||||
FREQ_INFO(0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info C7M_784[] = {
|
|
||||||
/* 1.80GHz Centaur C7-M 400 Mhz FSB */
|
|
||||||
FREQ_INFO_PWR(1800, 1148, 100, 18000),
|
|
||||||
FREQ_INFO_PWR(1600, 1100, 100, 15000),
|
|
||||||
FREQ_INFO_PWR(1400, 1052, 100, 13000),
|
|
||||||
FREQ_INFO_PWR(1000, 1004, 100, 10000),
|
|
||||||
FREQ_INFO_PWR( 800, 844, 100, 7000),
|
|
||||||
FREQ_INFO_PWR( 600, 844, 100, 6000),
|
|
||||||
FREQ_INFO_PWR( 400, 844, 100, 5000),
|
|
||||||
FREQ_INFO(0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info C7M_764[] = {
|
|
||||||
/* 1.60GHz Centaur C7-M 400 Mhz FSB */
|
|
||||||
FREQ_INFO_PWR(1600, 1084, 100, 15000),
|
|
||||||
FREQ_INFO_PWR(1400, 1052, 100, 13000),
|
|
||||||
FREQ_INFO_PWR(1000, 1004, 100, 10000),
|
|
||||||
FREQ_INFO_PWR( 800, 844, 100, 7000),
|
|
||||||
FREQ_INFO_PWR( 600, 844, 100, 6000),
|
|
||||||
FREQ_INFO_PWR( 400, 844, 100, 5000),
|
|
||||||
FREQ_INFO(0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info C7M_754[] = {
|
|
||||||
/* 1.50GHz Centaur C7-M 400 Mhz FSB */
|
|
||||||
FREQ_INFO_PWR(1500, 1004, 100, 12000),
|
|
||||||
FREQ_INFO_PWR(1400, 988, 100, 11000),
|
|
||||||
FREQ_INFO_PWR(1000, 940, 100, 9000),
|
|
||||||
FREQ_INFO_PWR( 800, 844, 100, 7000),
|
|
||||||
FREQ_INFO_PWR( 600, 844, 100, 6000),
|
|
||||||
FREQ_INFO_PWR( 400, 844, 100, 5000),
|
|
||||||
FREQ_INFO(0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info C7M_771[] = {
|
|
||||||
/* 1.20GHz Centaur C7-M 400 Mhz FSB */
|
|
||||||
FREQ_INFO_PWR(1200, 860, 100, 7000),
|
|
||||||
FREQ_INFO_PWR(1000, 860, 100, 6000),
|
|
||||||
FREQ_INFO_PWR( 800, 844, 100, 5500),
|
|
||||||
FREQ_INFO_PWR( 600, 844, 100, 5000),
|
|
||||||
FREQ_INFO_PWR( 400, 844, 100, 4000),
|
|
||||||
FREQ_INFO(0, 0, 1),
|
|
||||||
};
|
|
||||||
|
|
||||||
static freq_info C7M_775_ULV[] = {
|
|
||||||
/* 1.50GHz Centaur C7-M ULV */
|
|
||||||
FREQ_INFO_PWR(1500, 956, 100, 7500),
|
|
||||||
FREQ_INFO_PWR(1400, 940, 100, 6000),
|
|
||||||
FREQ_INFO_PWR(1000, 860, 100, 5000),
|
|
||||||
FREQ_INFO_PWR( 800, 828, 100, 2800),
|
|
||||||
FREQ_INFO_PWR( 600, 796, 100, 2500),
|
|
||||||
FREQ_INFO_PWR( 400, 796, 100, 2000),
|
|
||||||
FREQ_INFO(0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info C7M_772_ULV[] = {
|
|
||||||
/* 1.20GHz Centaur C7-M ULV */
|
|
||||||
FREQ_INFO_PWR(1200, 844, 100, 5000),
|
|
||||||
FREQ_INFO_PWR(1000, 844, 100, 4000),
|
|
||||||
FREQ_INFO_PWR( 800, 828, 100, 2800),
|
|
||||||
FREQ_INFO_PWR( 600, 796, 100, 2500),
|
|
||||||
FREQ_INFO_PWR( 400, 796, 100, 2000),
|
|
||||||
FREQ_INFO(0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info C7M_779_ULV[] = {
|
|
||||||
/* 1.00GHz Centaur C7-M ULV */
|
|
||||||
FREQ_INFO_PWR(1000, 796, 100, 3500),
|
|
||||||
FREQ_INFO_PWR( 800, 796, 100, 2800),
|
|
||||||
FREQ_INFO_PWR( 600, 796, 100, 2500),
|
|
||||||
FREQ_INFO_PWR( 400, 796, 100, 2000),
|
|
||||||
FREQ_INFO(0, 0, 1),
|
|
||||||
};
|
|
||||||
static freq_info C7M_770_ULV[] = {
|
|
||||||
/* 1.00GHz Centaur C7-M ULV */
|
|
||||||
FREQ_INFO_PWR(1000, 844, 100, 5000),
|
|
||||||
FREQ_INFO_PWR( 800, 796, 100, 2800),
|
|
||||||
FREQ_INFO_PWR( 600, 796, 100, 2500),
|
|
||||||
FREQ_INFO_PWR( 400, 796, 100, 2000),
|
|
||||||
FREQ_INFO(0, 0, 1),
|
|
||||||
};
|
|
||||||
|
|
||||||
static ss_cpu_info ESTprocs[] = {
|
|
||||||
INTEL(PM17_130, 1700, 1484, 600, 956, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM16_130, 1600, 1484, 600, 956, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM15_130, 1500, 1484, 600, 956, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM14_130, 1400, 1484, 600, 956, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM13_130, 1300, 1388, 600, 956, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM13_LV_130, 1300, 1180, 600, 956, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM12_LV_130, 1200, 1180, 600, 956, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM11_LV_130, 1100, 1180, 600, 956, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM11_ULV_130, 1100, 1004, 600, 844, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM10_ULV_130, 1000, 1004, 600, 844, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_765A_90, 2100, 1340, 600, 988, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_765B_90, 2100, 1324, 600, 988, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_765C_90, 2100, 1308, 600, 988, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_765E_90, 2100, 1356, 600, 988, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_755A_90, 2000, 1340, 600, 988, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_755B_90, 2000, 1324, 600, 988, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_755C_90, 2000, 1308, 600, 988, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_755D_90, 2000, 1276, 600, 988, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_745A_90, 1800, 1340, 600, 988, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_745B_90, 1800, 1324, 600, 988, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_745C_90, 1800, 1308, 600, 988, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_745D_90, 1800, 1276, 600, 988, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_735A_90, 1700, 1340, 600, 988, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_735B_90, 1700, 1324, 600, 988, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_735C_90, 1700, 1308, 600, 988, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_735D_90, 1700, 1276, 600, 988, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_725A_90, 1600, 1340, 600, 988, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_725B_90, 1600, 1324, 600, 988, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_725C_90, 1600, 1308, 600, 988, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_725D_90, 1600, 1276, 600, 988, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_715A_90, 1500, 1340, 600, 988, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_715B_90, 1500, 1324, 600, 988, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_715C_90, 1500, 1308, 600, 988, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_715D_90, 1500, 1276, 600, 988, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_778_90, 1600, 1116, 600, 988, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_758_90, 1500, 1116, 600, 988, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_738_90, 1400, 1116, 600, 988, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_773G_90, 1300, 956, 600, 812, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_773H_90, 1300, 940, 600, 812, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_773I_90, 1300, 924, 600, 812, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_773J_90, 1300, 908, 600, 812, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_773K_90, 1300, 892, 600, 812, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_773L_90, 1300, 876, 600, 812, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_753G_90, 1200, 956, 600, 812, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_753H_90, 1200, 940, 600, 812, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_753I_90, 1200, 924, 600, 812, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_753J_90, 1200, 908, 600, 812, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_753K_90, 1200, 892, 600, 812, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_753L_90, 1200, 876, 600, 812, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_733JG_90, 1100, 956, 600, 812, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_733JH_90, 1100, 940, 600, 812, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_733JI_90, 1100, 924, 600, 812, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_733JJ_90, 1100, 908, 600, 812, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_733JK_90, 1100, 892, 600, 812, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_733JL_90, 1100, 876, 600, 812, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_733_90, 1100, 940, 600, 812, INTEL_BUS_CLK),
|
|
||||||
INTEL(PM_723_90, 1000, 940, 600, 812, INTEL_BUS_CLK),
|
|
||||||
|
|
||||||
CENTAUR(C7M_795, 2000, 1148, 533, 844, 133),
|
|
||||||
CENTAUR(C7M_794, 2000, 1148, 400, 844, 100),
|
|
||||||
CENTAUR(C7M_785, 1867, 1148, 533, 844, 133),
|
|
||||||
CENTAUR(C7M_784, 1800, 1148, 400, 844, 100),
|
|
||||||
CENTAUR(C7M_765, 1600, 1084, 533, 844, 133),
|
|
||||||
CENTAUR(C7M_764, 1600, 1084, 400, 844, 100),
|
|
||||||
CENTAUR(C7M_754, 1500, 1004, 400, 844, 100),
|
|
||||||
CENTAUR(C7M_775_ULV, 1500, 956, 400, 796, 100),
|
|
||||||
CENTAUR(C7M_771, 1200, 860, 400, 844, 100),
|
|
||||||
CENTAUR(C7M_772_ULV, 1200, 844, 400, 796, 100),
|
|
||||||
CENTAUR(C7M_779_ULV, 1000, 796, 400, 796, 100),
|
|
||||||
CENTAUR(C7M_770_ULV, 1000, 844, 400, 796, 100),
|
|
||||||
{ 0, 0, NULL },
|
|
||||||
};
|
|
||||||
|
|
||||||
#endif
|
|
||||||
|
|
||||||
Reference in New Issue
Block a user