diff --git a/headers/private/graphics/nvidia_gpgpu/DriverInterface.h b/headers/private/graphics/nvidia_gpgpu/DriverInterface.h deleted file mode 100644 index 33c21f3041..0000000000 --- a/headers/private/graphics/nvidia_gpgpu/DriverInterface.h +++ /dev/null @@ -1,369 +0,0 @@ -/* - Copyright 1999, Be Incorporated. All Rights Reserved. - This file may be used under the terms of the Be Sample Code License. - - Other authors: - Mark Watson; - Apsed; - Rudolf Cornelissen 10/2002-6/2008. -*/ - -#ifndef DRIVERINTERFACE_H -#define DRIVERINTERFACE_H - -#include -#include "video_overlay.h" -#include -#include -#include - -#define DRIVER_PREFIX "nvidia_gpgpu" -#define DEVICE_FORMAT "%04x_%04x_%02x%02x%02x" - -/* - Internal driver state (also for sharing info between driver and accelerant) -*/ -#if defined(__cplusplus) -extern "C" { -#endif - -typedef struct { - sem_id sem; - int32 ben; -} benaphore; - -#define INIT_BEN(x) x.sem = create_sem(0, "NV_GPGPU "#x" benaphore"); x.ben = 0; -#define AQUIRE_BEN(x) if((atomic_add(&(x.ben), 1)) >= 1) acquire_sem(x.sem); -#define RELEASE_BEN(x) if((atomic_add(&(x.ben), -1)) > 1) release_sem(x.sem); -#define DELETE_BEN(x) delete_sem(x.sem); - - -#define NV_PRIVATE_DATA_MAGIC 0x0009 /* a private driver rev, of sorts */ - -/* dualhead extensions to flags */ -#define DUALHEAD_OFF (0<<6) -#define DUALHEAD_CLONE (1<<6) -#define DUALHEAD_ON (2<<6) -#define DUALHEAD_SWITCH (3<<6) -#define DUALHEAD_BITS (3<<6) -#define DUALHEAD_CAPABLE (1<<8) -#define TV_BITS (3<<9) -#define TV_MON (0<<9 -#define TV_PAL (1<<9) -#define TV_NTSC (2<<9) -#define TV_CAPABLE (1<<11) -#define TV_VIDEO (1<<12) -#define TV_PRIMARY (1<<13) - -#define SKD_MOVE_CURSOR 0x00000001 -#define SKD_PROGRAM_CLUT 0x00000002 -#define SKD_SET_START_ADDR 0x00000004 -#define SKD_SET_CURSOR 0x00000008 -#define SKD_HANDLER_INSTALLED 0x80000000 - -enum { - NV_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, - NV_GET_PCI, - NV_SET_PCI, - NV_DEVICE_NAME, - NV_RUN_INTERRUPTS, - NV_ISA_OUT, - NV_ISA_IN -}; - -/* card_type in order of date of NV chip design */ -enum { - NV40 = 0, - NV41, - NV43, - NV44, - NV45, - G70, - G71, - G72, - G73, - G80, - G84, - G86 -}; - -/* card_arch in order of date of NV chip design */ -enum { - NV40A = 0, - NV50A -}; - -/* handles to pre-defined engine commands */ -#define NV_ROP5_SOLID 0x00000000 /* 2D */ -#define NV_IMAGE_BLACK_RECTANGLE 0x00000001 /* 2D/3D */ -#define NV_IMAGE_PATTERN 0x00000002 /* 2D */ -#define NV_SCALED_IMAGE_FROM_MEMORY 0x00000003 /* 2D */ -#define NV_TCL_PRIMITIVE_3D 0x00000004 /* 3D */ //2007 -#define NV4_SURFACE 0x00000010 /* 2D */ -#define NV10_CONTEXT_SURFACES_2D 0x00000010 /* 2D */ -#define NV_IMAGE_BLIT 0x00000011 /* 2D */ -#define NV12_IMAGE_BLIT 0x00000011 /* 2D */ -/* fixme: - * never use NV3_GDI_RECTANGLE_TEXT for DMA acceleration: - * There's a hardware fault in the input->output colorspace conversion here. - * Besides, in NV40 and up this command nolonger exists. Both 'facts' are confirmed - * by testing. - */ -//#define NV3_GDI_RECTANGLE_TEXT 0x00000012 /* 2D */ -#define NV4_GDI_RECTANGLE_TEXT 0x00000012 /* 2D */ -#define NV1_RENDER_SOLID_LIN 0x00000016 /* 2D: unused */ - -//----------------------------------------------------------------------------------- -/* safety byte-offset from end of cardRAM for preventing acceleration engine crashes - * caused by the existance of DMA engine command buffers in cardRAM and/or fifo - * channel engine command re-assigning on-the-fly */ - -/* NV40 and higher notes: - * - we need at least 416kB distance from the DMA command buffer: - * If you get too close to the DMA command buffer on NV40 and NV43 at least (both - * confirmed), the source DMA instance will mess-up for at least engine command - * NV_IMAGE_BLIT and NV12_IMAGE_BLIT; - * - we need at least ???kB distance from the end of RAM for fifo-reassigning 'bug' - * (fixme: unknown yet because fifo assignment switching isn't used here atm); - * - keep extra failsafe room to prevent malfunctioning apps from crashing engine. */ -#define NV40_PLUS_OFFSET 512 * 1024 - -/* fifo re-assigning bug definition: - * if the fifo assignment is changed while at the same time card memory in the - * dangerous region is being accessed by some application, the engine will crash. - * This bug applies for both PIO and DMA mode acceleration! */ - -/* source-DMA instance bug definition: - * if card memory in the dangerous region is being accessed by some application while - * a DMA command buffer exists in the same memory (though in a different place), - * the engine will crash. */ -//----------------------------------------------------------------------------------- - -/* internal used info on overlay buffers */ -typedef struct { - uint16 slopspace; - uint32 size; -} int_buf_info; - -typedef struct { // apsed, see comments in nv.settings - // for driver - char accelerant[B_FILE_NAME_LENGTH]; - char primary[B_FILE_NAME_LENGTH]; - bool dumprom; - // for accelerant - uint32 logmask; - uint32 memory; - bool usebios; - bool hardcursor; - bool switchhead; - bool pgm_panel; - bool force_sync; - bool force_ws; - uint32 gpu_clk; - uint32 ram_clk; -} nv_settings; - -/* shared info */ -typedef struct { - /* a few ID things */ - uint16 vendor_id; /* PCI vendor ID, from pci_info */ - uint16 device_id; /* PCI device ID, from pci_info */ - uint8 revision; /* PCI device revsion, from pci_info */ - uint8 bus; /* PCI bus number, from pci_info */ - uint8 device; /* PCI device number on bus, from pci_info */ - uint8 function; /* PCI function number in device, from pci_info */ - - /* used to return status for INIT_ACCELERANT and CLONE_ACCELERANT */ - bool accelerant_in_use; - - /* bug workaround for 4.5.0 */ - uint32 use_clone_bugfix; /*for 4.5.0, cloning of physical memory does not work*/ - uint32 * clone_bugfix_regs; - - /*memory mappings*/ - area_id regs_area; /* Kernel's area_id for the memory mapped registers. - It will be cloned into the accelerant's address - space. */ - - area_id fb_area; /* Frame buffer's area_id. The addresses are shared with all teams. */ - area_id unaligned_dma_area; /* Area assigned for DMA. It will be (partially) mapped to an - aligned area using MTRR-WC. */ - area_id dma_area; /* Aligned area assigned for DMA. The addresses are shared with all teams. */ - - void *framebuffer; /* As viewed from virtual memory */ - void *framebuffer_pci; /* As viewed from the PCI bus (for DMA) */ - void *dma_buffer; /* As viewed from virtual memory */ - void *dma_buffer_pci; /* As viewed from the PCI bus (for DMA) */ - - /*screenmode list*/ - area_id mode_area; /* Contains the list of display modes the driver supports */ - uint32 mode_count; /* Number of display modes in the list */ - - /*flags - used by driver*/ - uint32 flags; - - /*vblank semaphore*/ - sem_id vblank; /* The vertical blank semaphore. Ownership will be - transfered to the team opening the device first */ - /*cursor information*/ - struct { - uint16 hot_x; /* Cursor hot spot. The top left corner of the cursor */ - uint16 hot_y; /* is 0,0 */ - uint16 x; /* The location of the cursor hot spot on the */ - uint16 y; /* desktop */ - uint16 width; /* Width and height of the cursor shape (always 16!) */ - uint16 height; - bool is_visible; /* Is the cursor currently displayed? */ - bool dh_right; /* Is cursor on right side of stretched screen? */ - } cursor; - - /*colour lookup table*/ - uint8 color_data[3 * 256]; /* Colour lookup table - as used by DAC */ - - /*more display mode stuff*/ - display_mode dm; /* current display mode configuration: head1 */ - uint32 dpms_flags; /* current DPMS mode */ - bool acc_mode; /* signals (non)accelerated mode */ - bool crtc_switch_mode; /* signals dualhead switch mode if panels are used */ - - /*frame buffer config - for BDirectScreen*/ - frame_buffer_config fbc; /* bytes_per_row and start of frame buffer: head1 */ - accelerant_device_info adi; /* as returned by hook GET_ACCELERANT_DEVICE_INFO */ - - /*acceleration engine*/ - struct { - uint32 count; /* last dwgsync slot used */ - uint32 last_idle; /* last dwgsync slot we *know* the engine was idle after */ - benaphore lock; /* for serializing access to the acc engine */ - struct { - uint32 handle[0x08]; /* FIFO channel's cmd handle for the owning cmd */ - uint32 ch_ptr[0x20]; /* cmd handle's ptr to it's assigned FIFO ch (if any) */ - } fifo; - struct { - uint32 put; /* last 32-bit-word adress given to engine to exec. to */ - uint32 current; /* first free 32-bit-word adress in buffer */ - uint32 free; /* nr. of useable free 32-bit words remaining in buffer */ - uint32 max; /* command buffer's useable size in 32-bit words */ - } dma; - struct { - uint32 clones; /* clone 'number' (mask, slot) (one bit per clone) */ - uint32 reload; /* reload state and surfaces (one bit per clone) */ - uint32 newmode; /* re-allocate all buffers (one bit per clone) */ - //fixme: memory stuff needs to be expanded (shared texture allocation?) - uint32 mem_low; /* ptr to first free mem adress: cardmem local offset */ - uint32 mem_high; /* ptr to last free mem adress: cardmem local offset */ - bool mode_changing; /* a mode-change is in progress (set/clear by 2D drv) */ - } threeD; - } engine; - - struct - { - /* specialised registers for card initialisation read from NV BIOS (pins) */ - - /* general card information */ - uint32 card_type; /* see card_type enum above */ - uint32 card_arch; /* see card_arch enum above */ - bool laptop; /* mobile chipset or not ('internal' flatpanel!) */ - bool slaved_tmds1; /* external TMDS encoder active on CRTC1 */ - bool slaved_tmds2; /* external TMDS encoder active on CRTC2 */ - bool master_tmds1; /* on die TMDS encoder active on CRTC1 */ - bool master_tmds2; /* on die TMDS encoder active on CRTC2 */ - bool tmds1_active; /* found panel on CRTC1 that is active */ - bool tmds2_active; /* found panel on CRTC2 that is active */ - display_timing p1_timing; /* 'modeline' fetched for panel 1 */ - display_timing p2_timing; /* 'modeline' fetched for panel 2 */ - float panel1_aspect; /* panel's aspect ratio */ - float panel2_aspect; /* panel's aspect ratio */ - bool crtc2_prim; /* using CRTC2 as primary CRTC */ - bool i2c_bus0; /* we have a wired I2C bus 0 on board */ - bool i2c_bus1; /* we have a wired I2C bus 1 on board */ - bool i2c_bus2; /* we have a wired I2C bus 2 on board */ - bool i2c_bus3; /* we have a wired I2C bus 3 on board */ - uint8 monitors; /* output devices connection matrix */ - bool int_assigned; /* card has a useable INT assigned to it */ - status_t pins_status; /* B_OK if read correctly, B_ERROR if faked */ - - /* PINS */ - float f_ref; /* PLL reference-oscillator frequency (Mhz) */ - bool ext_pll; /* the extended PLL contains more dividers */ - uint32 max_system_vco; /* graphics engine PLL VCO limits (Mhz) */ - uint32 min_system_vco; - uint32 max_pixel_vco; /* dac1 PLL VCO limits (Mhz) */ - uint32 min_pixel_vco; - uint32 max_video_vco; /* dac2 PLL VCO limits (Mhz) */ - uint32 min_video_vco; - uint32 std_engine_clock; /* graphics engine clock speed needed (Mhz) */ - uint32 std_memory_clock; /* card memory clock speed needed (Mhz) */ - uint32 max_dac1_clock; /* dac1 limits (Mhz) */ - uint32 max_dac1_clock_8; /* dac1 limits correlated to RAMspeed limits (Mhz) */ - uint32 max_dac1_clock_16; - uint32 max_dac1_clock_24; - uint32 max_dac1_clock_32; - uint32 max_dac1_clock_32dh; - uint32 max_dac2_clock; /* dac2 limits (Mhz) */ - uint32 max_dac2_clock_8; /* dac2, maven limits correlated to RAMspeed limits (Mhz) */ - uint32 max_dac2_clock_16; - uint32 max_dac2_clock_24; - uint32 max_dac2_clock_32; - uint32 max_dac2_clock_32dh; - bool secondary_head; /* presence of functions */ - bool primary_dvi; - bool secondary_dvi; - uint32 memory_size; /* memory (in bytes) */ - } ps; - - /* mirror of the ROM (copied in driver, because may not be mapped permanently) */ - uint8 rom_mirror[65536]; - - /* some configuration settings from ~/config/settings/kernel/drivers/nv.settings if exists */ - nv_settings settings; - -} shared_info; - -/* Read or write a value in PCI configuration space */ -typedef struct { - uint32 magic; /* magic number to make sure the caller groks us */ - uint32 offset; /* Offset to read/write */ - uint32 size; /* Number of bytes to transfer */ - uint32 value; /* The value read or written */ -} nv_get_set_pci; - -/* Enable or Disable CRTC (1,2) interrupts */ -typedef struct { - uint32 magic; /* magic number to make sure the caller groks us */ - bool crtc; /* adressed CRTC */ - bool do_it; /* state to set */ -} nv_set_vblank_int; - -/* Retrieve the area_id of the kernel/accelerant shared info */ -typedef struct { - uint32 magic; /* magic number to make sure the caller groks us */ - area_id shared_info_area; /* area_id containing the shared information */ -} nv_get_private_data; - -/* Retrieve the device name. Usefull for when we have a file handle, but want -to know the device name (like when we are cloning the accelerant) */ -typedef struct { - uint32 magic; /* magic number to make sure the caller groks us */ - char *name; /* The name of the device, less the /dev root */ -} nv_device_name; - -/* Read or write a value in ISA I/O space */ -typedef struct { - uint32 magic; /* magic number to make sure the caller groks us */ - uint16 adress; /* Offset to read/write */ - uint8 size; /* Number of bytes to transfer */ - uint16 data; /* The value read or written */ -} nv_in_out_isa; - -enum { - - _WAIT_FOR_VBLANK = (1 << 0) -}; - -#if defined(__cplusplus) -} -#endif - - -#endif diff --git a/headers/private/graphics/nvidia_gpgpu/nv_acc.h b/headers/private/graphics/nvidia_gpgpu/nv_acc.h deleted file mode 100644 index 7724b9f171..0000000000 --- a/headers/private/graphics/nvidia_gpgpu/nv_acc.h +++ /dev/null @@ -1,51 +0,0 @@ -/* - definitions for used nVidia acceleration engine commands. - - Written by Rudolf Cornelissen 12/2004-6/2008 -*/ - -#ifndef NV_ACC_H -#define NV_ACC_H - -/************ DMA command defines ***********/ - -/* FIFO channels */ -#define NV_GENERAL_FIFO_CH0 0x0000 -#define NV_GENERAL_FIFO_CH1 0x2000 -#define NV_GENERAL_FIFO_CH2 0x4000 -#define NV_GENERAL_FIFO_CH3 0x6000 -#define NV_GENERAL_FIFO_CH4 0x8000 -#define NV_GENERAL_FIFO_CH5 0xa000 -#define NV_GENERAL_FIFO_CH6 0xc000 -#define NV_GENERAL_FIFO_CH7 0xe000 - -/* sub-command offsets within FIFO channels */ -#define NV_GENERAL_DMAPUT 0x0040 -#define NV_GENERAL_DMAGET 0x0044 -#define NV_ROP5_SOLID_SETROP5 0x0300 -#define NV_IMAGE_BLACK_RECTANGLE_TOPLEFT 0x0300 -#define NV_IMAGE_PATTERN_SETCOLORFORMAT 0x0300 -#define NV_IMAGE_PATTERN_SETSHAPE 0x0308 -#define NV_IMAGE_PATTERN_SETCOLOR0 0x0310 -#define NV_IMAGE_BLIT_SOURCEORG 0x0300 -//fixme note: non-DMA acc is still using NV3_GDI_RECTANGLE_TEXT... -//which is just as fast as NV4_GDI_RECTANGLE_TEXT, but has a hardware fault for DMA! -#define NV4_GDI_RECTANGLE_TEXT_SETCOLORFORMAT 0x0300 -#define NV4_GDI_RECTANGLE_TEXT_COLOR1A 0x03fc -#define NV4_GDI_RECTANGLE_TEXT_UCR0_LEFTTOP 0x0400 -#define NV4_SURFACE_FORMAT 0x0300 -#define NV_SCALED_IMAGE_FROM_MEMORY_SETCOLORFORMAT 0x0300 -#define NV_SCALED_IMAGE_FROM_MEMORY_SOURCEORG 0x0308 -#define NV_SCALED_IMAGE_FROM_MEMORY_SOURCESIZE 0x0400 - - -/************************ - * 3D specific commands * - ************************/ - -#define NV4_DX5_TEXTURE_TRIANGLE_COLORKEY 0x0300 -#define NV4_DX5_TEXTURE_TRIANGLE_TLVERTEX(i) 0x0400 + (i << 5) -#define NV4_DX5_TEXTURE_TRIANGLE_TLVDRAWPRIM(i) 0x0600 + (i << 2) -#define NV4_CONTEXT_SURFACES_ARGB_ZS_PITCH 0x0308 - -#endif diff --git a/headers/private/graphics/nvidia_gpgpu/nv_macros.h b/headers/private/graphics/nvidia_gpgpu/nv_macros.h deleted file mode 100644 index 8e93afdecf..0000000000 --- a/headers/private/graphics/nvidia_gpgpu/nv_macros.h +++ /dev/null @@ -1,912 +0,0 @@ -/* NV registers definitions and macros for access to them */ - -/* PCI_config_space */ -#define NVCFG_DEVID 0x00 -#define NVCFG_DEVCTRL 0x04 -#define NVCFG_CLASS 0x08 -#define NVCFG_HEADER 0x0c -#define NVCFG_BASE1REGS 0x10 -#define NVCFG_BASE2FB 0x14 -#define NVCFG_BASE3 0x18 -#define NVCFG_BASE4 0x1c //unknown if used -#define NVCFG_BASE5 0x20 //unknown if used -#define NVCFG_BASE6 0x24 //unknown if used -#define NVCFG_BASE7 0x28 //unknown if used -#define NVCFG_SUBSYSID1 0x2c -#define NVCFG_ROMBASE 0x30 -#define NVCFG_CAPPTR 0x34 -#define NVCFG_CFG_1 0x38 //unknown if used -#define NVCFG_INTERRUPT 0x3c -#define NVCFG_SUBSYSID2 0x40 -#define NVCFG_AGPREF 0x44 -#define NVCFG_AGPSTAT 0x48 -#define NVCFG_AGPCMD 0x4c -#define NVCFG_ROMSHADOW 0x50 -#define NVCFG_VGA 0x54 -#define NVCFG_SCHRATCH 0x58 -#define NVCFG_CFG_10 0x5c -#define NVCFG_CFG_11 0x60 -#define NVCFG_CFG_12 0x64 -#define NVCFG_CFG_13 0x68 //unknown if used -#define NVCFG_CFG_14 0x6c //unknown if used -#define NVCFG_CFG_15 0x70 //unknown if used -#define NVCFG_CFG_16 0x74 //unknown if used -#define NVCFG_PCIEREF 0x78 -#define NVCFG_PCIEDCAP 0x7c -#define NVCFG_PCIEDCTST 0x80 -#define NVCFG_PCIELCAP 0x84 -#define NVCFG_PCIELCTST 0x88 -#define NVCFG_CFG_22 0x8c //unknown if used -#define NVCFG_CFG_23 0x90 //unknown if used -#define NVCFG_CFG_24 0x94 //unknown if used -#define NVCFG_CFG_25 0x98 //unknown if used -#define NVCFG_CFG_26 0x9c //unknown if used -#define NVCFG_CFG_27 0xa0 //unknown if used -#define NVCFG_CFG_28 0xa4 //unknown if used -#define NVCFG_CFG_29 0xa8 //unknown if used -#define NVCFG_CFG_30 0xac //unknown if used -#define NVCFG_CFG_31 0xb0 //unknown if used -#define NVCFG_CFG_32 0xb4 //unknown if used -#define NVCFG_CFG_33 0xb8 //unknown if used -#define NVCFG_CFG_34 0xbc //unknown if used -#define NVCFG_CFG_35 0xc0 //unknown if used -#define NVCFG_CFG_36 0xc4 //unknown if used -#define NVCFG_CFG_37 0xc8 //unknown if used -#define NVCFG_CFG_38 0xcc //unknown if used -#define NVCFG_CFG_39 0xd0 //unknown if used -#define NVCFG_CFG_40 0xd4 //unknown if used -#define NVCFG_CFG_41 0xd8 //unknown if used -#define NVCFG_CFG_42 0xdc //unknown if used -#define NVCFG_CFG_43 0xe0 //unknown if used -#define NVCFG_CFG_44 0xe4 //unknown if used -#define NVCFG_CFG_45 0xe8 //unknown if used -#define NVCFG_CFG_46 0xec //unknown if used -#define NVCFG_CFG_47 0xf0 //unknown if used -#define NVCFG_CFG_48 0xf4 //unknown if used -#define NVCFG_CFG_49 0xf8 //unknown if used -#define NVCFG_CFG_50 0xfc //unknown if used - -/* used NV INT registers for vblank */ -#define NV32_MAIN_INTE 0x00000140 -#define NV32_CRTC_INTS 0x00600100 -#define NV32_CRTC_INTE 0x00600140 -#define NV32_CRTC2_INTS 0x00602100 -#define NV32_CRTC2_INTE 0x00602140 - -/* NV ACCeleration registers */ -/* engine initialisation registers */ -#define NVACC_ABS_UCLP_XMIN 0x0040053c -#define NVACC_ABS_UCLP_YMIN 0x00400540 -#define NVACC_ABS_UCLP_XMAX 0x00400544 -#define NVACC_ABS_UCLP_YMAX 0x00400548 -#define NVACC_BETA_AND_VAL 0x00400608 -#define NVACC_FORMATS 0x00400618 -#define NVACC_OFFSET0 0x00400640 -#define NVACC_OFFSET1 0x00400644 -#define NVACC_OFFSET2 0x00400648 -#define NVACC_OFFSET3 0x0040064c -#define NVACC_OFFSET4 0x00400650 -#define NVACC_OFFSET5 0x00400654 -#define NVACC_BBASE0 0x00400658 -#define NVACC_BBASE1 0x0040065c -#define NVACC_BBASE2 0x00400660 -#define NVACC_BBASE3 0x00400664 -#define NVACC_NV10_BBASE4 0x00400668 -#define NVACC_NV10_BBASE5 0x0040066c -#define NVACC_PITCH0 0x00400670 -#define NVACC_PITCH1 0x00400674 -#define NVACC_PITCH2 0x00400678 -#define NVACC_PITCH3 0x0040067c -#define NVACC_PITCH4 0x00400680 -#define NVACC_BLIMIT0 0x00400684 -#define NVACC_BLIMIT1 0x00400688 -#define NVACC_BLIMIT2 0x0040068c -#define NVACC_BLIMIT3 0x00400690 -#define NVACC_NV10_BLIMIT4 0x00400694 -#define NVACC_NV10_BLIMIT5 0x00400698 -#define NVACC_BPIXEL 0x00400724 -#define NVACC_NV20_OFFSET0 0x00400820 -#define NVACC_NV20_OFFSET1 0x00400824 -#define NVACC_NV20_OFFSET2 0x00400828 -#define NVACC_NV20_OFFSET3 0x0040082c -#define NVACC_STRD_FMT 0x00400830 -#define NVACC_NV20_PITCH0 0x00400850 -#define NVACC_NV20_PITCH1 0x00400854 -#define NVACC_NV20_PITCH2 0x00400858 -#define NVACC_NV20_PITCH3 0x0040085c -#define NVACC_NV20_BLIMIT6 0x00400864 -#define NVACC_NV20_BLIMIT7 0x00400868 -#define NVACC_NV20_BLIMIT8 0x0040086c -#define NVACC_NV20_BLIMIT9 0x00400870 -#define NVACC_NV25_WHAT1 0x00400890 - -/* specials */ -#define NVACC_DEBUG0 0x00400080 -#define NVACC_DEBUG1 0x00400084 -#define NVACC_DEBUG2 0x00400088 -#define NVACC_DEBUG3 0x0040008c -#define NVACC_NV10_DEBUG4 0x00400090 -#define NVACC_NV10_DEBUG5 0x00400094 -#define NVACC_NV20_WHAT5 0x00400098 -#define NVACC_NV20_WHAT1 0x0040009c -#define NVACC_ACC_INTS 0x00400100 -#define NVACC_ACC_INTE 0x00400140 -#define NVACC_NV10_CTX_CTRL 0x00400144 -#define NVACC_NV4X_DMA_SRC 0x00400220 -#define NVACC_NV4X_WHAT1 0x0040032c -#define NVACC_NV4X_WHAT2 0x00405000 -#define NVACC_NV25_WHAT0 0x00400610 -#define NVACC_STATUS 0x00400700 -#define NVACC_NV04_SURF_TYP 0x0040070c -#define NVACC_NV10_SURF_TYP 0x00400710 -#define NVACC_NV04_ACC_STAT 0x00400710 -#define NVACC_NV10_ACC_STAT 0x00400714 -#define NVACC_FIFO_EN 0x00400720 -#define NVACC_RDI_INDEX 0x00400750 -#define NVACC_RDI_DATA 0x00400754 -#define NVACC_PAT_SHP 0x00400810 -#define NVACC_NV40P_WHAT0 0x00400820 -#define NVACC_NV40P_WHAT1 0x00400824 -#define NVACC_NV40P_WHAT2 0x00400828 -#define NVACC_NV40P_WHAT3 0x0040082c -#define NVACC_NV40P_OFFSET0 0x00400840 -#define NVACC_NV40P_OFFSET1 0x00400844 -#define NVACC_NV44_WHAT2 0x00400860 -#define NVACC_NV44_WHAT3 0x00400864 -//fixme? (guessed) -#define NVACC_NV40P_PITCH0 0x00400870 -#define NVACC_NV40P_PITCH1 0x00400874 -#define NVACC_NV20_WHAT2 0x00400880 -//end fixme. -#define NVACC_NV40P_BLIMIT6 0x004008a0 -#define NVACC_NV40P_BLIMIT7 0x004008a4 -#define NVACC_NV20_WHAT0 0x00400900 -#define NVACC_NV41_WHAT0 0x00400d00 -#define NVACC_NV20_2_WHAT0 0x00406900 -#define NVACC_NV40_WHAT0 0x004009b0 -#define NVACC_NV40_WHAT1 0x004009b4 -#define NVACC_NV40_WHAT2 0x004009b8 -#define NVACC_NV40_WHAT3 0x004009bc -#define NVACC_NV20_WHAT3 0x00400b80 -#define NVACC_NV20_WHAT4 0x00400b84 -#define NVACC_NV25_WHAT2 0x00400b88 -#define NVACC_WINCLIP_H_0 0x00400f00 -#define NVACC_WINCLIP_H_1 0x00400f04 -#define NVACC_WINCLIP_H_2 0x00400f08 -#define NVACC_WINCLIP_H_3 0x00400f0c -#define NVACC_WINCLIP_H_4 0x00400f10 -#define NVACC_WINCLIP_H_5 0x00400f14 -#define NVACC_WINCLIP_H_6 0x00400f18 -#define NVACC_WINCLIP_H_7 0x00400f1c -#define NVACC_WINCLIP_V_0 0x00400f20 -#define NVACC_WINCLIP_V_1 0x00400f24 -#define NVACC_WINCLIP_V_2 0x00400f28 -#define NVACC_WINCLIP_V_3 0x00400f2c -#define NVACC_WINCLIP_V_4 0x00400f30 -#define NVACC_WINCLIP_V_5 0x00400f34 -#define NVACC_WINCLIP_V_6 0x00400f38 -#define NVACC_WINCLIP_V_7 0x00400f3c -#define NVACC_NV10_XFMOD0 0x00400f40 -#define NVACC_NV10_XFMOD1 0x00400f44 -#define NVACC_GLOB_STAT_0 0x00400f48 -#define NVACC_GLOB_STAT_1 0x00400f4c -#define NVACC_NV10_PIPEADR 0x00400f50 -#define NVACC_NV10_PIPEDAT 0x00400f54 -/* PGRAPH unknown registers */ -#define NVACC_PGWHAT_00 0x00400e00 -#define NVACC_PGWHAT_01 0x00400e04 -#define NVACC_PGWHAT_02 0x00400e08 -#define NVACC_PGWHAT_03 0x00400e0c -#define NVACC_PGWHAT_04 0x00400e10 -#define NVACC_PGWHAT_05 0x00400e14 -#define NVACC_PGWHAT_06 0x00400e18 -#define NVACC_PGWHAT_07 0x00400e1c -#define NVACC_PGWHAT_08 0x00400e20 -#define NVACC_PGWHAT_09 0x00400e24 -#define NVACC_PGWHAT_0A 0x00400e28 -#define NVACC_PGWHAT_0B 0x00400e2c -#define NVACC_PGWHAT_0C 0x00400e30 -#define NVACC_PGWHAT_0D 0x00400e34 -#define NVACC_PGWHAT_0E 0x00400e38 -#define NVACC_PGWHAT_0F 0x00400e3c -#define NVACC_PGWHAT_10 0x00400e40 -#define NVACC_PGWHAT_11 0x00400e44 -#define NVACC_PGWHAT_12 0x00400e48 -#define NVACC_PGWHAT_13 0x00400e4c -#define NVACC_PGWHAT_14 0x00400e50 -#define NVACC_PGWHAT_15 0x00400e54 -#define NVACC_PGWHAT_16 0x00400e58 -#define NVACC_PGWHAT_17 0x00400e5c -#define NVACC_PGWHAT_18 0x00400e60 -#define NVACC_PGWHAT_19 0x00400e64 -#define NVACC_PGWHAT_1A 0x00400e68 -#define NVACC_PGWHAT_1B 0x00400e6c -#define NVACC_PGWHAT_1C 0x00400e70 -#define NVACC_PGWHAT_1D 0x00400e74 -#define NVACC_PGWHAT_1E 0x00400e78 -#define NVACC_PGWHAT_1F 0x00400e7c -#define NVACC_PGWHAT_20 0x00400e80 -#define NVACC_PGWHAT_21 0x00400e84 -#define NVACC_PGWHAT_22 0x00400e88 -#define NVACC_PGWHAT_23 0x00400e8c -#define NVACC_PGWHAT_24 0x00400e90 -#define NVACC_PGWHAT_25 0x00400e94 -#define NVACC_PGWHAT_26 0x00400e98 -#define NVACC_PGWHAT_27 0x00400e9c -#define NVACC_PGWHAT_28 0x00400ea0 -#define NVACC_PGWHAT_29 0x00400ea4 -#define NVACC_PGWHAT_2A 0x00400ea8 -/* PGRAPH cache registers */ -#define NVACC_CACHE1_1 0x00400160 -#define NVACC_CACHE1_2 0x00400180 -#define NVACC_CACHE1_3 0x004001a0 -#define NVACC_CACHE1_4 0x004001c0 -#define NVACC_CACHE1_5 0x004001e0 -#define NVACC_CACHE2_1 0x00400164 -#define NVACC_CACHE2_2 0x00400184 -#define NVACC_CACHE2_3 0x004001a4 -#define NVACC_CACHE2_4 0x004001c4 -#define NVACC_CACHE2_5 0x004001e4 -#define NVACC_CACHE3_1 0x00400168 -#define NVACC_CACHE3_2 0x00400188 -#define NVACC_CACHE3_3 0x004001a8 -#define NVACC_CACHE3_4 0x004001c8 -#define NVACC_CACHE3_5 0x004001e8 -#define NVACC_CACHE4_1 0x0040016c -#define NVACC_CACHE4_2 0x0040018c -#define NVACC_CACHE4_3 0x004001ac -#define NVACC_CACHE4_4 0x004001cc -#define NVACC_CACHE4_5 0x004001ec -#define NVACC_NV10_CACHE5_1 0x00400170 -#define NVACC_NV04_CTX_CTRL 0x00400170 -#define NVACC_CACHE5_2 0x00400190 -#define NVACC_CACHE5_3 0x004001b0 -#define NVACC_CACHE5_4 0x004001d0 -#define NVACC_CACHE5_5 0x004001f0 -#define NVACC_NV10_CACHE6_1 0x00400174 -#define NVACC_CACHE6_2 0x00400194 -#define NVACC_CACHE6_3 0x004001b4 -#define NVACC_CACHE6_4 0x004001d4 -#define NVACC_CACHE6_5 0x004001f4 -#define NVACC_NV10_CACHE7_1 0x00400178 -#define NVACC_CACHE7_2 0x00400198 -#define NVACC_CACHE7_3 0x004001b8 -#define NVACC_CACHE7_4 0x004001d8 -#define NVACC_CACHE7_5 0x004001f8 -#define NVACC_NV10_CACHE8_1 0x0040017c -#define NVACC_CACHE8_2 0x0040019c -#define NVACC_CACHE8_3 0x004001bc -#define NVACC_CACHE8_4 0x004001dc -#define NVACC_CACHE8_5 0x004001fc -#define NVACC_NV10_CTX_SW1 0x0040014c -#define NVACC_NV10_CTX_SW2 0x00400150 -#define NVACC_NV10_CTX_SW3 0x00400154 -#define NVACC_NV10_CTX_SW4 0x00400158 -#define NVACC_NV10_CTX_SW5 0x0040015c -/* engine tile registers src */ -#define NVACC_NV10_FBTIL0AD 0x00100240 -#define NVACC_NV10_FBTIL0ED 0x00100244 -#define NVACC_NV10_FBTIL0PT 0x00100248 -#define NVACC_NV10_FBTIL0ST 0x0010024c -#define NVACC_NV10_FBTIL1AD 0x00100250 -#define NVACC_NV10_FBTIL1ED 0x00100254 -#define NVACC_NV10_FBTIL1PT 0x00100258 -#define NVACC_NV10_FBTIL1ST 0x0010025c -#define NVACC_NV10_FBTIL2AD 0x00100260 -#define NVACC_NV10_FBTIL2ED 0x00100264 -#define NVACC_NV10_FBTIL2PT 0x00100268 -#define NVACC_NV10_FBTIL2ST 0x0010026c -#define NVACC_NV10_FBTIL3AD 0x00100270 -#define NVACC_NV10_FBTIL3ED 0x00100274 -#define NVACC_NV10_FBTIL3PT 0x00100278 -#define NVACC_NV10_FBTIL3ST 0x0010027c -#define NVACC_NV10_FBTIL4AD 0x00100280 -#define NVACC_NV10_FBTIL4ED 0x00100284 -#define NVACC_NV10_FBTIL4PT 0x00100288 -#define NVACC_NV10_FBTIL4ST 0x0010028c -#define NVACC_NV10_FBTIL5AD 0x00100290 -#define NVACC_NV10_FBTIL5ED 0x00100294 -#define NVACC_NV10_FBTIL5PT 0x00100298 -#define NVACC_NV10_FBTIL5ST 0x0010029c -#define NVACC_NV10_FBTIL6AD 0x001002a0 -#define NVACC_NV10_FBTIL6ED 0x001002a4 -#define NVACC_NV10_FBTIL6PT 0x001002a8 -#define NVACC_NV10_FBTIL6ST 0x001002ac -#define NVACC_NV10_FBTIL7AD 0x001002b0 -#define NVACC_NV10_FBTIL7ED 0x001002b4 -#define NVACC_NV10_FBTIL7PT 0x001002b8 -#define NVACC_NV10_FBTIL7ST 0x001002bc -#define NVACC_NV41_FBTIL0AD 0x00100600 -#define NVACC_NV41_FBTIL0ED 0x00100604 -#define NVACC_NV41_FBTIL0PT 0x00100608 -#define NVACC_NV41_FBTIL0ST 0x0010060c -#define NVACC_NV41_FBTIL1AD 0x00100610 -#define NVACC_NV41_FBTIL1ED 0x00100614 -#define NVACC_NV41_FBTIL1PT 0x00100618 -#define NVACC_NV41_FBTIL1ST 0x0010061c -#define NVACC_NV41_FBTIL2AD 0x00100620 -#define NVACC_NV41_FBTIL2ED 0x00100624 -#define NVACC_NV41_FBTIL2PT 0x00100628 -#define NVACC_NV41_FBTIL2ST 0x0010062c -#define NVACC_NV41_FBTIL3AD 0x00100630 -#define NVACC_NV41_FBTIL3ED 0x00100634 -#define NVACC_NV41_FBTIL3PT 0x00100638 -#define NVACC_NV41_FBTIL3ST 0x0010063c -#define NVACC_NV41_FBTIL4AD 0x00100640 -#define NVACC_NV41_FBTIL4ED 0x00100644 -#define NVACC_NV41_FBTIL4PT 0x00100648 -#define NVACC_NV41_FBTIL4ST 0x0010064c -#define NVACC_NV41_FBTIL5AD 0x00100650 -#define NVACC_NV41_FBTIL5ED 0x00100654 -#define NVACC_NV41_FBTIL5PT 0x00100658 -#define NVACC_NV41_FBTIL5ST 0x0010065c -#define NVACC_NV41_FBTIL6AD 0x00100660 -#define NVACC_NV41_FBTIL6ED 0x00100664 -#define NVACC_NV41_FBTIL6PT 0x00100668 -#define NVACC_NV41_FBTIL6ST 0x0010066c -#define NVACC_NV41_FBTIL7AD 0x00100670 -#define NVACC_NV41_FBTIL7ED 0x00100674 -#define NVACC_NV41_FBTIL7PT 0x00100678 -#define NVACC_NV41_FBTIL7ST 0x0010067c -#define NVACC_NV41_FBTIL8AD 0x00100680 -#define NVACC_NV41_FBTIL8ED 0x00100684 -#define NVACC_NV41_FBTIL8PT 0x00100688 -#define NVACC_NV41_FBTIL8ST 0x0010068c -#define NVACC_NV41_FBTIL9AD 0x00100690 -#define NVACC_NV41_FBTIL9ED 0x00100694 -#define NVACC_NV41_FBTIL9PT 0x00100698 -#define NVACC_NV41_FBTIL9ST 0x0010069c -#define NVACC_NV41_FBTILAAD 0x001006a0 -#define NVACC_NV41_FBTILAED 0x001006a4 -#define NVACC_NV41_FBTILAPT 0x001006a8 -#define NVACC_NV41_FBTILAST 0x001006ac -#define NVACC_NV41_FBTILBAD 0x001006b0 -#define NVACC_NV41_FBTILBED 0x001006b4 -#define NVACC_NV41_FBTILBPT 0x001006b8 -#define NVACC_NV41_FBTILBST 0x001006bc -#define NVACC_G70_FBTILCAD 0x001006c0 -#define NVACC_G70_FBTILCED 0x001006c4 -#define NVACC_G70_FBTILCPT 0x001006c8 -#define NVACC_G70_FBTILCST 0x001006cc -#define NVACC_G70_FBTILDAD 0x001006d0 -#define NVACC_G70_FBTILDED 0x001006d4 -#define NVACC_G70_FBTILDPT 0x001006d8 -#define NVACC_G70_FBTILDST 0x001006dc -#define NVACC_G70_FBTILEAD 0x001006e0 -#define NVACC_G70_FBTILEED 0x001006e4 -#define NVACC_G70_FBTILEPT 0x001006e8 -#define NVACC_G70_FBTILEST 0x001006ec -/* engine tile registers dst */ -#define NVACC_NV20_WHAT_T0 0x004009a4 -#define NVACC_NV20_WHAT_T1 0x004009a8 -#define NVACC_NV40_WHAT_T2 0x004069a4 -#define NVACC_NV40_WHAT_T3 0x004069a8 -#define NVACC_NV40P_WHAT_T0 0x004009f0 -#define NVACC_NV40P_WHAT_T1 0x004009f4 -#define NVACC_G70_WHAT_T0 0x00400df0 -#define NVACC_G70_WHAT_T1 0x00400df4 -#define NVACC_NV40P_WHAT_T2 0x004069f0 -#define NVACC_NV40P_WHAT_T3 0x004069f4 -#define NVACC_NV10_TIL0AD 0x00400b00 -#define NVACC_NV10_TIL0ED 0x00400b04 -#define NVACC_NV10_TIL0PT 0x00400b08 -#define NVACC_NV10_TIL0ST 0x00400b0c -#define NVACC_NV10_TIL1AD 0x00400b10 -#define NVACC_NV10_TIL1ED 0x00400b14 -#define NVACC_NV10_TIL1PT 0x00400b18 -#define NVACC_NV10_TIL1ST 0x00400b1c -#define NVACC_NV10_TIL2AD 0x00400b20 -#define NVACC_NV10_TIL2ED 0x00400b24 -#define NVACC_NV10_TIL2PT 0x00400b28 -#define NVACC_NV10_TIL2ST 0x00400b2c -#define NVACC_NV10_TIL3AD 0x00400b30 -#define NVACC_NV10_TIL3ED 0x00400b34 -#define NVACC_NV10_TIL3PT 0x00400b38 -#define NVACC_NV10_TIL3ST 0x00400b3c -#define NVACC_NV10_TIL4AD 0x00400b40 -#define NVACC_NV10_TIL4ED 0x00400b44 -#define NVACC_NV10_TIL4PT 0x00400b48 -#define NVACC_NV10_TIL4ST 0x00400b4c -#define NVACC_NV10_TIL5AD 0x00400b50 -#define NVACC_NV10_TIL5ED 0x00400b54 -#define NVACC_NV10_TIL5PT 0x00400b58 -#define NVACC_NV10_TIL5ST 0x00400b5c -#define NVACC_NV10_TIL6AD 0x00400b60 -#define NVACC_NV10_TIL6ED 0x00400b64 -#define NVACC_NV10_TIL6PT 0x00400b68 -#define NVACC_NV10_TIL6ST 0x00400b6c -#define NVACC_NV10_TIL7AD 0x00400b70 -#define NVACC_NV10_TIL7ED 0x00400b74 -#define NVACC_NV10_TIL7PT 0x00400b78 -#define NVACC_NV10_TIL7ST 0x00400b7c -/* cache setup registers */ -#define NVACC_PF_INTSTAT 0x00002100 -#define NVACC_PF_INTEN 0x00002140 -#define NVACC_PF_RAMHT 0x00002210 -#define NVACC_PF_RAMFC 0x00002214 -#define NVACC_PF_RAMRO 0x00002218 -#define NVACC_PF_CACHES 0x00002500 -#define NVACC_PF_MODE 0x00002504 -#define NVACC_PF_SIZE 0x0000250c -#define NVACC_PF_CACH0_PSH0 0x00003000 -#define NVACC_PF_CACH0_PUL0 0x00003050 -#define NVACC_PF_CACH0_PUL1 0x00003054 -#define NVACC_PF_CACH1_PSH0 0x00003200 -#define NVACC_PF_CACH1_PSH1 0x00003204 -#define NVACC_PF_CACH1_DMAS 0x00003220 -#define NVACC_PF_CACH1_DMAF 0x00003224 -#define NVACC_PF_CACH1_DMAI 0x0000322c -#define NVACC_PF_CACH1_DMAC 0x00003230 -#define NVACC_PF_CACH1_DMAP 0x00003240 -#define NVACC_PF_CACH1_DMAG 0x00003244 -#define NVACC_PF_CACH1_PUL0 0x00003250 -#define NVACC_PF_CACH1_PUL1 0x00003254 -#define NVACC_PF_CACH1_HASH 0x00003258 -#define NVACC_PF_CACH1_ENG 0x00003280 -/* Ptimer registers */ -#define NVACC_PT_INTSTAT 0x00009100 -#define NVACC_PT_INTEN 0x00009140 -#define NVACC_PT_NUMERATOR 0x00009200 -#define NVACC_PT_DENOMINATR 0x00009210 -/* used PRAMIN registers */ -#define NVACC_PR_CTX0_R 0x00711400 -#define NVACC_PR_CTX1_R 0x00711404 -#define NVACC_PR_CTX2_R 0x00711408 -#define NVACC_PR_CTX3_R 0x0071140c -#define NVACC_PR_CTX0_0 0x00711420 -#define NVACC_PR_CTX1_0 0x00711424 -#define NVACC_PR_CTX2_0 0x00711428 -#define NVACC_PR_CTX3_0 0x0071142c -#define NVACC_PR_CTX0_1 0x00711430 -#define NVACC_PR_CTX1_1 0x00711434 -#define NVACC_PR_CTX2_1 0x00711438 -#define NVACC_PR_CTX3_1 0x0071143c -#define NVACC_PR_CTX0_2 0x00711440 -#define NVACC_PR_CTX1_2 0x00711444 -#define NVACC_PR_CTX2_2 0x00711448 -#define NVACC_PR_CTX3_2 0x0071144c -#define NVACC_PR_CTX0_3 0x00711450 -#define NVACC_PR_CTX1_3 0x00711454 -#define NVACC_PR_CTX2_3 0x00711458 -#define NVACC_PR_CTX3_3 0x0071145c -#define NVACC_PR_CTX0_4 0x00711460 -#define NVACC_PR_CTX1_4 0x00711464 -#define NVACC_PR_CTX2_4 0x00711468 -#define NVACC_PR_CTX3_4 0x0071146c -#define NVACC_PR_CTX0_5 0x00711470 -#define NVACC_PR_CTX1_5 0x00711474 -#define NVACC_PR_CTX2_5 0x00711478 -#define NVACC_PR_CTX3_5 0x0071147c -#define NVACC_PR_CTX0_6 0x00711480 -#define NVACC_PR_CTX1_6 0x00711484 -#define NVACC_PR_CTX2_6 0x00711488 -#define NVACC_PR_CTX3_6 0x0071148c -#define NVACC_PR_CTX0_7 0x00711490 -#define NVACC_PR_CTX1_7 0x00711494 -#define NVACC_PR_CTX2_7 0x00711498 -#define NVACC_PR_CTX3_7 0x0071149c -#define NVACC_PR_CTX0_8 0x007114a0 -#define NVACC_PR_CTX1_8 0x007114a4 -#define NVACC_PR_CTX2_8 0x007114a8 -#define NVACC_PR_CTX3_8 0x007114ac -#define NVACC_PR_CTX0_9 0x007114b0 -#define NVACC_PR_CTX1_9 0x007114b4 -#define NVACC_PR_CTX2_9 0x007114b8 -#define NVACC_PR_CTX3_9 0x007114bc -#define NVACC_PR_CTX0_A 0x007114c0 -#define NVACC_PR_CTX1_A 0x007114c4 /* not used */ -#define NVACC_PR_CTX2_A 0x007114c8 -#define NVACC_PR_CTX3_A 0x007114cc -#define NVACC_PR_CTX0_B 0x007114d0 -#define NVACC_PR_CTX1_B 0x007114d4 -#define NVACC_PR_CTX2_B 0x007114d8 -#define NVACC_PR_CTX3_B 0x007114dc -#define NVACC_PR_CTX0_C 0x007114e0 -#define NVACC_PR_CTX1_C 0x007114e4 -#define NVACC_PR_CTX2_C 0x007114e8 -#define NVACC_PR_CTX3_C 0x007114ec -#define NVACC_PR_CTX0_D 0x007114f0 -#define NVACC_PR_CTX1_D 0x007114f4 -#define NVACC_PR_CTX2_D 0x007114f8 -#define NVACC_PR_CTX3_D 0x007114fc -#define NVACC_PR_CTX0_E 0x00711500 -#define NVACC_PR_CTX1_E 0x00711504 -#define NVACC_PR_CTX2_E 0x00711508 -#define NVACC_PR_CTX3_E 0x0071150c -#define NVACC_PR_CTX0_F 0x00711510 -#define NVACC_PR_CTX1_F 0x00711514 -#define NVACC_PR_CTX2_F 0x00711518 -#define NVACC_PR_CTX3_F 0x0071151c -#define NVACC_PR_CTX0_10 0x00711520 -#define NVACC_PR_CTX1_10 0x00711524 -#define NVACC_PR_CTX2_10 0x00711528 -#define NVACC_PR_CTX3_10 0x0071152c -/* used RAMHT registers (hash-table) */ -#define NVACC_HT_HANDL_00 0x00710000 -#define NVACC_HT_VALUE_00 0x00710004 -#define NVACC_HT_HANDL_01 0x00710008 -#define NVACC_HT_VALUE_01 0x0071000c -#define NVACC_HT_HANDL_02 0x00710010 -#define NVACC_HT_VALUE_02 0x00710014 -#define NVACC_HT_HANDL_03 0x00710018 -#define NVACC_HT_VALUE_03 0x0071001c -#define NVACC_HT_HANDL_04 0x00710020 -#define NVACC_HT_VALUE_04 0x00710024 -#define NVACC_HT_HANDL_05 0x00710028 -#define NVACC_HT_VALUE_05 0x0071002c -#define NVACC_HT_HANDL_06 0x00710030 -#define NVACC_HT_VALUE_06 0x00710034 -#define NVACC_HT_HANDL_10 0x00710080 -#define NVACC_HT_VALUE_10 0x00710084 -#define NVACC_HT_HANDL_11 0x00710088 -#define NVACC_HT_VALUE_11 0x0071008c -#define NVACC_HT_HANDL_12 0x00710090 -#define NVACC_HT_VALUE_12 0x00710094 -#define NVACC_HT_HANDL_13 0x00710098 -#define NVACC_HT_VALUE_13 0x0071009c -#define NVACC_HT_HANDL_14 0x007100a0 -#define NVACC_HT_VALUE_14 0x007100a4 -#define NVACC_HT_HANDL_15 0x007100a8 -#define NVACC_HT_VALUE_15 0x007100ac -#define NVACC_HT_HANDL_16 0x007100b0 -#define NVACC_HT_VALUE_16 0x007100b4 -#define NVACC_HT_HANDL_17 0x007100b8 -#define NVACC_HT_VALUE_17 0x007100bc - -/* acc engine fifo setup registers (for function_register 'mappings') */ -#define NVACC_FIFO 0x00800000 -#define NVACC_FIFO_CH0 0x00800000 -#define NVACC_FIFO_CH1 0x00802000 -#define NVACC_FIFO_CH2 0x00804000 -#define NVACC_FIFO_CH3 0x00806000 -#define NVACC_FIFO_CH4 0x00808000 -#define NVACC_FIFO_CH5 0x0080a000 -#define NVACC_FIFO_CH6 0x0080c000 -#define NVACC_FIFO_CH7 0x0080e000 - -/* Nvidia PCI direct registers */ -#define NV32_PWRUPCTRL 0x00000200 -#define NV32_DUALHEAD_CTRL 0x000010f0//verify!!! -#define NV8_MISCW 0x000c03c2 -#define NV8_MISCR 0x000c03cc -#define NV8_VSE2 0x000c03c3 -#define NV8_SEQIND 0x000c03c4 -#define NV16_SEQIND 0x000c03c4 -#define NV8_SEQDAT 0x000c03c5 -#define NV8_GRPHIND 0x000c03ce -#define NV16_GRPHIND 0x000c03ce -#define NV8_GRPHDAT 0x000c03cf - -/* bootstrap info registers */ -#define NV32_NV4STRAPINFO 0x00100000 -#define NV32_PFB_CONFIG_0 0x00100200 -#define NV32_PFB_CONFIG_1 0x00100204 -#define NV32_NV10STRAPINFO 0x0010020c -#define NV32_FB_MRS1 0x001002c0 -#define NV32_FB_MRS2 0x001002c8 -#define NV32_PFB_CLS_PAGE2 0x0010033c -#define NV32_NVSTRAPINFO2 0x00101000 - -/* registers needed for 'coldstart' */ -#define NV32_PFB_DEBUG_0 0x00100080 -#define NV32_PFB_REFCTRL 0x00100210 -#define NV32_COREPLL 0x00680500 -#define NV32_MEMPLL 0x00680504 -#define NV32_PLL_CTRL 0x00680510 -#define NV32_COREPLL2 0x00680570 /* NV31, NV36 only */ -#define NV32_MEMPLL2 0x00680574 /* NV31, NV36 only */ -#define NV32_CONFIG 0x00600804 - -/* primary head */ -#define NV8_ATTRINDW 0x006013c0 -#define NV8_ATTRDATW 0x006013c0 -#define NV8_ATTRDATR 0x006013c1 -#define NV8_CRTCIND 0x006013d4 -#define NV16_CRTCIND 0x006013d4 -#define NV8_CRTCDAT 0x006013d5 -#define NV8_INSTAT1 0x006013da -#define NV32_NV10FBSTADD32 0x00600800 -#define NV32_RASTER 0x00600808 -#define NV32_NV10CURADD32 0x0060080c -#define NV32_CURCONF 0x00600810 -#define NV32_PANEL_PWR 0x0060081c -#define NV32_FUNCSEL 0x00600860 - -/* secondary head */ -#define NV8_ATTR2INDW 0x006033c0 -#define NV8_ATTR2DATW 0x006033c0 -#define NV8_ATTR2DATR 0x006033c1 -#define NV8_CRTC2IND 0x006033d4 -#define NV16_CRTC2IND 0x006033d4 -#define NV8_CRTC2DAT 0x006033d5 -#define NV8_2INSTAT1 0x006033da//verify!!! -#define NV32_NV10FB2STADD32 0x00602800 -#define NV32_RASTER2 0x00602808 -#define NV32_NV10CUR2ADD32 0x0060280c -#define NV32_2CURCONF 0x00602810 -#define NV32_2PANEL_PWR 0x0060281c//verify!!! -#define NV32_2FUNCSEL 0x00602860 - -/* both heads */ -#define NVACC_NV11_CRTC_LO 0x00600830 -#define NVACC_NV11_CRTC_HI 0x00600834 - -/* Nvidia DAC direct registers (standard VGA palette RAM registers) */ -/* primary head */ -#define NV8_PALMASK 0x006813c6 -#define NV8_PALINDR 0x006813c7 -#define NV8_PALINDW 0x006813c8 -#define NV8_PALDATA 0x006813c9 -/* secondary head */ -#define NV8_PAL2MASK 0x006833c6 -#define NV8_PAL2INDR 0x006833c7 -#define NV8_PAL2INDW 0x006833c8 -#define NV8_PAL2DATA 0x006833c9 - -/* Nvidia PCI direct DAC registers (32bit) */ -/* primary head */ -#define NVDAC_CURPOS 0x00680300 -#define NVDAC_NV10_CURSYNC 0x00680404 -#define NVDAC_PIXPLLC 0x00680508 -#define NVDAC_PLLSEL 0x0068050c -#define NVDAC_OUTPUT 0x0068052c -#define NVDAC_PIXPLLC2 0x00680578 -#define NVDAC_GENCTRL 0x00680600 -#define NVDAC_TSTCTRL 0x00680608 -#define NVDAC_TSTDATA 0x00680610 -#define NVDAC_TV_SETUP 0x00680700 -/* (flatpanel registers: confirmed for TNT2 and up) */ -#define NVDAC_FP_VDISPEND 0x00680800 -#define NVDAC_FP_VTOTAL 0x00680804 -#define NVDAC_FP_VCRTC 0x00680808 -#define NVDAC_FP_VSYNC_S 0x0068080c -#define NVDAC_FP_VSYNC_E 0x00680810 -#define NVDAC_FP_VVALID_S 0x00680814 -#define NVDAC_FP_VVALID_E 0x00680818 -#define NVDAC_FP_HDISPEND 0x00680820 -#define NVDAC_FP_HTOTAL 0x00680824 -#define NVDAC_FP_HCRTC 0x00680828 -#define NVDAC_FP_HSYNC_S 0x0068082c -#define NVDAC_FP_HSYNC_E 0x00680830 -#define NVDAC_FP_HVALID_S 0x00680834 -#define NVDAC_FP_HVALID_E 0x00680838 -#define NVDAC_FP_CHKSUM 0x00680840 -#define NVDAC_FP_TST_CTRL 0x00680844 -#define NVDAC_FP_TG_CTRL 0x00680848 -#define NVDAC_FP_DEBUG0 0x00680880 -#define NVDAC_FP_DEBUG1 0x00680884 -#define NVDAC_FP_DEBUG2 0x00680888 -#define NVDAC_FP_DEBUG3 0x0068088c -#define NVDAC_FP_TMDS_CTRL 0x006808b0 -#define NVDAC_FP_TMDS_DATA 0x006808b4 -/* secondary head */ -#define NVDAC2_CURPOS 0x00682300 -#define NVDAC2_NV10_CURSYNC 0x00682404 -#define NVDAC2_PIXPLLC 0x00680520 -#define NVDAC2_OUTPUT 0x0068252c -#define NVDAC2_PIXPLLC2 0x0068057c -#define NVDAC2_GENCTRL 0x00682600 -#define NVDAC2_TSTCTRL 0x00682608 -#define NVDAC2_TV_SETUP 0x00682700 -/* (flatpanel registers) */ -#define NVDAC2_FP_VDISPEND 0x00682800 -#define NVDAC2_FP_VTOTAL 0x00682804 -#define NVDAC2_FP_VCRTC 0x00682808 -#define NVDAC2_FP_VSYNC_S 0x0068280c -#define NVDAC2_FP_VSYNC_E 0x00682810 -#define NVDAC2_FP_VVALID_S 0x00682814 -#define NVDAC2_FP_VVALID_E 0x00682818 -#define NVDAC2_FP_HDISPEND 0x00682820 -#define NVDAC2_FP_HTOTAL 0x00682824 -#define NVDAC2_FP_HCRTC 0x00682828 -#define NVDAC2_FP_HSYNC_S 0x0068282c -#define NVDAC2_FP_HSYNC_E 0x00682830 -#define NVDAC2_FP_HVALID_S 0x00682834 -#define NVDAC2_FP_HVALID_E 0x00682838 -#define NVDAC2_FP_CHKSUM 0x00682840 -#define NVDAC2_FP_TST_CTRL 0x00682844 -#define NVDAC2_FP_TG_CTRL 0x00682848 -#define NVDAC2_FP_DEBUG0 0x00682880 -#define NVDAC2_FP_DEBUG1 0x00682884 -#define NVDAC2_FP_DEBUG2 0x00682888 -#define NVDAC2_FP_DEBUG3 0x0068288c -#define NVDAC2_FP_TMDS_CTRL 0x006828b0//verify!!! -#define NVDAC2_FP_TMDS_DATA 0x006828b4//verify!!! - -/* Nvidia CRTC indexed registers */ -/* VGA standard registers: */ -#define NVCRTCX_HTOTAL 0x00 -#define NVCRTCX_HDISPE 0x01 -#define NVCRTCX_HBLANKS 0x02 -#define NVCRTCX_HBLANKE 0x03 -#define NVCRTCX_HSYNCS 0x04 -#define NVCRTCX_HSYNCE 0x05 -#define NVCRTCX_VTOTAL 0x06 -#define NVCRTCX_OVERFLOW 0x07 -#define NVCRTCX_PRROWSCN 0x08 -#define NVCRTCX_MAXSCLIN 0x09 -#define NVCRTCX_VGACURCTRL 0x0a -#define NVCRTCX_FBSTADDH 0x0c -#define NVCRTCX_FBSTADDL 0x0d -#define NVCRTCX_VSYNCS 0x10 -#define NVCRTCX_VSYNCE 0x11 -#define NVCRTCX_VDISPE 0x12 -#define NVCRTCX_PITCHL 0x13 -#define NVCRTCX_VBLANKS 0x15 -#define NVCRTCX_VBLANKE 0x16 -#define NVCRTCX_MODECTL 0x17 -#define NVCRTCX_LINECOMP 0x18 -/* Nvidia specific registers: */ -#define NVCRTCX_REPAINT0 0x19 -#define NVCRTCX_REPAINT1 0x1a -#define NVCRTCX_FIFO 0x1b -#define NVCRTCX_LOCK 0x1f -#define NVCRTCX_FIFO_LWM 0x20 -#define NVCRTCX_BUFFER 0x21 -#define NVCRTCX_LSR 0x25 -#define NVCRTCX_PIXEL 0x28 -#define NVCRTCX_HEB 0x2d -#define NVCRTCX_CURCTL2 0x2f -#define NVCRTCX_CURCTL1 0x30 -#define NVCRTCX_CURCTL0 0x31 -#define NVCRTCX_LCD 0x33 -#define NVCRTCX_RD_I2CBUS_1 0x36 -#define NVCRTCX_WR_I2CBUS_1 0x37 -#define NVCRTCX_RMA 0x38 -#define NVCRTCX_INTERLACE 0x39 -#define NVCRTCX_TREG 0x3d -#define NVCRTCX_RD_I2CBUS_0 0x3e -#define NVCRTCX_WR_I2CBUS_0 0x3f -#define NVCRTCX_EXTRA 0x41 -#define NVCRTCX_OWNER 0x44 -#define NVCRTCX_FP_HTIMING 0x53 -#define NVCRTCX_FP_VTIMING 0x54 -#define NVCRTCX_0x59 0x59 -#define NVCRTCX_0x9f 0x9f - -/* Nvidia ATTRIBUTE indexed registers */ -/* VGA standard registers: */ -#define NVATBX_MODECTL 0x10 -#define NVATBX_OSCANCOLOR 0x11 -#define NVATBX_COLPLANE_EN 0x12 -#define NVATBX_HORPIXPAN 0x13 -#define NVATBX_COLSEL 0x14 - -/* Nvidia SEQUENCER indexed registers */ -/* VGA standard registers: */ -#define NVSEQX_RESET 0x00 -#define NVSEQX_CLKMODE 0x01 -#define NVSEQX_MEMMODE 0x04 - -/* Nvidia GRAPHICS indexed registers */ -/* VGA standard registers: */ -#define NVGRPHX_ENSETRESET 0x01 -#define NVGRPHX_DATAROTATE 0x03 -#define NVGRPHX_READMAPSEL 0x04 -#define NVGRPHX_MODE 0x05 -#define NVGRPHX_MISC 0x06 -#define NVGRPHX_BITMASK 0x08 - -/* Nvidia BES (Back End Scaler) registers (< NV10, including NV03, so RIVA128(ZX)) */ -#define NVBES_NV04_INTE 0x00680140 -#define NVBES_NV04_ISCALVH 0x00680200 -#define NVBES_NV04_CTRL_V 0x00680204 -#define NVBES_NV04_CTRL_H 0x00680208 -#define NVBES_NV04_OE_STATE 0x00680224 -#define NVBES_NV04_SU_STATE 0x00680228 -#define NVBES_NV04_RM_STATE 0x0068022c -#define NVBES_NV04_DSTREF 0x00680230 -#define NVBES_NV04_DSTSIZE 0x00680234 -#define NVBES_NV04_FIFOTHRS 0x00680238 -#define NVBES_NV04_FIFOBURL 0x0068023c -#define NVBES_NV04_COLKEY 0x00680240 -#define NVBES_NV04_GENCTRL 0x00680244 -#define NVBES_NV04_RED_AMP 0x00680280 -#define NVBES_NV04_GRN_AMP 0x00680284 -#define NVBES_NV04_BLU_AMP 0x00680288 -#define NVBES_NV04_SAT 0x0068028c -/* buffer 0 */ -#define NVBES_NV04_0BUFADR 0x0068020c -#define NVBES_NV04_0SRCPTCH 0x00680214 -#define NVBES_NV04_0OFFSET 0x0068021c -/* buffer 1 */ -#define NVBES_NV04_1BUFADR 0x00680210 -#define NVBES_NV04_1SRCPTCH 0x00680218 -#define NVBES_NV04_1OFFSET 0x00680220 - -/* Nvidia BES (Back End Scaler) registers (>= NV10) */ -#define NVBES_NV10_INTE 0x00008140 -#define NVBES_NV10_BUFSEL 0x00008700 -#define NVBES_NV10_GENCTRL 0x00008704 -#define NVBES_NV10_COLKEY 0x00008b00 -/* buffer 0 */ -#define NVBES_NV10_0BUFADR 0x00008900 -#define NVBES_NV10_0MEMMASK 0x00008908 -#define NVBES_NV10_0BRICON 0x00008910 -#define NVBES_NV10_0SAT 0x00008918 -#define NVBES_NV10_0OFFSET 0x00008920 -#define NVBES_NV10_0SRCSIZE 0x00008928 -#define NVBES_NV10_0SRCREF 0x00008930 -#define NVBES_NV10_0ISCALH 0x00008938 -#define NVBES_NV10_0ISCALV 0x00008940 -#define NVBES_NV10_0DSTREF 0x00008948 -#define NVBES_NV10_0DSTSIZE 0x00008950 -#define NVBES_NV10_0SRCPTCH 0x00008958 -/* buffer 1 */ -#define NVBES_NV10_1BUFADR 0x00008904 -#define NVBES_NV10_1MEMMASK 0x0000890c -#define NVBES_NV10_1BRICON 0x00008914 -#define NVBES_NV10_1SAT 0x0000891c -#define NVBES_NV10_1OFFSET 0x00008924 -#define NVBES_NV10_1SRCSIZE 0x0000892c -#define NVBES_NV10_1SRCREF 0x00008934 -#define NVBES_NV10_1ISCALH 0x0000893c -#define NVBES_NV10_1ISCALV 0x00008944 -#define NVBES_NV10_1DSTREF 0x0000894c -#define NVBES_NV10_1DSTSIZE 0x00008954 -#define NVBES_NV10_1SRCPTCH 0x0000895c -/* Nvidia MPEG2 hardware decoder (GeForce4MX only) */ -#define NVBES_DEC_GENCTRL 0x00001588 -/* LVDS panel related registers */ -#define NV32_LVDS_PWR 0x0000130c -/* unknown registers */ -#define NV32_NV4X_WHAT0 0x00001540 -#define NV32_NV44_WHAT10 0x00001700 -#define NV32_NV44_WHAT11 0x00001704 -#define NV32_NV44_WHAT12 0x00001708 -#define NV32_NV44_WHAT13 0x0000170c - -/* Macros for convenient accesses to the NV chips */ -#define NV_REG8(r_) ((vuint8 *)regs)[(r_)] -#define NV_REG16(r_) ((vuint16 *)regs)[(r_) >> 1] -#define NV_REG32(r_) ((vuint32 *)regs)[(r_) >> 2] - -/* read and write to PCI config space */ -#define CFGR(A) (*(nv_pci_access.offset=NVCFG_##A, ioctl(fd,NV_GET_PCI, &nv_pci_access,sizeof(nv_pci_access)), &nv_pci_access.value)) -#define CFGW(A,B) (nv_pci_access.offset=NVCFG_##A, nv_pci_access.value = B, ioctl(fd,NV_SET_PCI,&nv_pci_access,sizeof(nv_pci_access))) - -/* read and write from ISA I/O space */ -#define ISAWB(A,B)(nv_isa_access.adress=A, nv_isa_access.data = (uint8)B, nv_isa_access.size = 1, ioctl(fd,NV_ISA_OUT, &nv_isa_access,sizeof(nv_isa_access))) -#define ISAWW(A,B)(nv_isa_access.adress=A, nv_isa_access.data = B, nv_isa_access.size = 2, ioctl(fd,NV_ISA_OUT, &nv_isa_access,sizeof(nv_isa_access))) -#define ISARB(A) (nv_isa_access.adress=A, ioctl(fd,NV_ISA_IN, &nv_isa_access,sizeof(nv_isa_access)), (uint8)nv_isa_access.data) -#define ISARW(A) (nv_isa_access.adress=A, ioctl(fd,NV_ISA_IN, &nv_isa_access,sizeof(nv_isa_access)), nv_isa_access.data) - -/* read and write from the dac registers */ -#define DACR(A) (NV_REG32(NVDAC_##A)) -#define DACW(A,B) (NV_REG32(NVDAC_##A)=B) - -/* read and write from the secondary dac registers */ -#define DAC2R(A) (NV_REG32(NVDAC2_##A)) -#define DAC2W(A,B) (NV_REG32(NVDAC2_##A)=B) - -/* read and write from the backend scaler registers */ -#define BESR(A) (NV_REG32(NVBES_##A)) -#define BESW(A,B) (NV_REG32(NVBES_##A)=B) - -/* read and write from CRTC indexed registers */ -#define CRTCW(A,B)(NV_REG16(NV16_CRTCIND) = ((NVCRTCX_##A) | ((B) << 8))) -#define CRTCR(A) (NV_REG8(NV8_CRTCIND) = (NVCRTCX_##A), NV_REG8(NV8_CRTCDAT)) - -/* read and write from second CRTC indexed registers */ -#define CRTC2W(A,B)(NV_REG16(NV16_CRTC2IND) = ((NVCRTCX_##A) | ((B) << 8))) -#define CRTC2R(A) (NV_REG8(NV8_CRTC2IND) = (NVCRTCX_##A), NV_REG8(NV8_CRTC2DAT)) - -/* read and write from ATTRIBUTE indexed registers */ -#define ATBW(A,B)(NV_REG8(NV8_INSTAT1), NV_REG8(NV8_ATTRINDW) = ((NVATBX_##A) | 0x20), NV_REG8(NV8_ATTRDATW) = (B)) -#define ATBR(A) (NV_REG8(NV8_INSTAT1), NV_REG8(NV8_ATTRINDW) = ((NVATBX_##A) | 0x20), NV_REG8(NV8_ATTRDATR)) - -/* read and write from ATTRIBUTE indexed registers */ -#define ATB2W(A,B)(NV_REG8(NV8_INSTAT1), NV_REG8(NV8_ATTR2INDW) = ((NVATBX_##A) | 0x20), NV_REG8(NV8_ATTR2DATW) = (B)) -#define ATB2R(A) (NV_REG8(NV8_INSTAT1), NV_REG8(NV8_ATTR2INDW) = ((NVATBX_##A) | 0x20), NV_REG8(NV8_ATTR2DATR)) - -/* read and write from SEQUENCER indexed registers */ -#define SEQW(A,B)(NV_REG16(NV16_SEQIND) = ((NVSEQX_##A) | ((B) << 8))) -#define SEQR(A) (NV_REG8(NV8_SEQIND) = (NVSEQX_##A), NV_REG8(NV8_SEQDAT)) - -/* read and write from PCI GRAPHICS indexed registers */ -#define GRPHW(A,B)(NV_REG16(NV16_GRPHIND) = ((NVGRPHX_##A) | ((B) << 8))) -#define GRPHR(A) (NV_REG8(NV8_GRPHIND) = (NVGRPHX_##A), NV_REG8(NV8_GRPHDAT)) - -/* read and write from the acceleration engine registers */ -#define ACCR(A) (NV_REG32(NVACC_##A)) -#define ACCW(A,B) (NV_REG32(NVACC_##A)=B) diff --git a/src/add-ons/accelerants/Jamfile b/src/add-ons/accelerants/Jamfile index a709cb20da..805d6edf95 100644 --- a/src/add-ons/accelerants/Jamfile +++ b/src/add-ons/accelerants/Jamfile @@ -8,7 +8,6 @@ SubInclude HAIKU_TOP src add-ons accelerants intel_810 ; SubInclude HAIKU_TOP src add-ons accelerants intel_extreme ; SubInclude HAIKU_TOP src add-ons accelerants matrox ; SubInclude HAIKU_TOP src add-ons accelerants neomagic ; -SubInclude HAIKU_TOP src add-ons accelerants nvidia_gpgpu ; SubInclude HAIKU_TOP src add-ons accelerants nvidia ; SubInclude HAIKU_TOP src add-ons accelerants radeon ; SubInclude HAIKU_TOP src add-ons accelerants radeon_hd ; diff --git a/src/add-ons/accelerants/nvidia_gpgpu/Acceleration.c b/src/add-ons/accelerants/nvidia_gpgpu/Acceleration.c deleted file mode 100644 index b87299090a..0000000000 --- a/src/add-ons/accelerants/nvidia_gpgpu/Acceleration.c +++ /dev/null @@ -1,18 +0,0 @@ -/* - Copyright 1999, Be Incorporated. All Rights Reserved. - This file may be used under the terms of the Be Sample Code License. - - Other authors: - Rudolf Cornelissen 9/2003-6/2008. -*/ - -/* - note: - moved DMA acceleration 'top-level' routines to be integrated in the engine: - it is costly to call the engine for every single function within a loop! - (measured with BeRoMeter 1.2.6: upto 15% speed increase on all CPU's.) -*/ - -#define MODULE_BIT 0x40000000 - -#include "acc_std.h" diff --git a/src/add-ons/accelerants/nvidia_gpgpu/Cursor.c b/src/add-ons/accelerants/nvidia_gpgpu/Cursor.c deleted file mode 100644 index f7380279ef..0000000000 --- a/src/add-ons/accelerants/nvidia_gpgpu/Cursor.c +++ /dev/null @@ -1,194 +0,0 @@ -/* - Copyright 1999, Be Incorporated. All Rights Reserved. - This file may be used under the terms of the Be Sample Code License. - - Other authors: - Mark Watson, - Rudolf Cornelissen 4/2003-6/2008 -*/ - -#define MODULE_BIT 0x20000000 - -#include "acc_std.h" - -status_t SET_CURSOR_SHAPE(uint16 width, uint16 height, uint16 hot_x, uint16 hot_y, uint8 *andMask, uint8 *xorMask) -{ - LOG(4,("SET_CURSOR_SHAPE: width %d, height %d, hot_x %d, hot_y %d\n", - width, height, hot_x, hot_y)); - - if ((width != 16) || (height != 16)) - { - return B_ERROR; - } - else if ((hot_x >= width) || (hot_y >= height)) - { - return B_ERROR; - } - else - { - head1_cursor_define(andMask,xorMask); - if ((si->dm.flags & DUALHEAD_BITS) != DUALHEAD_OFF) - head2_cursor_define(andMask,xorMask); - - /* Update cursor variables appropriately. */ - si->cursor.width = width; - si->cursor.height = height; - si->cursor.hot_x = hot_x; - si->cursor.hot_y = hot_y; - } - - return B_OK; -} - -/* Move the cursor to the specified position on the desktop, taking account of virtual/dual issues */ -void MOVE_CURSOR(uint16 x, uint16 y) -{ - uint16 hds = si->dm.h_display_start; /* the current horizontal starting pixel */ - uint16 vds = si->dm.v_display_start; /* the current vertical starting line */ - uint16 h_adjust; - - /* clamp cursor to display */ - if (x >= si->dm.virtual_width) x = si->dm.virtual_width - 1; - if (y >= si->dm.virtual_height) y = si->dm.virtual_height - 1; - - /* store, for our info */ - si->cursor.x = x; - si->cursor.y = y; - - /* setting up minimum amount to scroll not needed: - * Nvidia cards can always do pixelprecise panning on both heads */ - h_adjust = 0x00; - - /* adjust h/v_display_start to move cursor onto screen */ - switch (si->dm.flags & DUALHEAD_BITS) - { - case DUALHEAD_ON: - case DUALHEAD_SWITCH: - if (x >= ((si->dm.timing.h_display * 2) + hds)) - { - hds = ((x - (si->dm.timing.h_display * 2)) + 1 + h_adjust) & ~h_adjust; - /* make sure we stay within the display! */ - if ((hds + (si->dm.timing.h_display * 2)) > si->dm.virtual_width) - hds -= (h_adjust + 1); - } - else if (x < hds) - hds = x & ~h_adjust; - break; - default: - if (x >= (si->dm.timing.h_display + hds)) - { - hds = ((x - si->dm.timing.h_display) + 1 + h_adjust) & ~h_adjust; - /* make sure we stay within the display! */ - if ((hds + si->dm.timing.h_display) > si->dm.virtual_width) - hds -= (h_adjust + 1); - } - else if (x < hds) - hds = x & ~h_adjust; - break; - } - - if (y >= (si->dm.timing.v_display + vds)) - vds = y - si->dm.timing.v_display + 1; - else if (y < vds) - vds = y; - - /* reposition the desktop _and_ the overlay on the display if required */ - if ((hds!=si->dm.h_display_start) || (vds!=si->dm.v_display_start)) - { - MOVE_DISPLAY(hds,vds); - } - - /* put cursor in correct physical position, so stay onscreen (rel. to CRTC) */ - if (x > (hds + si->cursor.hot_x)) x -= (hds + si->cursor.hot_x); - else x = 0; - if (y > (vds + si->cursor.hot_y)) y -= (vds + si->cursor.hot_y); - else y = 0; - - /* position the cursor on the display */ - switch (si->dm.flags & DUALHEAD_BITS) - { - case DUALHEAD_CLONE: - head1_cursor_position(x,y); - head2_cursor_position(x,y); - break; - case DUALHEAD_ON: - case DUALHEAD_SWITCH: - if (x < si->dm.timing.h_display) - { - if (si->cursor.dh_right) - { - LOG(4,("MOVE_CURSOR: now on left side\n")); - head2_cursor_hide(); - head1_cursor_show(); - si->cursor.dh_right = false; - } - head1_cursor_position(x, y); - } - else - { - if (!si->cursor.dh_right) - { - LOG(4,("MOVE_CURSOR: now on right side\n")); - head1_cursor_hide(); - head2_cursor_show(); - si->cursor.dh_right = true; - } - head2_cursor_position((x - si->dm.timing.h_display), y); - } - break; - default: /* singlehead mode */ - head1_cursor_position(x,y); - break; - } -} - -void SHOW_CURSOR(bool is_visible) -{ - /* record for our info */ - si->cursor.is_visible = is_visible; - - switch (si->dm.flags & DUALHEAD_BITS) - { - case DUALHEAD_CLONE: - if (is_visible) - { - head1_cursor_show(); - head2_cursor_show(); - } - else - { - head1_cursor_hide(); - head2_cursor_hide(); - } - break; - case DUALHEAD_ON: - case DUALHEAD_SWITCH: - if (is_visible) - { - if (!si->cursor.dh_right) - { - head1_cursor_show(); - } - else - { - head2_cursor_show(); - } - } - else - { - head1_cursor_hide(); - head2_cursor_hide(); - } - break; - default: /* singlehead mode */ - if (is_visible) - { - head1_cursor_show(); - } - else - { - head1_cursor_hide(); - } - break; - } -} diff --git a/src/add-ons/accelerants/nvidia_gpgpu/EngineManagment.c b/src/add-ons/accelerants/nvidia_gpgpu/EngineManagment.c deleted file mode 100644 index 7c584732c0..0000000000 --- a/src/add-ons/accelerants/nvidia_gpgpu/EngineManagment.c +++ /dev/null @@ -1,73 +0,0 @@ -/* - Copyright 1999, Be Incorporated. All Rights Reserved. - This file may be used under the terms of the Be Sample Code License. - - other authors: - Mark Watson - Rudolf Cornelissen 3/2004-6/2008 -*/ - -#define MODULE_BIT 0x10000000 - -#include "acc_std.h" - - -static engine_token nv_engine_token = { 1, B_2D_ACCELERATION, NULL }; - -uint32 ACCELERANT_ENGINE_COUNT(void) -{ - /* we have one acceleration engine */ - return 1; -} - -status_t ACQUIRE_ENGINE_DMA(uint32 capabilities, uint32 max_wait, sync_token *st, engine_token **et) -{ - /* acquire the shared benaphore */ - AQUIRE_BEN(si->engine.lock) - /* sync if required */ - if (st) SYNC_TO_TOKEN(st); - - /* make sure all needed engine cmd's are mapped to the FIFO */ - nv_acc_assert_fifo_dma(); - - /* return an engine token */ - *et = &nv_engine_token; - return B_OK; -} - -status_t RELEASE_ENGINE(engine_token *et, sync_token *st) -{ - /* update the sync token, if any */ - if (st) GET_SYNC_TOKEN(et,st); - - /* release the shared benaphore */ - RELEASE_BEN(si->engine.lock) - return B_OK; -} - -void WAIT_ENGINE_IDLE(void) -{ - /*wait for the engine to be totally idle*/ - nv_acc_wait_idle_dma(); -} - -status_t GET_SYNC_TOKEN(engine_token *et, sync_token *st) -{ - /* engine count will always be zero: we don't support syncing to token (yet) */ - st->engine_id = et->engine_id; - st->counter = si->engine.count; - return B_OK; -} - -status_t SYNC_TO_TOKEN(sync_token *st) -{ - /* wait until the engine is totally idle: we don't support syncing to token (yet) */ - /* note: - * AFAIK in order to be able to setup sync_to_token, we'd need a circular fifo - * buffer in (main) memory instead of directly programming the GPU fifo so we - * can tell (via a hardware maintained pointer into this circular fifo) where - * the acc engine is with executing commands! */ - WAIT_ENGINE_IDLE(); - - return B_OK; -} diff --git a/src/add-ons/accelerants/nvidia_gpgpu/GetAccelerantHook.c b/src/add-ons/accelerants/nvidia_gpgpu/GetAccelerantHook.c deleted file mode 100644 index d55042ab70..0000000000 --- a/src/add-ons/accelerants/nvidia_gpgpu/GetAccelerantHook.c +++ /dev/null @@ -1,176 +0,0 @@ -/* - Copyright 1999, Be Incorporated. All Rights Reserved. - This file may be used under the terms of the Be Sample Code License. - - Other authors: - Mark Watson, - Rudolf Cornelissen 10/2002-6/2008 -*/ - -#define MODULE_BIT 0x08000000 - -#include "acc_std.h" - -/* -The standard entry point. Given a uint32 feature identifier, this routine -returns a pointer to the function that implements the feature. Some features -require more information than just the identifier to select the proper -function. The extra information (which is specific to the feature) is -pointed at by the void *data parameter. By default, no extra information -is available. Any extra information available to choose the function will be -noted on a case by case below. -*/ - -/* -These definitions are out of pure lazyness. -*/ -#define CHKA(x) case B_##x: \ - if (check_acc_capability(B_##x) == B_OK) \ - return (void *)x##_DMA; \ - else \ - return (void *)0 -#define CHKS(x) case B_##x: return (void *)x##_DMA -#define HOOK(x) case B_##x: return (void *)x -#define ZERO(x) case B_##x: return (void *)0 -#define HRDC(x) case B_##x: return si->settings.hardcursor? (void *)x: (void *)0; // apsed - -void * get_accelerant_hook(uint32 feature, void *data) -{ - switch (feature) - { - /* - One of either B_INIT_ACCELERANT or B_CLONE_ACCELERANT will be requested and - subsequently called before any other hook is requested. All other feature - hook selections can be predicated on variables assigned during the accelerant - initialization process. - */ - - /* initialization */ - HOOK(INIT_ACCELERANT); - HOOK(CLONE_ACCELERANT); - - HOOK(ACCELERANT_CLONE_INFO_SIZE); - HOOK(GET_ACCELERANT_CLONE_INFO); - HOOK(UNINIT_ACCELERANT); - HOOK(GET_ACCELERANT_DEVICE_INFO); - HOOK(ACCELERANT_RETRACE_SEMAPHORE); - - /* mode configuration */ - HOOK(ACCELERANT_MODE_COUNT); - HOOK(GET_MODE_LIST); - HOOK(PROPOSE_DISPLAY_MODE); - HOOK(SET_DISPLAY_MODE); - HOOK(GET_DISPLAY_MODE); - HOOK(GET_FRAME_BUFFER_CONFIG); - HOOK(GET_PIXEL_CLOCK_LIMITS); - HOOK(MOVE_DISPLAY); - HOOK(SET_INDEXED_COLORS); - HOOK(GET_TIMING_CONSTRAINTS); - - HOOK(DPMS_CAPABILITIES); - HOOK(DPMS_MODE); - HOOK(SET_DPMS_MODE); - - /* cursor managment */ - //HRDC(SET_CURSOR_SHAPE); - //HRDC(MOVE_CURSOR); - //HRDC(SHOW_CURSOR); - - /* synchronization */ - HOOK(ACCELERANT_ENGINE_COUNT); - CHKS(ACQUIRE_ENGINE); - HOOK(RELEASE_ENGINE); - HOOK(WAIT_ENGINE_IDLE); - HOOK(GET_SYNC_TOKEN); - HOOK(SYNC_TO_TOKEN); - - /* - Depending on the engine architecture, you may choose to provide a different - function to be used with each bit-depth for example. - - Note: These hooks are re-acquired by the app_server after each mode switch. - */ - - /* video overlay functions are not supported */ - - /* - When requesting an acceleration hook, the calling application provides a - pointer to the display_mode for which the acceleration function will be used. - Depending on the engine architecture, you may choose to provide a different - function to be used with each bit-depth. In the sample driver we return - the same function all the time. - - Note: These hooks are re-acquired by the app_server after each mode switch. - */ - - /* only export 2D acceleration functions in modes that are capable of it */ - /* used by the app_server and applications (BWindowScreen) */ - //CHKA(SCREEN_TO_SCREEN_BLIT); - //CHKA(FILL_RECTANGLE); - //CHKA(INVERT_RECTANGLE); - //CHKA(FILL_SPAN); - /* not (yet) used by the app_server: - * so just for application use (BWindowScreen) */ -// CHKA(SCREEN_TO_SCREEN_TRANSPARENT_BLIT); - //CHKA(SCREEN_TO_SCREEN_SCALED_FILTERED_BLIT); - } - - /* Return a null pointer for any feature we don't understand. */ - return 0; -} -#undef CHKA -#undef CHKD -#undef HOOK -#undef ZERO -#undef HRDC - -status_t check_acc_capability(uint32 feature) -{ - char *msg = ""; - - /* setup logmessage text */ - switch (feature) - { - case B_SCREEN_TO_SCREEN_BLIT: - msg = "B_SCREEN_TO_SCREEN_BLIT"; - break; - case B_FILL_RECTANGLE: - msg = "B_FILL_RECTANGLE"; - break; - case B_INVERT_RECTANGLE: - msg = "B_INVERT_RECTANGLE"; - break; - case B_FILL_SPAN: - msg = "B_FILL_SPAN"; - break; - case B_SCREEN_TO_SCREEN_TRANSPARENT_BLIT: - msg = "B_SCREEN_TO_SCREEN_TRANSPARENT_BLIT"; - break; - case B_SCREEN_TO_SCREEN_SCALED_FILTERED_BLIT: - msg = "B_SCREEN_TO_SCREEN_SCALED_FILTERED_BLIT"; - /* this function doesn't support the B_CMAP8 colorspace */ - //fixme: checkout B_CMAP8 support sometime, as some cards seem to support it? - if (si->dm.space == B_CMAP8) - { - LOG(4, ("Acc: Not exporting hook %s.\n", msg)); - return B_ERROR; - } - break; - default: - msg = "UNKNOWN"; - break; - } - - /* hardware acceleration is only supported in modes with upto a certain - * memory pitch.. */ - if (si->acc_mode) - { - LOG(4, ("Acc: Exporting hook %s.\n", msg)); - return B_OK; - } - else - { - LOG(4, ("Acc: Not exporting hook %s.\n", msg)); - return B_ERROR; - } -} diff --git a/src/add-ons/accelerants/nvidia_gpgpu/GetDeviceInfo.c b/src/add-ons/accelerants/nvidia_gpgpu/GetDeviceInfo.c deleted file mode 100644 index dac99cdcc3..0000000000 --- a/src/add-ons/accelerants/nvidia_gpgpu/GetDeviceInfo.c +++ /dev/null @@ -1,25 +0,0 @@ -/* - Author: - Rudolf Cornelissen 7/2004-01/2006 -*/ - -#define MODULE_BIT 0x04000000 - -#include "acc_std.h" - -/* Get some info about the device */ -status_t GET_ACCELERANT_DEVICE_INFO(accelerant_device_info * adi) -{ - LOG(4,("GET_ACCELERANT_DEVICE_INFO: returning info\n")); - - /* no info on version is provided, so presumably this is for my info */ - adi->version = 1; - - sprintf(adi->name, si->adi.name); - sprintf(adi->chipset, si->adi.chipset); - sprintf(adi->serial_no, "unknown"); - adi->memory = si->ps.memory_size; - adi->dac_speed = si->ps.max_dac1_clock; - - return B_OK; -} diff --git a/src/add-ons/accelerants/nvidia_gpgpu/GetModeInfo.c b/src/add-ons/accelerants/nvidia_gpgpu/GetModeInfo.c deleted file mode 100644 index 5a454d0c05..0000000000 --- a/src/add-ons/accelerants/nvidia_gpgpu/GetModeInfo.c +++ /dev/null @@ -1,163 +0,0 @@ -/* - Copyright 1999, Be Incorporated. All Rights Reserved. - This file may be used under the terms of the Be Sample Code License. - - Other authors: - Mark Watson - Rudolf Cornelissen 9/2002-10/2005 -*/ - -#define MODULE_BIT 0x02000000 - -#include "acc_std.h" - -/* - Return the current display mode. The only time you might return an - error is if a mode hasn't been set. Or if the system hands you a NULL pointer. -*/ -status_t GET_DISPLAY_MODE(display_mode *current_mode) -{ - /* check for NULL pointer */ - if (current_mode == NULL) return B_ERROR; - - *current_mode = si->dm; - return B_OK; -} - -/* Return the frame buffer configuration information. */ -status_t GET_FRAME_BUFFER_CONFIG(frame_buffer_config *afb) -{ - /* check for NULL pointer */ - if (afb == NULL) return B_ERROR; - - *afb = si->fbc; - return B_OK; -} - -/* Return the maximum and minium pixelclock limits for the specified mode. */ -/* NOTE: - * Due to BeOS constraints output for all heads will be limited to the head with - * the least capabilities. */ -status_t GET_PIXEL_CLOCK_LIMITS(display_mode *dm, uint32 *low, uint32 *high) -{ - uint32 max_pclk = 0; - uint32 min_pclk = 0; - - /* check for NULL pointers */ - if ((dm == NULL) || (low == NULL) || (high == NULL)) return B_ERROR; - - /* specify requested info */ - if (dm->flags & DUALHEAD_BITS) - { - /* dualhead mode */ - /* find min. value */ - switch (si->ps.card_type) - { - default: - *low = ((si->ps.min_video_vco * 1000) / 16); - break; - } - /* find max. value: - * using decondary DAC specs because they could be narrower (twinview) */ - switch (dm->space) - { - case B_CMAP8: - max_pclk = si->ps.max_dac2_clock_8; - break; - case B_RGB15_LITTLE: - case B_RGB16_LITTLE: - max_pclk = si->ps.max_dac2_clock_16; - break; - case B_RGB24_LITTLE: - max_pclk = si->ps.max_dac2_clock_24; - break; - case B_RGB32_LITTLE: - /* specially noted because of RAM speed constraints! */ - max_pclk = si->ps.max_dac2_clock_32dh; - break; - default: - /* use fail-safe value */ - max_pclk = si->ps.max_dac2_clock_32dh; - break; - } - /* return values in kHz */ - *high = max_pclk * 1000; - } - else - { - /* singlehead mode */ - /* find min. value */ - switch (si->ps.card_type) - { - default: - *low = ((si->ps.min_pixel_vco * 1000) / 16); - break; - } - /* find max. value: depends on which head is used as primary head */ - if (!si->ps.crtc2_prim) - { - switch (dm->space) - { - case B_CMAP8: - max_pclk = si->ps.max_dac1_clock_8; - break; - case B_RGB15_LITTLE: - case B_RGB16_LITTLE: - max_pclk = si->ps.max_dac1_clock_16; - break; - case B_RGB24_LITTLE: - max_pclk = si->ps.max_dac1_clock_24; - break; - case B_RGB32_LITTLE: - max_pclk = si->ps.max_dac1_clock_32; - break; - default: - /* use fail-safe value */ - max_pclk = si->ps.max_dac1_clock_32; - break; - } - } - else - { - switch (dm->space) - { - case B_CMAP8: - max_pclk = si->ps.max_dac2_clock_8; - break; - case B_RGB15_LITTLE: - case B_RGB16_LITTLE: - max_pclk = si->ps.max_dac2_clock_16; - break; - case B_RGB24_LITTLE: - max_pclk = si->ps.max_dac2_clock_24; - break; - case B_RGB32_LITTLE: - max_pclk = si->ps.max_dac2_clock_32; - break; - default: - /* use fail-safe value */ - max_pclk = si->ps.max_dac2_clock_32; - break; - } - } - /* return values in kHz */ - *high = max_pclk * 1000; - } - - /* clamp lower limit to 48Hz vertical refresh for now. - * Apparantly the BeOS screenprefs app does limit the upper refreshrate to 90Hz, - * while it does not limit the lower refreshrate. */ - min_pclk = ((uint32)dm->timing.h_total * (uint32)dm->timing.v_total * 48) / 1000; - if (min_pclk > *low) *low = min_pclk; - - return B_OK; -} - -/* Return the semaphore id that will be used to signal a vertical sync occured. */ -sem_id ACCELERANT_RETRACE_SEMAPHORE(void) -{ - if (si->ps.int_assigned) - return si->vblank; - else - return B_ERROR; -} diff --git a/src/add-ons/accelerants/nvidia_gpgpu/GetTimingConstraints.c b/src/add-ons/accelerants/nvidia_gpgpu/GetTimingConstraints.c deleted file mode 100644 index 2b00bbbf87..0000000000 --- a/src/add-ons/accelerants/nvidia_gpgpu/GetTimingConstraints.c +++ /dev/null @@ -1,33 +0,0 @@ -/* - Author: - Rudolf Cornelissen 7/2004 -*/ - -#define MODULE_BIT 0x01000000 - -#include "acc_std.h" - -/* Used to help generate mode lines */ -status_t GET_TIMING_CONSTRAINTS(display_timing_constraints * dtc) -{ - LOG(4, ("GET_TIMING_CONSTRAINTS: returning info\n")); - - /* specs are identical for all nVidia cards */ - dtc->h_res = 8; - dtc->h_sync_min = 8; - dtc->h_sync_max = 248; - /* Note: - * h_blank info is used to determine the max. diff. between h_total and h_display! */ - dtc->h_blank_min = 8; - dtc->h_blank_max = 1016; - - dtc->v_res = 1; - dtc->v_sync_min = 1; - dtc->v_sync_max = 15; - /* Note: - * v_blank info is used to determine the max. diff. between v_total and v_display! */ - dtc->v_blank_min = 1; - dtc->v_blank_max = 255; - - return B_OK; -} diff --git a/src/add-ons/accelerants/nvidia_gpgpu/InitAccelerant.c b/src/add-ons/accelerants/nvidia_gpgpu/InitAccelerant.c deleted file mode 100644 index 4b906a833e..0000000000 --- a/src/add-ons/accelerants/nvidia_gpgpu/InitAccelerant.c +++ /dev/null @@ -1,348 +0,0 @@ -/* - Copyright 1999, Be Incorporated. All Rights Reserved. - This file may be used under the terms of the Be Sample Code License. - - Other authors: - Mark Watson, - Rudolf Cornelissen 10/2002-6/2008. -*/ - -#define MODULE_BIT 0x00800000 - -#include -#include -#include "acc_std.h" - -static status_t init_common(int the_fd); - -/* Initialization code shared between primary and cloned accelerants */ -static status_t init_common(int the_fd) { - status_t result; - nv_get_private_data gpd; - - // LOG not available from here to next LOG: NULL si - - /* memorize the file descriptor */ - fd = the_fd; - /* set the magic number so the driver knows we're for real */ - gpd.magic = NV_PRIVATE_DATA_MAGIC; - /* contact driver and get a pointer to the registers and shared data */ - result = ioctl(fd, NV_GET_PRIVATE_DATA, &gpd, sizeof(gpd)); - if (result != B_OK) goto error0; - - /* clone the shared area for our use */ - shared_info_area = clone_area(DRIVER_PREFIX " shared", (void **)&si, B_ANY_ADDRESS, - B_READ_AREA | B_WRITE_AREA, gpd.shared_info_area); - if (shared_info_area < 0) { - result = shared_info_area; - goto error0; - } - // LOG is now available, si !NULL - LOG(4,("init_common: logmask 0x%08x, memory %dMB, hardcursor %d, usebios %d, switchhead %d\n", - si->settings.logmask, si->settings.memory, si->settings.hardcursor, si->settings.usebios, si->settings.switchhead)); - LOG(4,("init_common: dumprom %d, pgm_panel %d\n", - si->settings.dumprom, si->settings.pgm_panel)); - LOG(4,("init_common: force_sync %d, gpu_clk %dMhz, ram_clk %dMhz, force_ws %d\n", - si->settings.force_sync, si->settings.gpu_clk, si->settings.ram_clk, si->settings.force_ws)); - - /*Check for R4.5.0 and if it is running, use work around*/ - { - if (si->use_clone_bugfix) - { - /*check for R4.5.0 bug and attempt to work around*/ - LOG(2,("InitACC: Found R4.5.0 bug - attempting to work around\n")); - regs = si->clone_bugfix_regs; - } - else - { - /* clone the memory mapped registers for our use - does not work on <4.5.2 (but is better this way)*/ - regs_area = clone_area(DRIVER_PREFIX " regs", (void **)®s, B_ANY_ADDRESS, - B_READ_AREA | B_WRITE_AREA, si->regs_area); - if (regs_area < 0) { - result = regs_area; - goto error1; - } - } - } - - /* all done */ - goto error0; - -error1: - delete_area(shared_info_area); -error0: - return result; -} - -/* Clean up code shared between primary and cloned accelrants */ -static void uninit_common(void) { - /* release the memory mapped registers */ - delete_area(regs_area); - /* a little cheap paranoia */ - regs = 0; - /* release our copy of the shared info from the kernel driver */ - delete_area(shared_info_area); - /* more cheap paranoia */ - si = 0; -} - -/* -Initialize the accelerant. the_fd is the file handle of the device (in -/dev/graphics) that has been opened by the app_server (or some test harness). -We need to determine if the kernel driver and the accelerant are compatible. -If they are, get the accelerant ready to handle other hook functions and -report success or failure. -*/ -status_t INIT_ACCELERANT(int the_fd) -{ - status_t result; - int pointer_reservation; //mem reserved for pointer - - if (0) { - time_t now = time (NULL); - // LOG not available from here to next LOG: NULL si - MSG(("INIT_ACCELERANT: %s", ctime (&now))); - } - - /* note that we're the primary accelerant (accelerantIsClone is global) */ - accelerantIsClone = 0; - - /* do the initialization common to both the primary and the clones */ - result = init_common(the_fd); - - /* bail out if the common initialization failed */ - if (result != B_OK) goto error0; - // LOG now available: !NULL si - - /* ensure that INIT_ACCELERANT is executed just once (copies should be clones) */ - if (si->accelerant_in_use) - { - result = B_NOT_ALLOWED; - goto error1; - } - - /* call the device specific init code */ - result = nv_general_powerup(); - - /* bail out if it failed */ - if (result != B_OK) goto error1; - - /* - Now would be a good time to figure out what video modes your card supports. - We'll place the list of modes in another shared area so all of the copies - of the driver can see them. The primary copy of the accelerant (ie the one - initialized with this routine) will own the "one true copy" of the list. - Everybody else get's a read-only clone. - */ - result = create_mode_list(); - if (result != B_OK) - { - goto error1; - } - - /* - Put the cursor at the start of the frame buffer. - Nvidia cursor is 32x32 16 color? takes up 4096 bytes of RAM. - */ - /* Initialize the rest of the cursor information while we're here */ - si->cursor.width = 16; - si->cursor.height = 16; - si->cursor.hot_x = 0; - si->cursor.hot_y = 0; - si->cursor.x = 0; - si->cursor.y = 0; - si->cursor.dh_right = false; - - /* - Put the frame buffer immediately following the cursor data. We store this - info in a frame_buffer_config structure to make it convienient to return - to the app_server later. - */ - pointer_reservation = 0; - /* Nvidia hardcursor needs 2kB space */ - if (si->settings.hardcursor) pointer_reservation = 2048; - - si->fbc.frame_buffer = (void *)((char *)si->framebuffer+pointer_reservation); - si->fbc.frame_buffer_dma = (void *)((char *)si->framebuffer_pci+pointer_reservation); - - /* count of issued parameters or commands */ - si->engine.last_idle = si->engine.count = 0; - /* no 3D clones are currently loaded */ - si->engine.threeD.clones = 0; - /* tell 3D add-ons that they should reload their rendering states and surfaces */ - si->engine.threeD.reload = 0xffffffff; - INIT_BEN(si->engine.lock); - - /* bail out if something failed */ - if (result != B_OK) goto error1; - - /* initialise various cursor stuff */ - head1_cursor_init(); - if (si->ps.secondary_head) head2_cursor_init(); - - /* ensure cursor state */ - head1_cursor_hide(); - if (si->ps.secondary_head) head2_cursor_hide(); - - /* ensure DPMS state */ - si->dpms_flags = B_DPMS_ON; - - /* make sure a possible 3D add-on will block rendering and re-initialize itself. - * note: update in _this_ order only */ - /* SET_DISPLAY_MODE will reset this flag when it's done. */ - si->engine.threeD.mode_changing = true; - /* every 3D add-on will reset this bit-flag when it's done. */ - si->engine.threeD.newmode = 0xffffffff; - - /* a winner! */ - result = B_OK; - /* ensure that INIT_ACCELERANT won't be executed again (copies should be clones) */ - si->accelerant_in_use = true; - goto error0; - -error1: - /* - Initialization failed after init_common() succeeded, so we need to clean - up before quiting. - */ - uninit_common(); - -error0: - return result; -} - -/* -Return the number of bytes required to hold the information required -to clone the device. -*/ -ssize_t ACCELERANT_CLONE_INFO_SIZE(void) { - /* - Since we're passing the name of the device as the only required - info, return the size of the name buffer - */ - return B_OS_NAME_LENGTH; // apsed, was MAX_NV_DEVICE_NAME_LENGTH; -} - - -/* -Return the info required to clone the device. void *data points to -a buffer at least ACCELERANT_CLONE_INFO_SIZE() bytes in length. -*/ -void GET_ACCELERANT_CLONE_INFO(void *data) { - nv_device_name dn; - status_t result; - - /* call the kernel driver to get the device name */ - dn.magic = NV_PRIVATE_DATA_MAGIC; - /* store the returned info directly into the passed buffer */ - dn.name = (char *)data; - result = ioctl(fd, NV_DEVICE_NAME, &dn, sizeof(dn)); -} - -/* -Initialize a copy of the accelerant as a clone. void *data points to -a copy of the data returned by GET_ACCELERANT_CLONE_INFO(). -*/ -status_t CLONE_ACCELERANT(void *data) -{ - status_t result; - char path[MAXPATHLEN]; - - /* the data is the device name */ - /* Note: the R4 graphics driver kit is in error here (missing trailing '/') */ - strcpy(path, "/dev/"); - strcat(path, (const char *)data); - /* open the device, the permissions aren't important */ - fd = open(path, B_READ_WRITE); - if (fd < 0) - { - /* we can't use LOG because we didn't get the shared_info struct.. */ - char fname[64]; - FILE *myhand = NULL; - - sprintf (fname, "/boot/home/" DRIVER_PREFIX ".accelerant.0.log"); - myhand=fopen(fname,"a+"); - fprintf(myhand, "CLONE_ACCELERANT: couldn't open kerneldriver %s! Aborting.\n", path); - fclose(myhand); - - /* abort with resultcode from open attempt on kerneldriver */ - result = fd; - goto error0; - } - - /* note that we're a clone accelerant */ - accelerantIsClone = 1; - - /* call the shared initialization code */ - result = init_common(fd); - - /* bail out if the common initialization failed */ - if (result != B_OK) goto error1; - - /* ensure that INIT_ACCELERANT is executed first (i.e. primary accelerant exists) */ - if (!(si->accelerant_in_use)) - { - result = B_NOT_ALLOWED; - goto error2; - } - - /* setup CRTC and DAC functions access */ - //fixme: setup_virtualized_heads is a problem for clones: needs to be run - //for each clone if the mode is changed! - if (si->ps.secondary_head) - setup_virtualized_heads(si->crtc_switch_mode); - else - setup_virtualized_heads(si->ps.crtc2_prim); - - /* get shared area for display modes */ - result = my_mode_list_area = clone_area( - DRIVER_PREFIX " cloned display_modes", - (void **)&my_mode_list, - B_ANY_ADDRESS, - B_READ_AREA, - si->mode_area - ); - if (result < B_OK) goto error2; - - /* all done */ - LOG(4,("CLONE_ACCELERANT: cloning was succesfull.\n")); - - result = B_OK; - goto error0; - -error2: - /* free up the areas we cloned */ - uninit_common(); -error1: - /* close the device we opened */ - close(fd); -error0: - return result; -} - -void UNINIT_ACCELERANT(void) -{ - if (accelerantIsClone) - { - LOG(4,("UNINIT_ACCELERANT: shutting down clone accelerant.\n")); - } - else - { - LOG(4,("UNINIT_ACCELERANT: shutting down primary accelerant.\n")); - - /* delete benaphores ONLY if we are the primary accelerant */ - DELETE_BEN(si->engine.lock); - - /* ensure that INIT_ACCELERANT can be executed again */ - si->accelerant_in_use = false; - } - - /* free our mode list area */ - delete_area(my_mode_list_area); - /* paranoia */ - my_mode_list = 0; - /* release our cloned data */ - uninit_common(); - /* close the file handle ONLY if we're the clone */ - if (accelerantIsClone) close(fd); -} diff --git a/src/add-ons/accelerants/nvidia_gpgpu/Jamfile b/src/add-ons/accelerants/nvidia_gpgpu/Jamfile deleted file mode 100644 index dfbb1e6b45..0000000000 --- a/src/add-ons/accelerants/nvidia_gpgpu/Jamfile +++ /dev/null @@ -1,25 +0,0 @@ -SubDir HAIKU_TOP src add-ons accelerants nvidia_gpgpu ; - -SetSubDirSupportedPlatformsBeOSCompatible ; - -UsePrivateHeaders graphics ; -UsePrivateHeaders [ FDirName graphics nvidia_gpgpu ] ; -UseHeaders [ FDirName $(SUBDIR) engine ] ; - -Addon nvidia_gpgpu.accelerant : - Acceleration.c - Cursor.c - EngineManagment.c - GetAccelerantHook.c - GetDeviceInfo.c - GetModeInfo.c - GetTimingConstraints.c - InitAccelerant.c - ProposeDisplayMode.c - SetDisplayMode.c - : libnvidia_gpgpu_engine.a -; - -Depends nvidia_gpgpu.accelerant : nvidia_gpgpu ; - -SubInclude HAIKU_TOP src add-ons accelerants nvidia_gpgpu engine ; diff --git a/src/add-ons/accelerants/nvidia_gpgpu/ProposeDisplayMode.c b/src/add-ons/accelerants/nvidia_gpgpu/ProposeDisplayMode.c deleted file mode 100644 index d6048223da..0000000000 --- a/src/add-ons/accelerants/nvidia_gpgpu/ProposeDisplayMode.c +++ /dev/null @@ -1,546 +0,0 @@ -/* - Copyright 1999, Be Incorporated. All Rights Reserved. - This file may be used under the terms of the Be Sample Code License. - - Other authors for NV driver: - Mark Watson, - Rudolf Cornelissen 9/2002-6/2008 -*/ - -#define MODULE_BIT 0x00400000 - -#include "acc_std.h" - -#define T_POSITIVE_SYNC (B_POSITIVE_HSYNC | B_POSITIVE_VSYNC) -/* mode flags will be setup as status info by PROPOSEMODE! */ -#define MODE_FLAGS 0 -#define MODE_COUNT (sizeof (mode_list) / sizeof (display_mode)) - -/*some monitors only handle a fixed set of modes*/ -#include "valid_mode_list" - -/* Standard VESA modes, - * plus panel specific resolution modes which are internally modified during run-time depending on the requirements of the actual - * panel connected. The modes as listed here, should timing-wise be as compatible with analog (CRT) monitors as can be... */ -static const display_mode mode_list[] = { -/* 4:3 modes; 307.2k pixels */ -{ { 25175, 640, 656, 752, 800, 480, 490, 492, 525, 0}, B_CMAP8, 640, 480, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@60Hz_(640X480X8.Z1) */ -{ { 27500, 640, 672, 768, 864, 480, 488, 494, 530, 0}, B_CMAP8, 640, 480, 0, 0, MODE_FLAGS}, /* 640X480X60Hz */ -{ { 30500, 640, 672, 768, 864, 480, 517, 523, 588, 0}, B_CMAP8, 640, 480, 0, 0, MODE_FLAGS}, /* SVGA_640X480X60HzNI */ -{ { 31500, 640, 664, 704, 832, 480, 489, 492, 520, 0}, B_CMAP8, 640, 480, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@70-72Hz_(640X480X8.Z1) */ -{ { 31500, 640, 656, 720, 840, 480, 481, 484, 500, 0}, B_CMAP8, 640, 480, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@75Hz_(640X480X8.Z1) */ -{ { 36000, 640, 696, 752, 832, 480, 481, 484, 509, 0}, B_CMAP8, 640, 480, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@85Hz_(640X480X8.Z1) */ -/* 4:3 modes; 480k pixels */ -{ { 36000, 800, 824, 896, 1024, 600, 601, 603, 625, 0}, B_CMAP8, 800, 600, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@56Hz_(800X600) from Be, Inc. driver + XFree86 */ -{ { 38100, 800, 832, 960, 1088, 600, 602, 606, 620, 0}, B_CMAP8, 800, 600, 0, 0, MODE_FLAGS}, /* SVGA_800X600X56HzNI */ -{ { 40000, 800, 840, 968, 1056, 600, 601, 605, 628, T_POSITIVE_SYNC}, B_CMAP8, 800, 600, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@60Hz_(800X600X8.Z1) + XFree86 */ -{ { 49500, 800, 816, 896, 1056, 600, 601, 604, 625, T_POSITIVE_SYNC}, B_CMAP8, 800, 600, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@75Hz_(800X600X8.Z1) + XFree86 */ -{ { 50000, 800, 856, 976, 1040, 600, 637, 643, 666, T_POSITIVE_SYNC}, B_CMAP8, 800, 600, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@70-72Hz_(800X600X8.Z1) + XFree86 */ -{ { 56250, 800, 832, 896, 1048, 600, 601, 604, 631, T_POSITIVE_SYNC}, B_CMAP8, 800, 600, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@85Hz_(800X600X8.Z1) + XFree86 */ -/* 4:3 modes; 786.432k pixels */ -{ { 65000, 1024, 1048, 1184, 1344, 768, 771, 777, 806, 0}, B_CMAP8, 1024, 768, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@60Hz_(1024X768X8.Z1) + XFree86 */ -{ { 75000, 1024, 1048, 1184, 1328, 768, 771, 777, 806, 0}, B_CMAP8, 1024, 768, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@70-72Hz_(1024X768X8.Z1) + XFree86 */ -{ { 78750, 1024, 1040, 1136, 1312, 768, 769, 772, 800, T_POSITIVE_SYNC}, B_CMAP8, 1024, 768, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@75Hz_(1024X768X8.Z1) + XFree86 */ -{ { 94500, 1024, 1072, 1168, 1376, 768, 769, 772, 808, T_POSITIVE_SYNC}, B_CMAP8, 1024, 768, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@85Hz_(1024X768X8.Z1) + XFree86 */ -/* 4:3 modes; 995.328k pixels */ -{ { 94200, 1152, 1184, 1280, 1472, 864, 865, 868, 914, T_POSITIVE_SYNC}, B_CMAP8, 1152, 864, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@70Hz_(1152X864X8.Z1) */ -{ { 97800, 1152, 1216, 1344, 1552, 864, 865, 868, 900, T_POSITIVE_SYNC}, B_CMAP8, 1152, 864, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@70Hz_(1152X864X8.Z1) */ -{ { 108000, 1152, 1216, 1344, 1600, 864, 865, 868, 900, T_POSITIVE_SYNC}, B_CMAP8, 1152, 864, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@75Hz_(1152X864X8.Z1) + XFree86 */ -{ { 121500, 1152, 1216, 1344, 1568, 864, 865, 868, 911, T_POSITIVE_SYNC}, B_CMAP8, 1152, 864, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@85Hz_(1152X864X8.Z1) */ -/* 5:4 modes; 1.311M pixels */ -{ { 108000, 1280, 1328, 1440, 1688, 1024, 1025, 1028, 1066, T_POSITIVE_SYNC}, B_CMAP8, 1280, 1024, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@60Hz_(1280X1024) from Be, Inc. driver + XFree86 */ -{ { 135000, 1280, 1296, 1440, 1688, 1024, 1025, 1028, 1066, T_POSITIVE_SYNC}, B_CMAP8, 1280, 1024, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@75Hz_(1280X1024X8.Z1) + XFree86 */ -{ { 157500, 1280, 1344, 1504, 1728, 1024, 1025, 1028, 1072, T_POSITIVE_SYNC}, B_CMAP8, 1280, 1024, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@85Hz_(1280X1024X8.Z1) + XFree86 */ -/* 4:3 panel mode; 1.47M pixels */ -{ { 122600, 1400, 1488, 1640, 1880, 1050, 1051, 1054, 1087, T_POSITIVE_SYNC}, B_CMAP8, 1400, 1050, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@60Hz_(1400X1050) */ -/* 4:3 modes; 1.92M pixels */ -{ { 162000, 1600, 1664, 1856, 2160, 1200, 1201, 1204, 1250, T_POSITIVE_SYNC}, B_CMAP8, 1600, 1200, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@60Hz_(1600X1200X8.Z1) + XFree86 */ -/* identical lines to above one, apart from refreshrate.. */ -{ { 175500, 1600, 1664, 1856, 2160, 1200, 1201, 1204, 1250, T_POSITIVE_SYNC}, B_CMAP8, 1600, 1200, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@65Hz_(1600X1200X8.Z1) + XFree86 */ -{ { 189000, 1600, 1664, 1856, 2160, 1200, 1201, 1204, 1250, T_POSITIVE_SYNC}, B_CMAP8, 1600, 1200, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@70Hz_(1600X1200X8.Z1) + XFree86 */ -{ { 202500, 1600, 1664, 1856, 2160, 1200, 1201, 1204, 1250, T_POSITIVE_SYNC}, B_CMAP8, 1600, 1200, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@75Hz_(1600X1200X8.Z1) + XFree86 */ -{ { 216000, 1600, 1664, 1856, 2160, 1200, 1201, 1204, 1250, T_POSITIVE_SYNC}, B_CMAP8, 1600, 1200, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@80Hz_(1600X1200X8.Z1) */ -{ { 229500, 1600, 1664, 1856, 2160, 1200, 1201, 1204, 1250, T_POSITIVE_SYNC}, B_CMAP8, 1600, 1200, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@85Hz_(1600X1200X8.Z1) + XFree86 */ -/* end identical lines. */ -/* 4:3 modes; 2.408M pixels */ -{ { 204750, 1792, 1920, 2120, 2448, 1344, 1345, 1348, 1394, B_POSITIVE_VSYNC}, B_CMAP8, 1792, 1344, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@60Hz_(1792X1344) from Be, Inc. driver + XFree86 */ -{ { 261000, 1792, 1888, 2104, 2456, 1344, 1345, 1348, 1417, B_POSITIVE_VSYNC}, B_CMAP8, 1792, 1344, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@75Hz_(1792X1344) from Be, Inc. driver + XFree86 */ -/* 4:3 modes; 2.584M pixels */ -{ { 218250, 1856, 1952, 2176, 2528, 1392, 1393, 1396, 1439, B_POSITIVE_VSYNC}, B_CMAP8, 1856, 1392, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@60Hz_(1856X1392) from Be, Inc. driver + XFree86 */ -{ { 288000, 1856, 1984, 2208, 2560, 1392, 1393, 1396, 1500, B_POSITIVE_VSYNC}, B_CMAP8, 1856, 1392, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@75Hz_(1856X1392) from Be, Inc. driver + XFree86 */ -/* 4:3 modes; 2.765M pixels */ -{ { 234000, 1920, 2048, 2256, 2600, 1440, 1441, 1444, 1500, B_POSITIVE_VSYNC}, B_CMAP8, 1920, 1440, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@60Hz_(1920X1440) from Be, Inc. driver + XFree86 */ -{ { 297000, 1920, 2064, 2288, 2640, 1440, 1441, 1444, 1500, B_POSITIVE_VSYNC}, B_CMAP8, 1920, 1440, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@75Hz_(1920X1440) from Be, Inc. driver + XFree86 */ -/* 4:3 modes; 3.146M pixels */ -{ { 266950, 2048, 2200, 2424, 2800, 1536, 1537, 1540, 1589, B_POSITIVE_VSYNC}, B_CMAP8, 2048, 1536, 0, 0, MODE_FLAGS}, /* From XFree86 posting @60Hz + XFree86 */ -/* 16:10 panel mode; 400k pixels */ -{ { 31300, 800, 848, 928, 1008, 500, 501, 504, 518, T_POSITIVE_SYNC}, B_CMAP8, 800, 500, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@60Hz_(800X500) */ -/* 16:10 panel mode; 655.36k pixels */ -{ { 52800, 1024, 1072, 1176, 1328, 640, 641, 644, 663, T_POSITIVE_SYNC}, B_CMAP8, 1024, 640, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@60Hz_(1024X640) */ -/* 16:10 panel-TV mode; 983.04k pixels */ -{ { 80135, 1280, 1344, 1480, 1680, 768, 769, 772, 795, T_POSITIVE_SYNC}, B_CMAP8, 1280, 768, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@60Hz_(1280X768) */ -/* 16:10 panel mode; 1.024M pixels */ -{ { 83500, 1280, 1344, 1480, 1680, 800, 801, 804, 828, T_POSITIVE_SYNC}, B_CMAP8, 1280, 800, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@60Hz_(1280X800) */ -/* 16:10 panel mode; 1.296M pixels */ -{ { 106500, 1440, 1520, 1672, 1904, 900, 901, 904, 932, T_POSITIVE_SYNC}, B_CMAP8, 1440, 900, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@60Hz_(1440X900) */ -/* 16:10 panel mode; 1.764M pixels */ -{ { 147100, 1680, 1784, 1968, 2256, 1050, 1051, 1054, 1087, T_POSITIVE_SYNC}, B_CMAP8, 1680, 1050, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@60Hz_(1680X1050) */ -/* 16:10 panel mode; 2.304M pixels */ -{ { 160000, 1920, 2010, 2060, 2110, 1200, 1202, 1208, 1235, T_POSITIVE_SYNC}, B_CMAP8, 1920, 1200, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@60Hz_(1920X1200) */ -/* 16:9 panel mode; 1280x720 */ -{ { 74520, 1280, 1368, 1424, 1656, 720, 724, 730, 750, T_POSITIVE_SYNC}, B_CMAP8, 1280, 720, 0, 0, MODE_FLAGS}, /* Vesa_Monitor_@60Hz_(1280X720) */ -}; - - -/*! - Check mode is between low and high limits. - Returns: - B_OK - found one - B_BAD_VALUE - mode can be made, but outside limits - B_ERROR - not possible -*/ -/* BOUNDS WARNING: - * BeOS (tested R5.0.3PE) is failing BWindowScreen.SetFrameBuffer() if PROPOSEMODE - * returns B_BAD_VALUE. It's called by the OS with target, low and high set to - * have the same settings for BWindowScreen! - * Which means we should not return B_BAD_VALUE on anything except for deviations on: - * display_mode.virtual_width; - * display_mode.virtual_height; - * display_mode.timing.h_display; - * display_mode.timing.v_display; - */ -/* Note: - * The target mode should be modified to correspond to the mode as it can be made. */ -status_t -PROPOSE_DISPLAY_MODE(display_mode *target, const display_mode *low, const display_mode *high) -{ - status_t status = B_OK; - float pix_clock_found, target_aspect; - uint8 m,n,p, bpp; - status_t result; - uint32 max_vclk, row_bytes, mem_reservation; - bool acc_mode; - double target_refresh = ((double)target->timing.pixel_clock * 1000.0) - / ((double)target->timing.h_total * (double)target->timing.v_total); - bool want_same_width = target->timing.h_display == target->virtual_width; - bool want_same_height = target->timing.v_display == target->virtual_height; - - LOG(1, ("PROPOSEMODE: (ENTER) requested virtual_width %d, virtual_height %d\n", - target->virtual_width, target->virtual_height)); - - /*check valid list: - if (VALID_REQUIRED is set) - { - if (find modes with same size) - { - pick one with nearest pixel clock - } - else - { - pick next largest with nearest pixel clock and modify visible portion as far as possible - } - } - */ - -#ifdef VALID_MODE_REQUIRED - { - int i; - int closest_mode_ptr; - uint32 closest_mode_clock; - - LOG(1, ("PROPOSEMODE: valid mode required!\n")); - - closest_mode_ptr = 0xbad; - closest_mode_clock = 0; - for (i = 0; i < VALID_MODES; i++) { - /*check size is ok and clock is better than any found before*/ - if (target->timing.h_display == valid_mode_list[i].h_display - && target->timing.v_display == valid_mode_list[i].v_display) { - if (abs(valid_mode_list[i].pixel_clock-target->timing.pixel_clock) - < abs(closest_mode_clock-target->timing.pixel_clock)) { - closest_mode_clock = valid_mode_list[i].pixel_clock; - closest_mode_ptr = i; - } - } - } - - if (closest_mode_ptr == 0xbad) { - /* if no modes of correct size */ - LOG(4, ("PROPOSEMODE: no valid mode found, aborted.\n")); - return B_ERROR; - } else { - target->timing = valid_mode_list[closest_mode_ptr]; - /* I require this refresh */ - target_refresh = ((double)target->timing.pixel_clock * 1000.0) - / ((double)target->timing.h_total * (double)target->timing.v_total); - } - } -#endif - - /*find a nearby valid timing from that given*/ - result = head1_validate_timing(&target->timing.h_display, - &target->timing.h_sync_start, &target->timing.h_sync_end, - &target->timing.h_total, &target->timing.v_display, - &target->timing.v_sync_start, &target->timing.v_sync_end, - &target->timing.v_total); - if (result == B_ERROR) { - LOG(4, ("PROPOSEMODE: could not validate timing, aborted.\n")); - return result; - } - - /* check if all connected output devices can display the requested mode's aspect: */ - /* calculate display mode aspect */ - target_aspect = (target->timing.h_display / ((float)target->timing.v_display)); - /* NOTE: - * allow 0.10 difference so 5:4 aspect panels will be able to use 4:3 aspect modes! */ - switch (si->ps.monitors) { - case 0x01: /* digital panel on head 1, nothing on head 2 */ - if (si->ps.panel1_aspect < (target_aspect - 0.10)) { - LOG(4, ("PROPOSEMODE: connected panel1 is not widescreen type, aborted.\n")); - return B_ERROR; - } - break; - case 0x10: /* nothing on head 1, digital panel on head 2 */ - if (si->ps.panel2_aspect < (target_aspect - 0.10)) { - LOG(4, ("PROPOSEMODE: connected panel2 is not widescreen type, aborted.\n")); - return B_ERROR; - } - break; - case 0x11: /* digital panels on both heads */ - if ((si->ps.panel1_aspect < (target_aspect - 0.10)) - || (si->ps.panel2_aspect < (target_aspect - 0.10))) { - LOG(4, ("PROPOSEMODE: not all connected panels are widescreen type, aborted.\n")); - return B_ERROR; - } - break; - default: - /* at least one analog monitor is connected, or nothing detected at all */ - /* (if forcing widescreen type was requested don't block mode) */ - if (target_aspect > 1.34 && !si->settings.force_ws) { - LOG(4, ("PROPOSEMODE: not all output devices can display widescreen modes, aborted.\n")); - return B_ERROR; - } - break; - } - - /* only export widescreen panel-TV modes when an exact resolution match exists, - * to prevent the modelist from becoming too crowded */ - if (target_aspect > 1.61 && !si->settings.force_ws) { - status_t panel_TV_stat = B_ERROR; - - if (si->ps.tmds1_active) { - if (target->timing.h_display == si->ps.p1_timing.h_display - && target->timing.v_display == si->ps.p1_timing.v_display) - panel_TV_stat = B_OK; - } - if (si->ps.tmds2_active) { - if (target->timing.h_display == si->ps.p2_timing.h_display - && target->timing.v_display == si->ps.p2_timing.v_display) - panel_TV_stat = B_OK; - } - if (panel_TV_stat != B_OK) { - LOG(4, ("PROPOSEMODE: WS panel_TV mode requested but no such TV here, aborted.\n")); - return B_ERROR; - } - } - - /* check if panel(s) can display the requested resolution (if connected) */ - if (si->ps.tmds1_active) { - if (target->timing.h_display > si->ps.p1_timing.h_display - || target->timing.v_display > si->ps.p1_timing.v_display) { - LOG(4, ("PROPOSEMODE: panel1 can't display requested resolution, aborted.\n")); - return B_ERROR; - } - } - if (si->ps.tmds2_active) { - if (target->timing.h_display > si->ps.p2_timing.h_display - || target->timing.v_display > si->ps.p2_timing.v_display) { - LOG(4, ("PROPOSEMODE: panel2 can't display requested resolution, aborted.\n")); - return B_ERROR; - } - } - - /* validate display vs. virtual */ - if (target->timing.h_display > target->virtual_width || want_same_width) - target->virtual_width = target->timing.h_display; - if (target->timing.v_display > target->virtual_height || want_same_height) - target->virtual_height = target->timing.v_display; - - /* nail virtual size and 'subsequently' calculate rowbytes */ - result = nv_general_validate_pic_size(target, &row_bytes, &acc_mode); - if (result == B_ERROR) { - LOG(4, ("PROPOSEMODE: could not validate virtual picture size, aborted.\n")); - return result; - } - - /* check if virtual_width is still within the requested limits */ - if (target->virtual_width < low->virtual_width - || target->virtual_width > high->virtual_width) { - status = B_BAD_VALUE; - LOG(4, ("PROPOSEMODE: WARNING: virtual_width deviates too much\n")); - } - - /* check if timing found is within the requested horizontal limits */ - if (target->timing.h_display < low->timing.h_display - || target->timing.h_display > high->timing.h_display - || target->timing.h_sync_start < low->timing.h_sync_start - || target->timing.h_sync_start > high->timing.h_sync_start - || target->timing.h_sync_end < low->timing.h_sync_end - || target->timing.h_sync_end > high->timing.h_sync_end - || target->timing.h_total < low->timing.h_total - || target->timing.h_total > high->timing.h_total) { - /* BWindowScreen workaround: we accept everything except h_display deviations */ - if (target->timing.h_display < low->timing.h_display - || target->timing.h_display > high->timing.h_display) - status = B_BAD_VALUE; - - LOG(4, ("PROPOSEMODE: WARNING: horizontal timing deviates too much\n")); - } - - /* check if timing found is within the requested vertical limits */ - if (target->timing.v_display < low->timing.v_display - || target->timing.v_display > high->timing.v_display - || target->timing.v_sync_start < low->timing.v_sync_start - || target->timing.v_sync_start > high->timing.v_sync_start - || target->timing.v_sync_end < low->timing.v_sync_end - || target->timing.v_sync_end > high->timing.v_sync_end - || target->timing.v_total < low->timing.v_total - || target->timing.v_total > high->timing.v_total) { - /* BWindowScreen workaround: we accept everything except v_display deviations */ - if (target->timing.v_display < low->timing.v_display - || target->timing.v_display > high->timing.v_display) - status = B_BAD_VALUE; - - LOG(4, ("PROPOSEMODE: WARNING: vertical timing deviates too much\n")); - } - - /* adjust pixelclock for possible timing modifications done above */ - target->timing.pixel_clock = target_refresh * ((double)target->timing.h_total) - * ((double)target->timing.v_total) / 1000.0; - - /* Now find the nearest valid pixelclock we actually can setup for the target mode, - * this also makes sure we don't generate more pixel bandwidth than the device can handle */ - /* calculate settings, but do not actually test anything (that costs too much time!) */ - result = head1_pix_pll_find(*target, &pix_clock_found, &m, &n, &p, 0); - /* update the target mode */ - target->timing.pixel_clock = pix_clock_found * 1000; - - /* note if we fell outside the limits */ - if (target->timing.pixel_clock < low->timing.pixel_clock - || target->timing.pixel_clock > high->timing.pixel_clock) { - /* BWindowScreen workaround: we accept deviations <= 1Mhz */ - if (target->timing.pixel_clock < low->timing.pixel_clock - 1000 - || target->timing.pixel_clock > high->timing.pixel_clock + 1000) - status = B_BAD_VALUE; - - LOG(4, ("PROPOSEMODE: WARNING: pixelclock deviates too much\n")); - } - - mem_reservation = 0; - /* checkout space needed for hardcursor (if any) */ - if (si->settings.hardcursor) - mem_reservation = 2048; - - /* Reserve extra space as a workaround for certain bugs (see DriverInterface.h - * for an explanation). */ - mem_reservation += NV40_PLUS_OFFSET; - - /* memory requirement for frame buffer */ - if (row_bytes * target->virtual_height > si->ps.memory_size - mem_reservation) { - target->virtual_height = (si->ps.memory_size - mem_reservation) / row_bytes; - } - if (target->virtual_height < target->timing.v_display) { - LOG(4,("PROPOSEMODE: not enough memory for current mode, aborted.\n")); - return B_ERROR; - } - - LOG(4,("PROPOSEMODE: validated virtual_width %d, virtual_height %d pixels\n", - target->virtual_width, target->virtual_height)); - - if (target->virtual_height < low->virtual_height - || target->virtual_height > high->virtual_height) { - status = B_BAD_VALUE; - LOG(4, ("PROPOSEMODE: WARNING: virtual_height deviates too much\n")); - } - - /* setup status flags */ - LOG(1, ("PROPOSEMODE: initial modeflags: $%08x\n", target->flags)); - /* preset to singlehead card without TVout, no overlay support and no hardcursor. - * also advice system that app_server and acc engine may touch the framebuffer - * simultaneously (fixed). */ - target->flags &= - ~(DUALHEAD_CAPABLE | TV_CAPABLE | B_SUPPORTS_OVERLAYS | B_HARDWARE_CURSOR | B_IO_FB_NA); - /* we always allow parallel access (fixed), the DAC is always in 'enhanced' - * mode (fixed), and all modes support DPMS (fixed); - * We support scrolling and panning in every mode, so we 'send a signal' to - * BWindowScreen.CanControlFrameBuffer() by setting B_SCROLL. */ - /* BTW: B_PARALLEL_ACCESS in combination with a hardcursor enables - * BDirectWindow windowed modes. */ - target->flags |= (B_PARALLEL_ACCESS | B_8_BIT_DAC | B_DPMS | B_SCROLL); - - /* determine the 'would be' max. pixelclock for the second DAC for the current videomode if dualhead were activated */ - switch (target->space) { - case B_CMAP8: - max_vclk = si->ps.max_dac2_clock_8; - bpp = 1; - break; - case B_RGB15_LITTLE: - case B_RGB16_LITTLE: - max_vclk = si->ps.max_dac2_clock_16; - bpp = 2; - break; - case B_RGB24_LITTLE: - max_vclk = si->ps.max_dac2_clock_24; - bpp = 3; - break; - case B_RGB32_LITTLE: - max_vclk = si->ps.max_dac2_clock_32dh; - bpp = 4; - break; - default: - /* use fail-safe value */ - max_vclk = si->ps.max_dac2_clock_32dh; - bpp = 4; - break; - } - - /* set DUALHEAD_CAPABLE if suitable */ - //fixme: update for independant secondary head use! (reserve fixed memory then) - if (si->ps.secondary_head && target->timing.pixel_clock <= (max_vclk * 1000)) { - switch (target->flags & DUALHEAD_BITS) { - case DUALHEAD_ON: - case DUALHEAD_SWITCH: - if (si->ps.memory_size - mem_reservation - >= row_bytes * target->virtual_height - && (uint16)(row_bytes / bpp) >= target->timing.h_display * 2) - target->flags |= DUALHEAD_CAPABLE; - break; - case DUALHEAD_CLONE: - if (si->ps.memory_size - mem_reservation - >= row_bytes * target->virtual_height) - target->flags |= DUALHEAD_CAPABLE; - break; - case DUALHEAD_OFF: - if (si->ps.memory_size - mem_reservation - >= row_bytes * target->virtual_height * 2) - target->flags |= DUALHEAD_CAPABLE; - break; - } - } - - /* if not dualhead capable card clear dualhead flags */ - if (!(target->flags & DUALHEAD_CAPABLE)) - target->flags &= ~DUALHEAD_BITS; - - /* if not TVout capable card clear TVout flags */ - if (!(target->flags & TV_CAPABLE)) - target->flags &= ~TV_BITS; - - /* set HARDWARE_CURSOR mode if suitable */ - if (si->settings.hardcursor) - target->flags |= B_HARDWARE_CURSOR; - - /* set SUPPORTS_OVERLAYS if suitable */ - if (si->ps.card_type <= NV40 || si->ps.card_type == NV45) - target->flags |= B_SUPPORTS_OVERLAYS; - - LOG(1, ("PROPOSEMODE: validated modeflags: $%08x\n", target->flags)); - - /* overrule timing command flags to be (fixed) blank_pedestal = 0.0IRE, - * progressive scan (fixed), and sync_on_green not avaible. */ - target->timing.flags &= ~(B_BLANK_PEDESTAL | B_TIMING_INTERLACED | B_SYNC_ON_GREEN); - /* The HSYNC and VSYNC command flags are actually executed by the driver. */ - - if (status == B_OK) - LOG(4, ("PROPOSEMODE: completed successfully.\n")); - else - LOG(4, ("PROPOSEMODE: mode can be made, but outside given limits.\n")); - return status; -} - - -/*! - Return the number of modes this device will return from GET_MODE_LIST(). - This is precalculated in create_mode_list (called from InitAccelerant stuff) -*/ -uint32 -ACCELERANT_MODE_COUNT(void) -{ - LOG(1, ("ACCELERANT_MODE_COUNT: the modelist contains %d modes\n",si->mode_count)); - return si->mode_count; -} - - -/*! Copy the list of guaranteed supported video modes to the location provided. -*/ -status_t -GET_MODE_LIST(display_mode *dm) -{ - LOG(1, ("GET_MODE_LIST: exporting the modelist created before.\n")); - - memcpy(dm, my_mode_list, si->mode_count * sizeof(display_mode)); - return B_OK; -} - - -/*! Create a list of display_modes to pass back to the caller. -*/ -status_t -create_mode_list(void) -{ - size_t max_size; - uint32 i, j, pix_clk_range; - const display_mode *src; - display_mode *dst, low, high; - color_space spaces[4] = {B_RGB32_LITTLE, B_RGB16_LITTLE, B_RGB15_LITTLE, B_CMAP8}; - - /* figure out how big the list could be, and adjust up to nearest multiple of B_PAGE_SIZE */ - max_size = (((MODE_COUNT * 4) * sizeof(display_mode)) + (B_PAGE_SIZE-1)) & ~(B_PAGE_SIZE-1); - - /* create an area to hold the info */ - si->mode_area = my_mode_list_area = create_area("NV accelerant mode info", - (void **)&my_mode_list, B_ANY_ADDRESS, max_size, B_NO_LOCK, - B_READ_AREA | B_WRITE_AREA); - if (my_mode_list_area < B_OK) - return my_mode_list_area; - - /* walk through our predefined list and see which modes fit this device */ - src = mode_list; - dst = my_mode_list; - si->mode_count = 0; - for (i = 0; i < MODE_COUNT; i++) { - /* set ranges for acceptable values */ - low = high = *src; - /* range is 6.25% of default clock: arbitrarily picked */ - pix_clk_range = low.timing.pixel_clock >> 5; - low.timing.pixel_clock -= pix_clk_range; - high.timing.pixel_clock += pix_clk_range; - /* 'some cards need wider virtual widths for certain modes': - * Not true. They might need a wider pitch, but this is _not_ reflected in - * virtual_width, but in fbc.bytes_per_row. */ - //So disable next line: - //high.virtual_width = 4096; - /* do it once for each depth we want to support */ - for (j = 0; j < (sizeof(spaces) / sizeof(color_space)); j++) { - /* set target values */ - *dst = *src; - /* poke the specific space */ - dst->space = low.space = high.space = spaces[j]; - /* ask for a compatible mode */ - /* We have to check for B_OK, because otherwise the pix_clk_range - * won't be taken into account!! */ - //So don't do this: - //if (PROPOSE_DISPLAY_MODE(dst, &low, &high) != B_ERROR) { - //Instead, do this: - if (PROPOSE_DISPLAY_MODE(dst, &low, &high) == B_OK) { - /* count it, and move on to next mode */ - dst++; - si->mode_count++; - } - } - /* advance to next mode */ - src++; - } - - return B_OK; -} diff --git a/src/add-ons/accelerants/nvidia_gpgpu/SetDisplayMode.c b/src/add-ons/accelerants/nvidia_gpgpu/SetDisplayMode.c deleted file mode 100644 index e5c5830870..0000000000 --- a/src/add-ons/accelerants/nvidia_gpgpu/SetDisplayMode.c +++ /dev/null @@ -1,490 +0,0 @@ - -/* - Copyright 1999, Be Incorporated. All Rights Reserved. - This file may be used under the terms of the Be Sample Code License. - - Other authors: - Mark Watson, - Apsed, - Rudolf Cornelissen 11/2002-6/2008 -*/ - -#define MODULE_BIT 0x00200000 - -#include "acc_std.h" - -/* First validate the mode, then call lots of bit banging stuff to set the mode(s)! */ -status_t SET_DISPLAY_MODE(display_mode *mode_to_set) -{ - /* BOUNDS WARNING: - * It's impossible to deviate whatever small amount in a display_mode if the lower - * and upper limits are the same! - * Besides: - * BeOS (tested R5.0.3PE) is failing BWindowScreen::SetFrameBuffer() if PROPOSEMODE - * returns B_BAD_VALUE! - * Which means PROPOSEMODE should not return that on anything except on - * deviations for: - * display_mode.virtual_width; - * display_mode.virtual_height; - * display_mode.timing.h_display; - * display_mode.timing.v_display; - * So: - * We don't use bounds here by making sure bounds and target are the same struct! - * (See the call to PROPOSE_DISPLAY_MODE below) */ - display_mode /*bounds,*/ target; - - uint8 colour_depth1 = 32; - uint32 startadd,startadd_right; -// bool crt1, crt2, cross; - - /* Adjust mode to valid one and fail if invalid */ - target /*= bounds*/ = *mode_to_set; - /* show the mode bits */ - LOG(1, ("SETMODE: (ENTER) initial modeflags: $%08x\n", target.flags)); - LOG(1, ("SETMODE: requested target pixelclock %dkHz\n", target.timing.pixel_clock)); - LOG(1, ("SETMODE: requested virtual_width %d, virtual_height %d\n", - target.virtual_width, target.virtual_height)); - - /* See BOUNDS WARNING above... */ - if (PROPOSE_DISPLAY_MODE(&target, &target, &target) == B_ERROR) return B_ERROR; - - /* make sure a possible 3D add-on will block rendering and re-initialize itself. - * note: update in _this_ order only */ - /* SET_DISPLAY_MODE will reset this flag when it's done. */ - si->engine.threeD.mode_changing = true; - /* every 3D add-on will reset this bit-flag when it's done. */ - si->engine.threeD.newmode = 0xffffffff; - /* every 3D clone needs to reclaim a slot. - * note: this also cleans up reserved channels for killed 3D clones.. */ - si->engine.threeD.clones = 0x00000000; - - /* disable interrupts using the kernel driver */ -// head1_interrupt_enable(false); -// if (si->ps.secondary_head) head2_interrupt_enable(false); - - /* turn off screen(s) */ -// head1_dpms(false, false, false, true); -// if (si->ps.secondary_head) head2_dpms(false, false, false, true); - - /*where in framebuffer the screen is (should this be dependant on previous MOVEDISPLAY?)*/ - startadd = (uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer; - - /* calculate and set new mode bytes_per_row */ - nv_general_validate_pic_size (&target, &si->fbc.bytes_per_row, &si->acc_mode); - - /*Perform the very long mode switch!*/ - if (target.flags & DUALHEAD_BITS) /*if some dualhead mode*/ - { - uint8 colour_depth2 = colour_depth1; - - /* init display mode for secondary head */ - display_mode target2 = target; - - LOG(1,("SETMODE: setting DUALHEAD mode\n")); - - /* detect which connectors have a CRT connected */ - //fixme: 'hot-plugging' for analog monitors removed: remove code as well; - //or make it work with digital panels connected as well. -// crt1 = nv_dac_crt_connected(); -// crt2 = nv_dac2_crt_connected(); - /* connect outputs 'straight-through' */ -// if (crt1) -// { - /* connector1 is used as primary output */ -// cross = false; -// } -// else -// { -// if (crt2) - /* connector2 is used as primary output */ -// cross = true; -// else - /* no CRT detected: assume connector1 is used as primary output */ -// cross = false; -// } - /* set output connectors assignment if possible */ -// if ((target.flags & DUALHEAD_BITS) == DUALHEAD_SWITCH) - /* invert output assignment in switch mode */ -// nv_general_head_select(true); -// else -// nv_general_head_select(false); - - /* set the pixel clock PLL(s) */ - LOG(8,("SETMODE: target clock %dkHz\n",target.timing.pixel_clock)); -// if (head1_set_pix_pll(target) == B_ERROR) -// LOG(8,("SETMODE: error setting pixel clock (internal DAC)\n")); - - LOG(8,("SETMODE: target2 clock %dkHz\n",target2.timing.pixel_clock)); -// if (head2_set_pix_pll(target2) == B_ERROR) -// LOG(8,("SETMODE: error setting pixel clock (DAC2)\n")); - - /*set the colour depth for CRTC1 and the DAC */ - switch(target.space) - { - case B_CMAP8: - colour_depth1 = 8; -// head1_mode(BPP8, 1.0); -// head1_depth(BPP8); - break; - case B_RGB15_LITTLE: - colour_depth1 = 16; -// head1_mode(BPP15, 1.0); -// head1_depth(BPP15); - break; - case B_RGB16_LITTLE: - colour_depth1 = 16; -// head1_mode(BPP16, 1.0); -// head1_depth(BPP16); - break; - case B_RGB32_LITTLE: - colour_depth1 = 32; -// head1_mode(BPP32, 1.0); -// head1_depth(BPP32); - break; - } - /*set the colour depth for CRTC2 and DAC2 */ - switch(target2.space) - { - case B_CMAP8: - colour_depth2 = 8; -// head2_mode(BPP8, 1.0); -// head2_depth(BPP8); - break; - case B_RGB15_LITTLE: - colour_depth2 = 16; -// head2_mode(BPP15, 1.0); -// head2_depth(BPP15); - break; - case B_RGB16_LITTLE: - colour_depth2 = 16; -// head2_mode(BPP16, 1.0); -// head2_depth(BPP16); - break; - case B_RGB32_LITTLE: - colour_depth2 = 32; -// head2_mode(BPP32, 1.0); -// head2_depth(BPP32); - break; - } - - /*set the display(s) pitches*/ -// head1_set_display_pitch (); - //fixme: seperate for real dualhead modes: - //we need a secondary si->fbc! -// head2_set_display_pitch (); - - /*work out where the "right" screen starts*/ - startadd_right = startadd + (target.timing.h_display * (colour_depth1 >> 3)); - - /* Tell card what memory to display */ - switch (target.flags & DUALHEAD_BITS) - { - case DUALHEAD_ON: - case DUALHEAD_SWITCH: -// head1_set_display_start(startadd,colour_depth1); -// head2_set_display_start(startadd_right,colour_depth2); - break; - case DUALHEAD_CLONE: -// head1_set_display_start(startadd,colour_depth1); -// head2_set_display_start(startadd,colour_depth2); - break; - } - - /* set the timing */ -// head1_set_timing(target); -// head2_set_timing(target2); - } - else /* single head mode */ - { - int colour_mode = BPP32; - - /* connect output */ - if (si->ps.secondary_head) - { - /* detect which connectors have a CRT connected */ - //fixme: 'hot-plugging' for analog monitors removed: remove code as well; - //or make it work with digital panels connected as well. -// crt1 = nv_dac_crt_connected(); -// crt2 = nv_dac2_crt_connected(); - /* connect outputs 'straight-through' */ -// if (crt1) -// { - /* connector1 is used as primary output */ -// cross = false; -// } -// else -// { -// if (crt2) - /* connector2 is used as primary output */ -// cross = true; -// else - /* no CRT detected: assume connector1 is used as primary output */ -// cross = false; -// } - /* set output connectors assignment if possible */ - nv_general_head_select(false); - } - - switch(target.space) - { - case B_CMAP8: colour_depth1 = 8; colour_mode = BPP8; break; - case B_RGB15_LITTLE: colour_depth1 = 16; colour_mode = BPP15; break; - case B_RGB16_LITTLE: colour_depth1 = 16; colour_mode = BPP16; break; - case B_RGB32_LITTLE: colour_depth1 = 32; colour_mode = BPP32; break; - default: - LOG(8,("SETMODE: Invalid singlehead colour depth 0x%08x\n", target.space)); - return B_ERROR; - } - - /* set the pixel clock PLL */ -// if (head1_set_pix_pll(target) == B_ERROR) -// LOG(8,("CRTC: error setting pixel clock (internal DAC)\n")); - - /* set the colour depth for CRTC1 and the DAC */ - /* first set the colordepth */ -// head1_depth(colour_mode); - /* then(!) program the PAL (<8bit colordepth does not support 8bit PAL) */ -// head1_mode(colour_mode,1.0); - - /* set the display pitch */ -// head1_set_display_pitch(); - - /* tell the card what memory to display */ -// head1_set_display_start(startadd,colour_depth1); - - /* set the timing */ -// head1_set_timing(target); - - //fixme: shut-off the videoPLL if it exists... - } - - /* update driver's mode store */ - si->dm = target; - - /* update FIFO data fetching according to mode */ -// nv_crtc_update_fifo(); -// if (si->ps.secondary_head) nv_crtc2_update_fifo(); - - /* set up acceleration for this mode */ - /* note: - * Maybe later we can forget about non-DMA mode (depends on 3D acceleration - * attempts). */ -//no acc support for G8x yet! -if (si->ps.card_arch < NV50A) -{ - nv_acc_init_dma(); -} - /* set up overlay unit for this mode */ -// nv_bes_init(); - - /* note freemem range */ - /* first free adress follows hardcursor and workspace */ - si->engine.threeD.mem_low = si->fbc.bytes_per_row * si->dm.virtual_height; - if (si->settings.hardcursor) si->engine.threeD.mem_low += 2048; - /* last free adress is end-of-ram minus max space needed for overlay bitmaps */ - //fixme possible: - //if overlay buffers are allocated subtract buffersize from mem_high; - //only allocate overlay buffers if 3D is not in use. (block overlay during 3D) - si->engine.threeD.mem_high = si->ps.memory_size - 1; - /* Keep some extra distance as a workaround for certain bugs (see - * DriverInterface.h for an explanation). */ - si->engine.threeD.mem_high -= NV40_PLUS_OFFSET; - - /* restore screen(s) output state(s) */ -// SET_DPMS_MODE(si->dpms_flags); - - /* enable interrupts using the kernel driver */ - //fixme: - //add head2 once we use one driver instance 'per head' (instead of 'per card') -// head1_interrupt_enable(true); - - /* make sure a possible 3D add-on will re-initialize itself by signalling ready */ - si->engine.threeD.mode_changing = false; - - /* optimize memory-access if needed */ -// head1_mem_priority(colour_depth1); - - /* Tune RAM CAS-latency if needed. Must be done *here*! */ -// nv_set_cas_latency(); - - LOG(1,("SETMODE: booted since %f mS\n", system_time()/1000.0)); - - return B_OK; -} - -/* - Set which pixel of the virtual frame buffer will show up in the - top left corner of the display device. Used for page-flipping - games and virtual desktops. -*/ -status_t MOVE_DISPLAY(uint16 h_display_start, uint16 v_display_start) { - uint8 colour_depth; - uint32 startadd,startadd_right; - - LOG(4,("MOVE_DISPLAY: h %d, v %d\n", h_display_start, v_display_start)); - - /* nVidia cards support pixelprecise panning on both heads in all modes: - * No stepping granularity needed! */ - - /* determine bits used for the colordepth */ - switch(si->dm.space) - { - case B_CMAP8: - colour_depth=8; - break; - case B_RGB15_LITTLE: - case B_RGB16_LITTLE: - colour_depth=16; - break; - case B_RGB24_LITTLE: - colour_depth=24; - break; - case B_RGB32_LITTLE: - colour_depth=32; - break; - default: - return B_ERROR; - } - - /* do not run past end of display */ - switch (si->dm.flags & DUALHEAD_BITS) - { - case DUALHEAD_ON: - case DUALHEAD_SWITCH: - if (((si->dm.timing.h_display * 2) + h_display_start) > si->dm.virtual_width) - return B_ERROR; - break; - default: - if ((si->dm.timing.h_display + h_display_start) > si->dm.virtual_width) - return B_ERROR; - break; - } - if ((si->dm.timing.v_display + v_display_start) > si->dm.virtual_height) - return B_ERROR; - - /* everybody remember where we parked... */ - si->dm.h_display_start = h_display_start; - si->dm.v_display_start = v_display_start; - - /* actually set the registers */ - //fixme: seperate both heads: we need a secondary si->fbc! - startadd = v_display_start * si->fbc.bytes_per_row; - startadd += h_display_start * (colour_depth >> 3); - startadd += (uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer; - startadd_right = startadd + si->dm.timing.h_display * (colour_depth >> 3); - - /* disable interrupts using the kernel driver */ - head1_interrupt_enable(false); - if (si->ps.secondary_head) head2_interrupt_enable(false); - - switch (si->dm.flags & DUALHEAD_BITS) - { - case DUALHEAD_ON: - case DUALHEAD_SWITCH: - head1_set_display_start(startadd,colour_depth); - head2_set_display_start(startadd_right,colour_depth); - break; - case DUALHEAD_OFF: - head1_set_display_start(startadd,colour_depth); - break; - case DUALHEAD_CLONE: - head1_set_display_start(startadd,colour_depth); - head2_set_display_start(startadd,colour_depth); - break; - } - - //fixme: - //add head2 once we use one driver instance 'per head' (instead of 'per card') - head1_interrupt_enable(true); - - return B_OK; -} - -/* Set the indexed color palette */ -void SET_INDEXED_COLORS(uint count, uint8 first, uint8 *color_data, uint32 flags) { - int i; - uint8 *r,*g,*b; - - /* Protect gamma correction when not in CMAP8 */ - if (si->dm.space != B_CMAP8) return; - - r=si->color_data; - g=r+256; - b=g+256; - - i=first; - while (count--) - { - r[i]=*color_data++; - g[i]=*color_data++; - b[i]=*color_data++; - i++; - } - head1_palette(r,g,b); - if (si->dm.flags & DUALHEAD_BITS) head2_palette(r,g,b); -} - -/* Put the display into one of the Display Power Management modes. */ -status_t SET_DPMS_MODE(uint32 dpms_flags) -{ - bool display, h1h, h1v, h2h, h2v, do_p1, do_p2; - - /* disable interrupts using the kernel driver */ - head1_interrupt_enable(false); - if (si->ps.secondary_head) head2_interrupt_enable(false); - - LOG(4,("SET_DPMS_MODE: $%08x\n", dpms_flags)); - - /* note current DPMS state for our reference */ - si->dpms_flags = dpms_flags; - - /* preset: DPMS for panels should be executed */ - do_p1 = do_p2 = true; - - /* determine signals to send to head(s) */ - display = h1h = h1v = h2h = h2v = true; - switch(dpms_flags) - { - case B_DPMS_ON: /* H: on, V: on, display on */ - break; - case B_DPMS_STAND_BY: - display = h1h = h2h = false; - break; - case B_DPMS_SUSPEND: - display = h1v = h2v = false; - break; - case B_DPMS_OFF: /* H: off, V: off, display off */ - display = h1h = h1v = h2h = h2v = false; - break; - default: - LOG(8,("SET: Invalid DPMS settings $%08x\n", dpms_flags)); - //fixme: - //add head2 once we use one driver instance 'per head' (instead of 'per card') - head1_interrupt_enable(true); - - return B_ERROR; - } - - /* issue actual DPMS commands as far as applicable */ - head1_dpms(display, h1h, h1v, do_p1); - if ((si->ps.secondary_head) && (si->dm.flags & DUALHEAD_BITS)) - head2_dpms(display, h2h, h2v, do_p2); - - //fixme: - //add head2 once we use one driver instance 'per head' (instead of 'per card') - head1_interrupt_enable(true); - - return B_OK; -} - -/* Report device DPMS capabilities */ -uint32 DPMS_CAPABILITIES(void) -{ - return (B_DPMS_ON | B_DPMS_STAND_BY | B_DPMS_SUSPEND | B_DPMS_OFF); -} - -/* Return the current DPMS mode */ -uint32 DPMS_MODE(void) -{ - return si->dpms_flags; -} diff --git a/src/add-ons/accelerants/nvidia_gpgpu/acc_std.h b/src/add-ons/accelerants/nvidia_gpgpu/acc_std.h deleted file mode 100644 index 560ab04a67..0000000000 --- a/src/add-ons/accelerants/nvidia_gpgpu/acc_std.h +++ /dev/null @@ -1,17 +0,0 @@ -/* - Copyright 1999, Be Incorporated. All Rights Reserved. - This file may be used under the terms of the Be Sample Code License. -*/ - -#if !defined(GLOBALDATA_H) -#define GLOBALDATA_H - -#include -#include -#include "DriverInterface.h" -#include "nv_globals.h" -//apsed #include "nv_extern.h" -#include "nv_proto.h" -#include "be_driver_proto.h" - -#endif diff --git a/src/add-ons/accelerants/nvidia_gpgpu/be_driver_proto.h b/src/add-ons/accelerants/nvidia_gpgpu/be_driver_proto.h deleted file mode 100644 index b1b6045f61..0000000000 --- a/src/add-ons/accelerants/nvidia_gpgpu/be_driver_proto.h +++ /dev/null @@ -1,72 +0,0 @@ -/* - Copyright 1999, Be Incorporated. All Rights Reserved. - This file may be used under the terms of the Be Sample Code License. - - Modified by Rudolf Cornelissen 2/2005. -*/ - -#if !defined(GENERIC_H) -#define GENERIC_H - -#include -#include "video_overlay.h" - -#define DEBUG 1 - -status_t INIT_ACCELERANT(int fd); -ssize_t ACCELERANT_CLONE_INFO_SIZE(void); -void GET_ACCELERANT_CLONE_INFO(void *data); -status_t CLONE_ACCELERANT(void *data); -void UNINIT_ACCELERANT(void); -status_t GET_ACCELERANT_DEVICE_INFO(accelerant_device_info *adi); -sem_id ACCELERANT_RETRACE_SEMAPHORE(void); - -uint32 ACCELERANT_MODE_COUNT(void); -status_t GET_MODE_LIST(display_mode *dm); -status_t PROPOSE_DISPLAY_MODE(display_mode *target, const display_mode *low, const display_mode *high); -status_t SET_DISPLAY_MODE(display_mode *mode_to_set); -status_t GET_DISPLAY_MODE(display_mode *current_mode); -status_t GET_FRAME_BUFFER_CONFIG(frame_buffer_config *a_frame_buffer); -status_t GET_PIXEL_CLOCK_LIMITS(display_mode *dm, uint32 *low, uint32 *high); -status_t MOVE_DISPLAY(uint16 h_display_start, uint16 v_display_start); -status_t GET_TIMING_CONSTRAINTS(display_timing_constraints *dtc); -void SET_INDEXED_COLORS(uint count, uint8 first, uint8 *color_data, uint32 flags); - -uint32 DPMS_CAPABILITIES(void); -uint32 DPMS_MODE(void); -status_t SET_DPMS_MODE(uint32 dpms_flags); - -status_t SET_CURSOR_SHAPE(uint16 width, uint16 height, uint16 hot_x, uint16 hot_y, uint8 *andMask, uint8 *xorMask); -void MOVE_CURSOR(uint16 x, uint16 y); -void SHOW_CURSOR(bool is_visible); - -uint32 ACCELERANT_ENGINE_COUNT(void); -status_t ACQUIRE_ENGINE_PIO(uint32 capabilities, uint32 max_wait, sync_token *st, engine_token **et); -status_t ACQUIRE_ENGINE_DMA(uint32 capabilities, uint32 max_wait, sync_token *st, engine_token **et); -status_t RELEASE_ENGINE(engine_token *et, sync_token *st); -void WAIT_ENGINE_IDLE(void); -status_t GET_SYNC_TOKEN(engine_token *et, sync_token *st); -status_t SYNC_TO_TOKEN(sync_token *st); - -/* PIO acceleration */ -void SCREEN_TO_SCREEN_BLIT_PIO(engine_token *et, blit_params *list, uint32 count); -void SCREEN_TO_SCREEN_TRANSPARENT_BLIT_PIO(engine_token *et, uint32 transparent_colour, blit_params *list, uint32 count); -void SCREEN_TO_SCREEN_SCALED_FILTERED_BLIT_PIO(engine_token *et, scaled_blit_params *list, uint32 count); -void FILL_RECTANGLE_PIO(engine_token *et, uint32 color, fill_rect_params *list, uint32 count); -void INVERT_RECTANGLE_PIO(engine_token *et, fill_rect_params *list, uint32 count); -void FILL_SPAN_PIO(engine_token *et, uint32 color, uint16 *list, uint32 count); - -/* video_overlay */ -uint32 OVERLAY_COUNT(const display_mode *dm); -const uint32 *OVERLAY_SUPPORTED_SPACES(const display_mode *dm); -uint32 OVERLAY_SUPPORTED_FEATURES(uint32 a_color_space); -const overlay_buffer *ALLOCATE_OVERLAY_BUFFER(color_space cs, uint16 width, uint16 height); -status_t RELEASE_OVERLAY_BUFFER(const overlay_buffer *ob); -status_t GET_OVERLAY_CONSTRAINTS(const display_mode *dm, const overlay_buffer *ob, overlay_constraints *oc); -overlay_token ALLOCATE_OVERLAY(void); -status_t RELEASE_OVERLAY(overlay_token ot); -status_t CONFIGURE_OVERLAY(overlay_token ot, const overlay_buffer *ob, const overlay_window *ow, const overlay_view *ov); - -status_t create_mode_list(void); - -#endif diff --git a/src/add-ons/accelerants/nvidia_gpgpu/engine/Jamfile b/src/add-ons/accelerants/nvidia_gpgpu/engine/Jamfile deleted file mode 100644 index 7d28e82cb3..0000000000 --- a/src/add-ons/accelerants/nvidia_gpgpu/engine/Jamfile +++ /dev/null @@ -1,19 +0,0 @@ -SubDir HAIKU_TOP src add-ons accelerants nvidia_gpgpu engine ; - -SetSubDirSupportedPlatformsBeOSCompatible ; - -UsePrivateHeaders graphics ; -UsePrivateHeaders [ FDirName graphics nvidia_gpgpu ] ; - -StaticLibrary libnvidia_gpgpu_engine.a : - nv_acc_dma.c - nv_crtc.c - nv_crtc2.c - nv_dac.c - nv_dac2.c - nv_general.c - nv_globals.c - nv_i2c.c - nv_info.c - nv_support.c - ; diff --git a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_acc_dma.c b/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_acc_dma.c deleted file mode 100644 index ebf8626aa4..0000000000 --- a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_acc_dma.c +++ /dev/null @@ -1,1297 +0,0 @@ -/* NV Acceleration functions */ - -/* Author: - Rudolf Cornelissen 8/2003-6/2008. - - This code was possible thanks to: - - the Linux XFree86 NV driver, - - the Linux UtahGLX 3D driver. -*/ - -#define MODULE_BIT 0x00080000 - -#include "nv_std.h" - -/*acceleration notes*/ - -/*functions Be's app_server uses: -fill span (horizontal only) -fill rectangle (these 2 are very similar) -invert rectangle -blit -*/ - -static void nv_start_dma(void); -static status_t nv_acc_fifofree_dma(uint16 cmd_size); -static void nv_acc_cmd_dma(uint32 cmd, uint16 offset, uint16 size); -static void nv_acc_set_ch_dma(uint16 ch, uint32 handle); - -/* used to track engine DMA stalls */ -static uint8 err; - -/* wait until engine completely idle */ -status_t nv_acc_wait_idle_dma() -{ - /* we'd better check for timeouts on the DMA engine as it's theoretically - * breakable by malfunctioning software */ - uint16 cnt = 0; -return B_OK; - - /* wait until all upcoming commands are in execution at least. Do this until - * we hit a timeout; abort if we failed at least three times before: - * if DMA stalls, we have to forget about it alltogether at some point, or - * the system will almost come to a complete halt.. */ - /* note: - * it doesn't matter which FIFO channel's DMA registers we access, they are in - * fact all the same set. It also doesn't matter if the channel was assigned a - * command or not. */ - while ((NV_REG32(NVACC_FIFO + NV_GENERAL_DMAGET) != (si->engine.dma.put << 2)) && - (cnt < 10000) && (err < 3)) - { - /* snooze a bit so I do not hammer the bus */ - snooze (100); - cnt++; - } - - /* log timeout if we had one */ - if (cnt == 10000) - { - if (err < 3) err++; - LOG(4,("ACC_DMA: wait_idle; DMA timeout #%d, engine trouble!\n", err)); - } - - /* wait until execution completed */ - while (ACCR(STATUS)) - { - /* snooze a bit so I do not hammer the bus */ - snooze (100); - } - - return B_OK; -} - -/* AFAIK this must be done for every new screenmode. - * Engine required init. */ -status_t nv_acc_init_dma() -{ - uint32 cnt, tmp; - uint32 surf_depth, cmd_depth; - /* reset the engine DMA stalls counter */ - err = 0; - - /* a hanging engine only recovers from a complete power-down/power-up cycle */ - NV_REG32(NV32_PWRUPCTRL) = 0x13110011; - snooze(1000); - NV_REG32(NV32_PWRUPCTRL) = 0x13111111; - - /* setup PTIMER: */ - //fixme? how about NV28 setup as just after coldstarting? (see nv_info.c) - /* set timer numerator to 8 (in b0-15) */ - ACCW(PT_NUMERATOR, 0x00000008); - /* set timer denominator to 3 (in b0-15) */ - ACCW(PT_DENOMINATR, 0x00000003); - - /* disable timer-alarm INT requests (b0) */ - ACCW(PT_INTEN, 0x00000000); - /* reset timer-alarm INT status bit (b0) */ - ACCW(PT_INTSTAT, 0xffffffff); - - /* setup acc engine 'source' tile adressranges */ - if ((si->ps.card_type == NV40) || (si->ps.card_type == NV45)) - { - ACCW(NV10_FBTIL0AD, 0); - ACCW(NV10_FBTIL1AD, 0); - ACCW(NV10_FBTIL2AD, 0); - ACCW(NV10_FBTIL3AD, 0); - ACCW(NV10_FBTIL4AD, 0); - ACCW(NV10_FBTIL5AD, 0); - ACCW(NV10_FBTIL6AD, 0); - ACCW(NV10_FBTIL7AD, 0); - ACCW(NV10_FBTIL0ED, (si->ps.memory_size - 1)); - ACCW(NV10_FBTIL1ED, (si->ps.memory_size - 1)); - ACCW(NV10_FBTIL2ED, (si->ps.memory_size - 1)); - ACCW(NV10_FBTIL3ED, (si->ps.memory_size - 1)); - ACCW(NV10_FBTIL4ED, (si->ps.memory_size - 1)); - ACCW(NV10_FBTIL5ED, (si->ps.memory_size - 1)); - ACCW(NV10_FBTIL6ED, (si->ps.memory_size - 1)); - ACCW(NV10_FBTIL7ED, (si->ps.memory_size - 1)); - } - else - { - /* NV41, 43, 44, G70 and up */ - ACCW(NV41_FBTIL0AD, 0); - ACCW(NV41_FBTIL1AD, 0); - ACCW(NV41_FBTIL2AD, 0); - ACCW(NV41_FBTIL3AD, 0); - ACCW(NV41_FBTIL4AD, 0); - ACCW(NV41_FBTIL5AD, 0); - ACCW(NV41_FBTIL6AD, 0); - ACCW(NV41_FBTIL7AD, 0); - ACCW(NV41_FBTIL8AD, 0); - ACCW(NV41_FBTIL9AD, 0); - ACCW(NV41_FBTILAAD, 0); - ACCW(NV41_FBTILBAD, 0); - ACCW(NV41_FBTIL0ED, (si->ps.memory_size - 1)); - ACCW(NV41_FBTIL1ED, (si->ps.memory_size - 1)); - ACCW(NV41_FBTIL2ED, (si->ps.memory_size - 1)); - ACCW(NV41_FBTIL3ED, (si->ps.memory_size - 1)); - ACCW(NV41_FBTIL4ED, (si->ps.memory_size - 1)); - ACCW(NV41_FBTIL5ED, (si->ps.memory_size - 1)); - ACCW(NV41_FBTIL6ED, (si->ps.memory_size - 1)); - ACCW(NV41_FBTIL7ED, (si->ps.memory_size - 1)); - ACCW(NV41_FBTIL8ED, (si->ps.memory_size - 1)); - ACCW(NV41_FBTIL9ED, (si->ps.memory_size - 1)); - ACCW(NV41_FBTILAED, (si->ps.memory_size - 1)); - ACCW(NV41_FBTILBED, (si->ps.memory_size - 1)); - - if (si->ps.card_type >= G70) - { - ACCW(G70_FBTILCAD, 0); - ACCW(G70_FBTILDAD, 0); - ACCW(G70_FBTILEAD, 0); - ACCW(G70_FBTILCED, (si->ps.memory_size - 1)); - ACCW(G70_FBTILDED, (si->ps.memory_size - 1)); - ACCW(G70_FBTILEED, (si->ps.memory_size - 1)); - } - } - - /*** PRAMIN ***/ - /* first clear the entire RAMHT (hash-table) space to a defined state. It turns - * out at least NV11 will keep the previously programmed handles over resets and - * power-outages upto about 15 seconds!! Faulty entries might well hang the - * engine (confirmed on NV11). - * Note: - * this behaviour is not very strange: even very old DRAM chips are known to be - * able to do this, even though you should refresh them every few milliseconds or - * so. (Large memory cell capacitors, though different cells vary a lot in their - * capacity.) - * Of course data validity is not certain by a long shot over this large - * amount of time.. */ - for(cnt = 0; cnt < 0x0400; cnt++) - NV_REG32(NVACC_HT_HANDL_00 + (cnt << 2)) = 0; - /* RAMHT (hash-table) space SETUP FIFO HANDLES */ - /* note: - * 'instance' tells you where the engine command is stored in 'PR_CTXx_x' sets - * below: instance being b4-19 with baseadress NV_PRAMIN_CTX_0 (0x00700000). - * That command is linked to the handle noted here. This handle is then used to - * tell the FIFO to which engine command it is connected! - * (CTX registers are actually a sort of RAM space.) */ - - /* (first set) */ - ACCW(HT_HANDL_00, (0x80000000 | NV10_CONTEXT_SURFACES_2D)); /* 32bit handle (not used) */ - ACCW(HT_VALUE_00, 0x0010114c); /* instance $114c, engine = acc engine, CHID = $00 */ - - ACCW(HT_HANDL_01, (0x80000000 | NV_IMAGE_BLIT)); /* 32bit handle */ - ACCW(HT_VALUE_01, 0x00101148); /* instance $1148, engine = acc engine, CHID = $00 */ - - ACCW(HT_HANDL_02, (0x80000000 | NV4_GDI_RECTANGLE_TEXT)); /* 32bit handle */ - ACCW(HT_VALUE_02, 0x0010114a); /* instance $114a, engine = acc engine, CHID = $00 */ - - /* (second set) */ - ACCW(HT_HANDL_10, (0x80000000 | NV_ROP5_SOLID)); /* 32bit handle */ - ACCW(HT_VALUE_10, 0x00101142); /* instance $1142, engine = acc engine, CHID = $00 */ - - ACCW(HT_HANDL_11, (0x80000000 | NV_IMAGE_BLACK_RECTANGLE)); /* 32bit handle */ - ACCW(HT_VALUE_11, 0x00101144); /* instance $1144, engine = acc engine, CHID = $00 */ - - ACCW(HT_HANDL_12, (0x80000000 | NV_IMAGE_PATTERN)); /* 32bit handle */ - ACCW(HT_VALUE_12, 0x00101146); /* instance $1146, engine = acc engine, CHID = $00 */ - - ACCW(HT_HANDL_13, (0x80000000 | NV_SCALED_IMAGE_FROM_MEMORY)); /* 32bit handle */ - ACCW(HT_VALUE_13, 0x0010114e); /* instance $114e, engine = acc engine, CHID = $00 */ - - /* program CTX registers: CTX1 is mostly done later (colorspace dependant) */ - /* note: - * CTX determines which HT handles point to what engine commands. */ - /* note also: - * CTX registers are in fact in the same GPU internal RAM space as the engine's - * hashtable. This means that stuff programmed in here also survives resets and - * power-outages! (confirmed NV11) */ - - /* setup a DMA define for use by command defines below. */ - ACCW(PR_CTX0_R, 0x00003000); /* DMA page table present and of linear type; - * DMA target node is NVM (non-volatile memory?) - * (instead of doing PCI or AGP transfers) */ - ACCW(PR_CTX1_R, (si->ps.memory_size - 1)); /* DMA limit: size is all cardRAM */ - ACCW(PR_CTX2_R, ((0x00000000 & 0xfffff000) | 0x00000002)); - /* DMA access type is READ_AND_WRITE; - * memory starts at start of cardRAM (b12-31): - * It's adress needs to be at a 4kb boundary! */ - ACCW(PR_CTX3_R, 0x00000002); /* unknown (looks like this is rubbish/not needed?) */ - /* setup set '0' for cmd NV_ROP5_SOLID */ - ACCW(PR_CTX0_0, 0x02080043); /* NVclass $043, patchcfg ROP_AND, nv10+: little endian */ - ACCW(PR_CTX1_0, 0x00000000); /* colorspace not set, notify instance invalid (b16-31) */ - ACCW(PR_CTX2_0, 0x00000000); /* DMA0 and DMA1 instance invalid */ - ACCW(PR_CTX3_0, 0x00000000); /* method traps disabled */ - ACCW(PR_CTX0_1, 0x00000000); /* extra */ - ACCW(PR_CTX1_1, 0x00000000); /* extra */ - /* setup set '1' for cmd NV_IMAGE_BLACK_RECTANGLE */ - ACCW(PR_CTX0_2, 0x02080019); /* NVclass $019, patchcfg ROP_AND, nv10+: little endian */ - ACCW(PR_CTX1_2, 0x00000000); /* colorspace not set, notify instance invalid (b16-31) */ - ACCW(PR_CTX2_2, 0x00000000); /* DMA0 and DMA1 instance invalid */ - ACCW(PR_CTX3_2, 0x00000000); /* method traps disabled */ - ACCW(PR_CTX0_3, 0x00000000); /* extra */ - ACCW(PR_CTX1_3, 0x00000000); /* extra */ - /* setup set '2' for cmd NV_IMAGE_PATTERN */ - ACCW(PR_CTX0_4, 0x02080018); /* NVclass $018, patchcfg ROP_AND, nv10+: little endian */ - ACCW(PR_CTX1_4, 0x02000000); /* colorspace not set, notify instance is $0200 (b16-31) */ - ACCW(PR_CTX2_4, 0x00000000); /* DMA0 and DMA1 instance invalid */ - ACCW(PR_CTX3_4, 0x00000000); /* method traps disabled */ - ACCW(PR_CTX0_5, 0x00000000); /* extra */ - ACCW(PR_CTX1_5, 0x00000000); /* extra */ - /* setup set '4' for cmd NV12_IMAGE_BLIT */ - ACCW(PR_CTX0_6, 0x0208009f); /* NVclass $09f, patchcfg ROP_AND, nv10+: little endian */ - ACCW(PR_CTX1_6, 0x00000000); /* colorspace not set, notify instance invalid (b16-31) */ - ACCW(PR_CTX2_6, 0x00001140); /* DMA0 instance is $1140, DMA1 instance invalid */ - ACCW(PR_CTX3_6, 0x00001140); /* method trap 0 is $1140, trap 1 disabled */ - ACCW(PR_CTX0_7, 0x00000000); /* extra */ - ACCW(PR_CTX1_7, 0x00000000); /* extra */ - /* setup set '5' for cmd NV4_GDI_RECTANGLE_TEXT */ - ACCW(PR_CTX0_8, 0x0208004a); /* NVclass $04a, patchcfg ROP_AND, nv10+: little endian */ - ACCW(PR_CTX1_8, 0x02000000); /* colorspace not set, notify instance is $0200 (b16-31) */ - ACCW(PR_CTX2_8, 0x00000000); /* DMA0 and DMA1 instance invalid */ - ACCW(PR_CTX3_8, 0x00000000); /* method traps disabled */ - ACCW(PR_CTX0_9, 0x00000000); /* extra */ - ACCW(PR_CTX1_9, 0x00000000); /* extra */ - /* setup set '6' for cmd NV10_CONTEXT_SURFACES_2D */ - ACCW(PR_CTX0_A, 0x02080062); /* NVclass $062, nv10+: little endian */ - ACCW(PR_CTX1_A, 0x00000000); /* colorspace not set, notify instance invalid (b16-31) */ - ACCW(PR_CTX2_A, 0x00001140); /* DMA0 instance is $1140, DMA1 instance invalid */ - ACCW(PR_CTX3_A, 0x00001140); /* method trap 0 is $1140, trap 1 disabled */ - ACCW(PR_CTX0_B, 0x00000000); /* extra */ - ACCW(PR_CTX1_B, 0x00000000); /* extra */ - /* setup set '7' for cmd NV_SCALED_IMAGE_FROM_MEMORY */ - ACCW(PR_CTX0_C, 0x02080077); /* NVclass $077, nv10+: little endian */ - ACCW(PR_CTX1_C, 0x00000000); /* colorspace not set, notify instance invalid (b16-31) */ - ACCW(PR_CTX2_C, 0x00001140); /* DMA0 instance is $1140, DMA1 instance invalid */ - ACCW(PR_CTX3_C, 0x00001140); /* method trap 0 is $1140, trap 1 disabled */ - ACCW(PR_CTX0_D, 0x00000000); /* extra */ - ACCW(PR_CTX1_D, 0x00000000); /* extra */ - /* setup DMA set pointed at by PF_CACH1_DMAI */ - ACCW(PR_CTX0_E, 0x00003002); /* DMA page table present and of linear type; - * DMA class is $002 (b0-11); - * DMA target node is NVM (non-volatile memory?) - * (instead of doing PCI or AGP transfers) */ - ACCW(PR_CTX1_E, 0x00007fff); /* DMA limit: tablesize is 32k bytes */ - ACCW(PR_CTX2_E, (((si->ps.memory_size - 1) & 0xffff8000) | 0x00000002)); - /* DMA access type is READ_AND_WRITE; - * table is located at end of cardRAM (b12-31): - * It's adress needs to be at a 4kb boundary! */ - - /* do a explicit engine reset */ - ACCW(DEBUG0, 0xffffffff); - ACCW(DEBUG0, 0x00000000); - /* disable all acceleration engine INT reguests */ - ACCW(ACC_INTE, 0x00000000); - /* reset all acceration engine INT status bits */ - ACCW(ACC_INTS, 0xffffffff); - /* context control enabled */ - ACCW(NV10_CTX_CTRL, 0x10010100); - /* all acceleration buffers, pitches and colors are valid */ - ACCW(NV10_ACC_STAT, 0xffffffff); - /* enable acceleration engine command FIFO */ - ACCW(FIFO_EN, 0x00000001); - /* setup surface type: - * b1-0 = %01 = surface type is non-swizzle; - * this is needed to enable 3D on NV1x (confirmed) and maybe others? */ - ACCW(NV10_SURF_TYP, ((ACCR(NV10_SURF_TYP)) & 0x0007ff00)); - ACCW(NV10_SURF_TYP, ((ACCR(NV10_SURF_TYP)) | 0x00020101)); - - /* init some function blocks */ - ACCW(DEBUG1, 0x401287c0); - ACCW(DEBUG3, 0x60de8051); - /* disable specific functions, but enable SETUP_SPARE2 register */ - ACCW(NV10_DEBUG4, 0x00008000); - /* set limit_viol_pix_adress(?): more likely something unknown.. */ - ACCW(NV25_WHAT0, 0x00be3c5f); - - /* setup some unknown serially accessed registers (?) */ - tmp = (NV_REG32(NV32_NV4X_WHAT0) & 0x000000ff); - for (cnt = 0; (tmp && !(tmp & 0x00000001)); tmp >>= 1, cnt++); - { - ACCW(NV4X_WHAT2, cnt); - } - - /* unknown.. */ - switch (si->ps.card_type) - { - case NV40: - case NV45: - /* and NV48: but these are pgm'd as NV45 currently */ - ACCW(NV40_WHAT0, 0x83280fff); - ACCW(NV40_WHAT1, 0x000000a0); - ACCW(NV40_WHAT2, 0x0078e366); - ACCW(NV40_WHAT3, 0x0000014c); - break; - case NV41: - /* and ID == 0x012x: but no cards defined yet */ - ACCW(NV40P_WHAT0, 0x83280eff); - ACCW(NV40P_WHAT1, 0x000000a0); - ACCW(NV40P_WHAT2, 0x007596ff); - ACCW(NV40P_WHAT3, 0x00000108); - break; - case NV43: - ACCW(NV40P_WHAT0, 0x83280eff); - ACCW(NV40P_WHAT1, 0x000000a0); - ACCW(NV40P_WHAT2, 0x0072cb77); - ACCW(NV40P_WHAT3, 0x00000108); - break; - case NV44: - case G72: - ACCW(NV40P_WHAT0, 0x83280eff); - ACCW(NV40P_WHAT1, 0x000000a0); - - NV_REG32(NV32_NV44_WHAT10) = NV_REG32(NV32_NV10STRAPINFO); - NV_REG32(NV32_NV44_WHAT11) = 0x00000000; - NV_REG32(NV32_NV44_WHAT12) = 0x00000000; - NV_REG32(NV32_NV44_WHAT13) = NV_REG32(NV32_NV10STRAPINFO); - - ACCW(NV44_WHAT2, 0x00000000); - ACCW(NV44_WHAT3, 0x00000000); - break; -/* case NV44 type 2: (cardID 0x022x) - //fixme if needed: doesn't seem to need the strapinfo thing.. - ACCW(NV40P_WHAT0, 0x83280eff); - ACCW(NV40P_WHAT1, 0x000000a0); - - ACCW(NV44_WHAT2, 0x00000000); - ACCW(NV44_WHAT3, 0x00000000); - break; -*/ case G70: - case G71: - case G73: - ACCW(NV40P_WHAT0, 0x83280eff); - ACCW(NV40P_WHAT1, 0x000000a0); - ACCW(NV40P_WHAT2, 0x07830610); - ACCW(NV40P_WHAT3, 0x0000016a); - break; - default: - ACCW(NV40P_WHAT0, 0x83280eff); - ACCW(NV40P_WHAT1, 0x000000a0); - break; - } - - ACCW(NV10_TIL3PT, 0x2ffff800); - ACCW(NV10_TIL3ST, 0x00006000); - ACCW(NV4X_WHAT1, 0x01000000); - /* engine data source DMA instance = $1140 */ - ACCW(NV4X_DMA_SRC, 0x00001140); - - /* copy tile setup stuff from previous setup 'source' to acc engine - * (pattern colorRAM?) */ - if ((si->ps.card_type == NV40) || (si->ps.card_type == NV45)) - { - for (cnt = 0; cnt < 32; cnt++) - { - /* copy NV10_FBTIL0AD upto/including NV10_FBTIL7ST */ - NV_REG32(NVACC_NV20_WHAT0 + (cnt << 2)) = - NV_REG32(NVACC_NV10_FBTIL0AD + (cnt << 2)); - - /* copy NV10_FBTIL0AD upto/including NV10_FBTIL7ST */ - NV_REG32(NVACC_NV20_2_WHAT0 + (cnt << 2)) = - NV_REG32(NVACC_NV10_FBTIL0AD + (cnt << 2)); - } - } - else - { - /* NV41, 43, 44, G70 and later */ - if (si->ps.card_type >= G70) - { - for (cnt = 0; cnt < 60; cnt++) - { - /* copy NV41_FBTIL0AD upto/including G70_FBTILEST */ - NV_REG32(NVACC_NV41_WHAT0 + (cnt << 2)) = - NV_REG32(NVACC_NV41_FBTIL0AD + (cnt << 2)); - - /* copy NV41_FBTIL0AD upto/including G70_FBTILEST */ - NV_REG32(NVACC_NV20_2_WHAT0 + (cnt << 2)) = - NV_REG32(NVACC_NV41_FBTIL0AD + (cnt << 2)); - } - } - else - { - /* NV41, 43, 44 */ - for (cnt = 0; cnt < 48; cnt++) - { - /* copy NV41_FBTIL0AD upto/including NV41_FBTILBST */ - NV_REG32(NVACC_NV20_WHAT0 + (cnt << 2)) = - NV_REG32(NVACC_NV41_FBTIL0AD + (cnt << 2)); - - if (si->ps.card_type != NV44) - { - /* copy NV41_FBTIL0AD upto/including NV41_FBTILBST */ - NV_REG32(NVACC_NV20_2_WHAT0 + (cnt << 2)) = - NV_REG32(NVACC_NV41_FBTIL0AD + (cnt << 2)); - } - } - } - } - - if ((si->ps.card_type == NV40) || (si->ps.card_type == NV45)) - { - /* copy some RAM configuration info(?) */ - ACCW(NV20_WHAT_T0, NV_REG32(NV32_PFB_CONFIG_0)); - ACCW(NV20_WHAT_T1, NV_REG32(NV32_PFB_CONFIG_1)); - ACCW(NV40_WHAT_T2, NV_REG32(NV32_PFB_CONFIG_0)); - ACCW(NV40_WHAT_T3, NV_REG32(NV32_PFB_CONFIG_1)); - - /* setup location of active screen in framebuffer */ - ACCW(NV20_OFFSET0, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer)); - ACCW(NV20_OFFSET1, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer)); - /* setup accesible card memory range */ - ACCW(NV20_BLIMIT6, (si->ps.memory_size - 1)); - ACCW(NV20_BLIMIT7, (si->ps.memory_size - 1)); - } - else - { - /* NV41, 43, 44, G70 and later */ - - /* copy some RAM configuration info(?) */ - if (si->ps.card_type >= G70) - { - ACCW(G70_WHAT_T0, NV_REG32(NV32_PFB_CONFIG_0)); - ACCW(G70_WHAT_T1, NV_REG32(NV32_PFB_CONFIG_1)); - } - else - { - /* NV41, 43, 44 */ - ACCW(NV40P_WHAT_T0, NV_REG32(NV32_PFB_CONFIG_0)); - ACCW(NV40P_WHAT_T1, NV_REG32(NV32_PFB_CONFIG_1)); - } - ACCW(NV40P_WHAT_T2, NV_REG32(NV32_PFB_CONFIG_0)); - ACCW(NV40P_WHAT_T3, NV_REG32(NV32_PFB_CONFIG_1)); - - /* setup location of active screen in framebuffer */ - ACCW(NV40P_OFFSET0, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer)); - ACCW(NV40P_OFFSET1, ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer)); - /* setup accesible card memory range */ - ACCW(NV40P_BLIMIT6, (si->ps.memory_size - 1)); - ACCW(NV40P_BLIMIT7, (si->ps.memory_size - 1)); - } - - /* setup some acc engine tile stuff */ - ACCW(NV10_TIL2AD, 0x00000000); - ACCW(NV10_TIL0ED, 0xffffffff); - - /* all cards: */ - /* setup clipping: rect size is 32768 x 32768, probably max. setting */ - /* note: - * can also be done via the NV_IMAGE_BLACK_RECTANGLE engine command. */ - ACCW(ABS_UCLP_XMIN, 0x00000000); - ACCW(ABS_UCLP_YMIN, 0x00000000); - ACCW(ABS_UCLP_XMAX, 0x00007fff); - ACCW(ABS_UCLP_YMAX, 0x00007fff); - - /* setup sync parameters for NV12_IMAGE_BLIT command for the current mode: - * values given are CRTC vertical counter limit values. The NV12 command will wait - * for the specified's CRTC's vertical counter to be in between the given values */ - ACCW(NV11_CRTC_LO, si->dm.timing.v_display - 1); - ACCW(NV11_CRTC_HI, si->dm.timing.v_display + 1); - - /*** PFIFO ***/ - /* (setup caches) */ - /* disable caches reassign */ - ACCW(PF_CACHES, 0x00000000); - /* PFIFO mode: channel 0 is in DMA mode, channels 1 - 32 are in PIO mode */ - ACCW(PF_MODE, 0x00000001); - /* cache1 push0 access disabled */ - ACCW(PF_CACH1_PSH0, 0x00000000); - /* cache1 pull0 access disabled */ - ACCW(PF_CACH1_PUL0, 0x00000000); - /* cache1 push1 mode = DMA */ - ACCW(PF_CACH1_PSH1, 0x00010000); - /* cache1 DMA Put offset = 0 (b2-28) */ - ACCW(PF_CACH1_DMAP, 0x00000000); - /* cache1 DMA Get offset = 0 (b2-28) */ - ACCW(PF_CACH1_DMAG, 0x00000000); - /* cache1 DMA instance adress = $114e (b0-15); - * instance being b4-19 with baseadress NV_PRAMIN_CTX_0 (0x00700000). */ - /* note: - * should point to a DMA definition in CTX register space (which is sort of RAM). - * This define tells the engine where the DMA cmd buffer is and what it's size is. - * Inside that cmd buffer you'll find the actual issued engine commands. */ - ACCW(PF_CACH1_DMAI, 0x00001150); - /* cache0 push0 access disabled */ - ACCW(PF_CACH0_PSH0, 0x00000000); - /* cache0 pull0 access disabled */ - ACCW(PF_CACH0_PUL0, 0x00000000); - /* RAM HT (hash table) baseadress = $10000 (b4-8), size = 4k, - * search = 128 (is byte offset between hash 'sets') */ - /* note: - * so HT base is $00710000, last is $00710fff. - * In this space you define the engine command handles (HT_HANDL_XX), which - * in turn points to the defines in CTX register space (which is sort of RAM) */ - ACCW(PF_RAMHT, 0x03000100); - /* RAM FC baseadress = $11000 (b3-8) (size is fixed to 0.5k(?)) */ - /* note: - * so FC base is $00711000, last is $007111ff. (not used?) */ - ACCW(PF_RAMFC, 0x00000110); - /* RAM RO baseadress = $11200 (b1-8), size = 0.5k */ - /* note: - * so RO base is $00711200, last is $007113ff. (not used?) */ - /* note also: - * This means(?) the PRAMIN CTX registers are accessible from base $00711400. */ - ACCW(PF_RAMRO, 0x00000112); - /* PFIFO size: ch0-15 = 512 bytes, ch16-31 = 124 bytes */ - ACCW(PF_SIZE, 0x0000ffff); - /* cache1 hash instance = $ffff (b0-15) */ - ACCW(PF_CACH1_HASH, 0x0000ffff); - /* disable all PFIFO INTs */ - ACCW(PF_INTEN, 0x00000000); - /* reset all PFIFO INT status bits */ - ACCW(PF_INTSTAT, 0xffffffff); - /* cache0 pull0 engine = acceleration engine (graphics) */ - ACCW(PF_CACH0_PUL1, 0x00000001); - /* cache1 DMA control: disable some stuff */ - ACCW(PF_CACH1_DMAC, 0x00000000); - /* cache1 engine 0 upto/including 7 is software (could also be graphics or DVD) */ - ACCW(PF_CACH1_ENG, 0x00000000); - /* cache1 DMA fetch: trigger at 128 bytes, size is 32 bytes, max requests is 15, - * use little endian */ - ACCW(PF_CACH1_DMAF, 0x000f0078); - /* cache1 DMA push: b0 = 1: access is enabled */ - ACCW(PF_CACH1_DMAS, 0x00000001); - /* cache1 push0 access enabled */ - ACCW(PF_CACH1_PSH0, 0x00000001); - /* cache1 pull0 access enabled */ - ACCW(PF_CACH1_PUL0, 0x00000001); - /* cache1 pull1 engine = acceleration engine (graphics) */ - ACCW(PF_CACH1_PUL1, 0x00000001); - /* enable PFIFO caches reassign */ - ACCW(PF_CACHES, 0x00000001); - - /*** init acceleration engine command info ***/ - /* set object handles */ - /* note: - * probably depending on some other setup, there are 8 or 32 FIFO channels - * available. Assuming the current setup only has 8 channels because the 'rest' - * isn't setup here... */ - si->engine.fifo.handle[0] = NV_ROP5_SOLID; - si->engine.fifo.handle[1] = NV_IMAGE_BLACK_RECTANGLE; - si->engine.fifo.handle[2] = NV_IMAGE_PATTERN; - si->engine.fifo.handle[3] = NV4_SURFACE; /* NV10_CONTEXT_SURFACES_2D is identical */ - si->engine.fifo.handle[4] = NV_IMAGE_BLIT; - si->engine.fifo.handle[5] = NV4_GDI_RECTANGLE_TEXT; - /* not used currently */ - si->engine.fifo.handle[6] = 0; - si->engine.fifo.handle[7] = 0; - /* preset no FIFO channels assigned to cmd's */ - for (cnt = 0; cnt < 0x20; cnt++) - { - si->engine.fifo.ch_ptr[cnt] = 0; - } - /* set handle's pointers to their assigned FIFO channels */ - /* note: - * b0-1 aren't used as adressbits. Using b0 to indicate a valid pointer. */ - for (cnt = 0; cnt < 0x08; cnt++) - { - si->engine.fifo.ch_ptr[(si->engine.fifo.handle[cnt])] = - (0x00000001 + (cnt * 0x00002000)); - } - - /*** init DMA command buffer info ***/ - si->dma_buffer = (void *)((char *)si->framebuffer + - ((si->ps.memory_size - 1) & 0xffff8000)); - - LOG(4,("ACC_DMA: command buffer is at adress $%08x\n", - ((uint32)(si->dma_buffer)))); - /* we have issued no DMA cmd's to the engine yet */ - si->engine.dma.put = 0; - /* the current first free adress in the DMA buffer is at offset 0 */ - si->engine.dma.current = 0; - /* the DMA buffer can hold 8k 32-bit words (it's 32kb in size). */ - /* note: - * one word is reserved at the end of the DMA buffer to be able to instruct the - * engine to do a buffer wrap-around! - * (DMA opcode 'noninc method': issue word $20000000.) */ - si->engine.dma.max = 8192 - 1; - /* note the current free space we have left in the DMA buffer */ - si->engine.dma.free = si->engine.dma.max - si->engine.dma.current; - - /*** init FIFO via DMA command buffer. ***/ - /* wait for room in fifo for new FIFO assigment cmds if needed: */ - if (nv_acc_fifofree_dma(12) != B_OK) return B_ERROR; - - /* program new FIFO assignments */ - /* Raster OPeration: */ - nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH0, si->engine.fifo.handle[0]); - /* Clip: */ - nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH1, si->engine.fifo.handle[1]); - /* Pattern: */ - nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH2, si->engine.fifo.handle[2]); - /* 2D Surfaces: */ - nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH3, si->engine.fifo.handle[3]); - /* Blit: */ - nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH4, si->engine.fifo.handle[4]); - /* Bitmap: */ - nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH5, si->engine.fifo.handle[5]); - - /*** Set pixel width ***/ - switch(si->dm.space) - { - case B_CMAP8: - surf_depth = 0x00000001; - cmd_depth = 0x00000003; - break; - case B_RGB15_LITTLE: - case B_RGB16_LITTLE: - surf_depth = 0x00000004; - cmd_depth = 0x00000001; - break; - case B_RGB32_LITTLE: - case B_RGBA32_LITTLE: - surf_depth = 0x00000006; - cmd_depth = 0x00000003; - break; - default: - LOG(8,("ACC_DMA: init, invalid bit depth\n")); - return B_ERROR; - } - - /* wait for room in fifo for surface setup cmd if needed */ - if (nv_acc_fifofree_dma(5) != B_OK) return B_ERROR; - /* now setup 2D surface (writing 5 32bit words) */ - nv_acc_cmd_dma(NV4_SURFACE, NV4_SURFACE_FORMAT, 4); - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = surf_depth; /* Format */ - /* setup screen pitch */ - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = - ((si->fbc.bytes_per_row & 0x0000ffff) | (si->fbc.bytes_per_row << 16)); /* Pitch */ - /* setup screen location */ - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = - ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer); /* OffsetSource */ - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = - ((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer); /* OffsetDest */ - - /* wait for room in fifo for pattern colordepth setup cmd if needed */ - if (nv_acc_fifofree_dma(2) != B_OK) return B_ERROR; - /* set pattern colordepth (writing 2 32bit words) */ - nv_acc_cmd_dma(NV_IMAGE_PATTERN, NV_IMAGE_PATTERN_SETCOLORFORMAT, 1); - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = cmd_depth; /* SetColorFormat */ - - /* wait for room in fifo for bitmap colordepth setup cmd if needed */ - if (nv_acc_fifofree_dma(2) != B_OK) return B_ERROR; - /* set bitmap colordepth (writing 2 32bit words) */ - nv_acc_cmd_dma(NV4_GDI_RECTANGLE_TEXT, NV4_GDI_RECTANGLE_TEXT_SETCOLORFORMAT, 1); - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = cmd_depth; /* SetColorFormat */ - - /* Load our pattern into the engine: */ - /* wait for room in fifo for pattern cmd if needed. */ - if (nv_acc_fifofree_dma(7) != B_OK) return B_ERROR; - /* now setup pattern (writing 7 32bit words) */ - nv_acc_cmd_dma(NV_IMAGE_PATTERN, NV_IMAGE_PATTERN_SETSHAPE, 1); - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0x00000000; /* SetShape: 0 = 8x8, 1 = 64x1, 2 = 1x64 */ - nv_acc_cmd_dma(NV_IMAGE_PATTERN, NV_IMAGE_PATTERN_SETCOLOR0, 4); - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0xffffffff; /* SetColor0 */ - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0xffffffff; /* SetColor1 */ - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0xffffffff; /* SetPattern[0] */ - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0xffffffff; /* SetPattern[1] */ - - /* tell the engine to fetch and execute all (new) commands in the DMA buffer */ - nv_start_dma(); - - return B_OK; -} - -static void nv_start_dma(void) -{ - uint32 dummy; - - if (si->engine.dma.current != si->engine.dma.put) - { - si->engine.dma.put = si->engine.dma.current; - /* dummy read the first adress of the framebuffer to flush MTRR-WC buffers */ - dummy = *((volatile uint32 *)(si->framebuffer)); - - /* actually start DMA to execute all commands now in buffer */ - /* note: - * it doesn't matter which FIFO channel's DMA registers we access, they are in - * fact all the same set. It also doesn't matter if the channel was assigned a - * command or not. */ - /* note also: - * NV_GENERAL_DMAPUT is a write-only register on some cards (confirmed NV11). */ - NV_REG32(NVACC_FIFO + NV_GENERAL_DMAPUT) = (si->engine.dma.put << 2); - } -} - -/* this routine does not check the engine's internal hardware FIFO, but the DMA - * command buffer. You can see this as a FIFO as well, that feeds the hardware FIFO. - * The hardware FIFO state is checked by the DMA hardware automatically. */ -static status_t nv_acc_fifofree_dma(uint16 cmd_size) -{ - uint32 dmaget; - - /* we'd better check for timeouts on the DMA engine as it's theoretically - * breakable by malfunctioning software */ - uint16 cnt = 0; - - /* check if the DMA buffer has enough room for the command. - * note: - * engine.dma.free is 'cached' */ - while ((si->engine.dma.free < cmd_size) && (cnt < 10000) && (err < 3)) - { - /* see where the engine is currently fetching from the buffer */ - /* note: - * read this only once in the code as accessing registers is relatively slow */ - /* note also: - * it doesn't matter which FIFO channel's DMA registers we access, they are in - * fact all the same set. It also doesn't matter if the channel was assigned a - * command or not. */ - dmaget = ((NV_REG32(NVACC_FIFO + NV_GENERAL_DMAGET)) >> 2); - - /* update timeout counter: on NV11 on a Pentium4 2.8Ghz max reached count - * using BeRoMeter 1.2.6 was about 600; so counting 10000 before generating - * a timeout should definately do it. Snooze()-ing cannot be done without a - * serious speed penalty, even if done for only 1 microSecond. */ - cnt++; - - /* where's the engine fetching viewed from us issuing? */ - if (si->engine.dma.put >= dmaget) - { - /* engine is fetching 'behind us', the last piece of the buffer is free */ - - /* note the 'updated' free space we have in the DMA buffer */ - si->engine.dma.free = si->engine.dma.max - si->engine.dma.current; - /* if it's enough after all we exit this routine immediately. Else: */ - if (si->engine.dma.free < cmd_size) - { - /* not enough room left, so instruct DMA engine to reset the buffer - * when it's reaching the end of it */ - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0x20000000; - /* reset our buffer pointer, so new commands will be placed at the - * beginning of the buffer. */ - si->engine.dma.current = 0; - /* tell the engine to fetch the remaining command(s) in the DMA buffer - * that where not executed before. */ - nv_start_dma(); - - /* NOW the engine is fetching 'in front of us', so the first piece - * of the buffer is free */ - - /* note the updated current free space we have in the DMA buffer */ - si->engine.dma.free = dmaget - si->engine.dma.current; - /* mind this pittfall: - * Leave some room between where the engine is fetching and where we - * put new commands. Otherwise the engine will crash on heavy loads. - * A crash can be forced best in 640x480x32 mode with BeRoMeter 1.2.6. - * (confirmed on NV11 and NV43 with less than 256 words forced freespace.) - * Note: - * The engine is DMA triggered for fetching chunks every 128 bytes, - * maybe this is the reason for this behaviour. - * Note also: - * it looks like the space that needs to be kept free is coupled - * with the size of the DMA buffer. */ - if (si->engine.dma.free < 256) - si->engine.dma.free = 0; - else - si->engine.dma.free -= 256; - } - } - else - { - /* engine is fetching 'in front of us', so the first piece of the buffer - * is free */ - - /* note the updated current free space we have in the DMA buffer */ - si->engine.dma.free = dmaget - si->engine.dma.current; - /* mind this pittfall: - * Leave some room between where the engine is fetching and where we - * put new commands. Otherwise the engine will crash on heavy loads. - * A crash can be forced best in 640x480x32 mode with BeRoMeter 1.2.6. - * (confirmed on NV11 and NV43 with less than 256 words forced freespace.) - * Note: - * The engine is DMA triggered for fetching chunks every 128 bytes, - * maybe this is the reason for this behaviour. - * Note also: - * it looks like the space that needs to be kept free is coupled - * with the size of the DMA buffer. */ - if (si->engine.dma.free < 256) - si->engine.dma.free = 0; - else - si->engine.dma.free -= 256; - } - } - - /* log timeout if we had one */ - if (cnt == 10000) - { - if (err < 3) err++; - LOG(4,("ACC_DMA: fifofree; DMA timeout #%d, engine trouble!\n", err)); - } - - /* we must make the acceleration routines abort or the driver will hang! */ - if (err >= 3) return B_ERROR; - - return B_OK; -} - -static void nv_acc_cmd_dma(uint32 cmd, uint16 offset, uint16 size) -{ - /* NV_FIFO_DMA_OPCODE: set number of cmd words (b18 - 28); set FIFO offset for - * first cmd word (b2 - 15); set DMA opcode = method (b29 - 31). - * a 'NOP' is the opcode word $00000000. */ - /* note: - * possible DMA opcodes: - * b'000' is 'method' (execute cmd); - * b'001' is 'jump'; - * b'002' is 'noninc method' (execute buffer wrap-around); - * b'003' is 'call': return is executed by opcode word $00020000 (b17 = 1). */ - /* note also: - * this system uses auto-increments for the FIFO offset adresses. Make sure - * to set a new adress if a gap exists between the previous one and the new one. */ - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = ((size << 18) | - ((si->engine.fifo.ch_ptr[cmd] + offset) & 0x0000fffc)); - - /* space left after issuing the current command is the cmd AND it's arguments less */ - si->engine.dma.free -= (size + 1); -} - -static void nv_acc_set_ch_dma(uint16 ch, uint32 handle) -{ - /* issue FIFO channel assign cmd */ - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = ((1 << 18) | ch); - /* set new assignment */ - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = (0x80000000 | handle); - - /* space left after issuing the current command is the cmd AND it's arguments less */ - si->engine.dma.free -= 2; -} - -/* note: - * switching fifo channel assignments this way has no noticable slowdown: - * measured 0.2% with Quake2. */ -void nv_acc_assert_fifo_dma(void) -{ - /* does every engine cmd this accelerant needs have a FIFO channel? */ - //fixme: can probably be optimized for both speed and channel selection... - if (!si->engine.fifo.ch_ptr[NV_ROP5_SOLID] || - !si->engine.fifo.ch_ptr[NV_IMAGE_BLACK_RECTANGLE] || - !si->engine.fifo.ch_ptr[NV_IMAGE_PATTERN] || - !si->engine.fifo.ch_ptr[NV4_SURFACE] || - !si->engine.fifo.ch_ptr[NV_IMAGE_BLIT] || - !si->engine.fifo.ch_ptr[NV4_GDI_RECTANGLE_TEXT] || - !si->engine.fifo.ch_ptr[NV_SCALED_IMAGE_FROM_MEMORY]) - { - uint16 cnt; - - /* free the FIFO channels we want from the currently assigned cmd's */ - si->engine.fifo.ch_ptr[si->engine.fifo.handle[0]] = 0; - si->engine.fifo.ch_ptr[si->engine.fifo.handle[1]] = 0; - si->engine.fifo.ch_ptr[si->engine.fifo.handle[2]] = 0; - si->engine.fifo.ch_ptr[si->engine.fifo.handle[3]] = 0; - si->engine.fifo.ch_ptr[si->engine.fifo.handle[4]] = 0; - si->engine.fifo.ch_ptr[si->engine.fifo.handle[5]] = 0; - si->engine.fifo.ch_ptr[si->engine.fifo.handle[6]] = 0; - - /* set new object handles */ - si->engine.fifo.handle[0] = NV_ROP5_SOLID; - si->engine.fifo.handle[1] = NV_IMAGE_BLACK_RECTANGLE; - si->engine.fifo.handle[2] = NV_IMAGE_PATTERN; - si->engine.fifo.handle[3] = NV4_SURFACE; - si->engine.fifo.handle[4] = NV_IMAGE_BLIT; - si->engine.fifo.handle[5] = NV4_GDI_RECTANGLE_TEXT; - si->engine.fifo.handle[6] = NV_SCALED_IMAGE_FROM_MEMORY; - - /* set handle's pointers to their assigned FIFO channels */ - /* note: - * b0-1 aren't used as adressbits. Using b0 to indicate a valid pointer. */ - for (cnt = 0; cnt < 0x08; cnt++) - { - si->engine.fifo.ch_ptr[(si->engine.fifo.handle[cnt])] = - (0x00000001 + (cnt * 0x00002000)); - } - - /* wait for room in fifo for new FIFO assigment cmds if needed. */ - if (nv_acc_fifofree_dma(14) != B_OK) return; - - /* program new FIFO assignments */ - /* Raster OPeration: */ - nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH0, si->engine.fifo.handle[0]); - /* Clip: */ - nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH1, si->engine.fifo.handle[1]); - /* Pattern: */ - nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH2, si->engine.fifo.handle[2]); - /* 2D Surface: */ - nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH3, si->engine.fifo.handle[3]); - /* Blit: */ - nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH4, si->engine.fifo.handle[4]); - /* Bitmap: */ - nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH5, si->engine.fifo.handle[5]); - /* Scaled and fitered Blit: */ - nv_acc_set_ch_dma(NV_GENERAL_FIFO_CH6, si->engine.fifo.handle[6]); - - /* tell the engine to fetch and execute all (new) commands in the DMA buffer */ - nv_start_dma(); - } -} - -/* - note: - moved acceleration 'top-level' routines to be integrated in the engine: - it is costly to call the engine for every single function within a loop! - (measured with BeRoMeter 1.2.6: upto 15% speed increase on all CPU's.) - - note also: - splitting up each command list into sublists (see routines below) prevents - a lot more nested calls, further increasing the speed with upto 70%. - - finally: - sending the sublist to just one single engine command even further increases - speed with upto another 10%. This can't be done for blits though, as this engine- - command's hardware does not support multiple objects. -*/ - -/* screen to screen blit - i.e. move windows around and scroll within them. */ -void SCREEN_TO_SCREEN_BLIT_DMA(engine_token *et, blit_params *list, uint32 count) -{ - uint32 i = 0; - uint16 subcnt; - - /*** init acc engine for blit function ***/ - /* ROP registers (Raster OPeration): - * wait for room in fifo for ROP cmd if needed. */ - if (nv_acc_fifofree_dma(2) != B_OK) return; - /* now setup ROP (writing 2 32bit words) for GXcopy */ - nv_acc_cmd_dma(NV_ROP5_SOLID, NV_ROP5_SOLID_SETROP5, 1); - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0xcc; /* SetRop5 */ - - /*** do each blit ***/ - /* Note: - * blit-copy direction is determined inside nvidia hardware: no setup needed */ - while (count) - { - /* break up the list in sublists to minimize calls, while making sure long - * lists still get executed without trouble */ - subcnt = 32; - if (count < 32) subcnt = count; - count -= subcnt; - - /* wait for room in fifo for blit cmd if needed. */ - if (nv_acc_fifofree_dma(4 * subcnt) != B_OK) return; - - while (subcnt--) - { - /* now setup blit (writing 4 32bit words) */ - nv_acc_cmd_dma(NV_IMAGE_BLIT, NV_IMAGE_BLIT_SOURCEORG, 3); - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = - (((list[i].src_top) << 16) | (list[i].src_left)); /* SourceOrg */ - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = - (((list[i].dest_top) << 16) | (list[i].dest_left)); /* DestOrg */ - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = - ((((list[i].height) + 1) << 16) | ((list[i].width) + 1)); /* HeightWidth */ - - i++; - } - - /* tell the engine to fetch the commands in the DMA buffer that where not - * executed before. */ - nv_start_dma(); - } - - /* tell 3D add-ons that they should reload their rendering states and surfaces */ - si->engine.threeD.reload = 0xffffffff; -} - -/* scaled and filtered screen to screen blit - i.e. video playback without overlay */ -/* note: source and destination may not overlap. */ -//fixme? checkout NV5 and NV10 version of cmd: faster?? (or is 0x77 a 'autoselect' version?) -void SCREEN_TO_SCREEN_SCALED_FILTERED_BLIT_DMA(engine_token *et, scaled_blit_params *list, uint32 count) -{ - uint32 i = 0; - uint16 subcnt; - uint32 cmd_depth; - uint8 bpp; - - /*** init acc engine for scaled filtered blit function ***/ - /* Set pixel width */ - switch(si->dm.space) - { - case B_RGB15_LITTLE: - cmd_depth = 0x00000002; - bpp = 2; - break; - case B_RGB16_LITTLE: - cmd_depth = 0x00000007; - bpp = 2; - break; - case B_RGB32_LITTLE: - case B_RGBA32_LITTLE: - cmd_depth = 0x00000004; - bpp = 4; - break; - /* fixme sometime: - * we could do the spaces below if this function would be modified to be able - * to use a source outside of the desktop, i.e. using offscreen bitmaps... */ - case B_YCbCr422: - cmd_depth = 0x00000005; - bpp = 2; - break; - case B_YUV422: - cmd_depth = 0x00000006; - bpp = 2; - break; - default: - /* note: this function does not support src or dest in the B_CMAP8 space! */ - //fixme: the NV10 version of this cmd supports B_CMAP8 src though... (checkout) - LOG(8,("ACC_DMA: scaled_filtered_blit, invalid bit depth\n")); - return; - } - - /* modify surface depth settings for 15-bit colorspace so command works as intended */ - if (si->dm.space == B_RGB15_LITTLE) - { - /* wait for room in fifo for surface setup cmd if needed */ - if (nv_acc_fifofree_dma(2) != B_OK) return; - /* now setup 2D surface (writing 1 32bit word) */ - nv_acc_cmd_dma(NV4_SURFACE, NV4_SURFACE_FORMAT, 1); - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0x00000002; /* Format */ - } - - /* program operation mode 'SRCcopy' */ - /* wait for room in fifo for cmds if needed. */ - if (nv_acc_fifofree_dma(5) != B_OK) return; - /* now setup source bitmap colorspace */ - nv_acc_cmd_dma(NV_SCALED_IMAGE_FROM_MEMORY, NV_SCALED_IMAGE_FROM_MEMORY_SETCOLORFORMAT, 2); - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = cmd_depth; /* SetColorFormat */ - /* now setup operation mode to SRCcopy */ - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0x00000003; /* SetOperation */ - - /* now setup fill color (writing 2 32bit words) */ - nv_acc_cmd_dma(NV4_GDI_RECTANGLE_TEXT, NV4_GDI_RECTANGLE_TEXT_COLOR1A, 1); - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0x00000000; /* Color1A */ - - /*** do each blit ***/ - while (count) - { - /* break up the list in sublists to minimize calls, while making sure long - * lists still get executed without trouble */ - subcnt = 16; - if (count < 16) subcnt = count; - count -= subcnt; - - /* wait for room in fifo for blit cmd if needed. */ - if (nv_acc_fifofree_dma(12 * subcnt) != B_OK) return; - - while (subcnt--) - { - /* now setup blit (writing 12 32bit words) */ - nv_acc_cmd_dma(NV_SCALED_IMAGE_FROM_MEMORY, NV_SCALED_IMAGE_FROM_MEMORY_SOURCEORG, 6); - /* setup dest clipping ref for blit (not used) (b0-15 = left, b16-31 = top) */ - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0; /* SourceOrg */ - /* setup dest clipping size for blit */ - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = - (((list[i].dest_height + 1) << 16) | (list[i].dest_width + 1)); /* SourceHeightWidth */ - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = - /* setup destination location and size for blit */ - (((list[i].dest_top) << 16) | (list[i].dest_left)); /* DestOrg */ - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = - (((list[i].dest_height + 1) << 16) | (list[i].dest_width + 1)); /* DestHeightWidth */ - //fixme: findout scaling limits... (although the current cmd interface doesn't support them.) - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = - (((list[i].src_width + 1) << 20) / (list[i].dest_width + 1)); /* HorInvScale (in 12.20 format) */ - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = - (((list[i].src_height + 1) << 20) / (list[i].dest_height + 1)); /* VerInvScale (in 12.20 format) */ - - nv_acc_cmd_dma(NV_SCALED_IMAGE_FROM_MEMORY, NV_SCALED_IMAGE_FROM_MEMORY_SOURCESIZE, 4); - /* setup horizontal and vertical source (fetching) ends. - * note: - * horizontal granularity is 2 pixels, vertical granularity is 1 pixel. - * look at Matrox or Neomagic bes engines code for usage example. */ - //fixme: tested 15, 16 and 32-bit RGB depth, verify other depths... - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = - (((list[i].src_height + 1) << 16) | - (((list[i].src_width + 1) + 0x0001) & ~0x0001)); /* SourceHeightWidth */ - /* setup source pitch (b0-15). Set 'format origin center' (b16-17) and - * select 'format interpolator foh (bilinear filtering)' (b24). */ - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = - (si->fbc.bytes_per_row | (1 << 16) | (1 << 24)); /* SourcePitch */ - /* setup source surface location */ - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = - ((uint32)((uint8*)si->fbc.frame_buffer - (uint8*)si->framebuffer)) + - (list[i].src_top * si->fbc.bytes_per_row) + (list[i].src_left * bpp); /* Offset */ - /* setup source start: first (sub)pixel contributing to output picture */ - /* note: - * clipping is not asked for. - * look at nVidia NV10+ bes engine code for useage example. */ - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = - 0; /* SourceRef (b0-15 = hor, b16-31 = ver: both in 12.4 format) */ - - i++; - } - - /* tell the engine to fetch the commands in the DMA buffer that where not - * executed before. */ - nv_start_dma(); - } - - /* reset surface depth settings so the other engine commands works as intended */ - if (si->dm.space == B_RGB15_LITTLE) - { - /* wait for room in fifo for surface setup cmd if needed */ - if (nv_acc_fifofree_dma(2) != B_OK) return; - /* now setup 2D surface (writing 1 32bit word) */ - nv_acc_cmd_dma(NV4_SURFACE, NV4_SURFACE_FORMAT, 1); - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0x00000004; /* Format */ - - /* tell the engine to fetch the commands in the DMA buffer that where not - * executed before. */ - nv_start_dma(); - } - - /* tell 3D add-ons that they should reload their rendering states and surfaces */ - si->engine.threeD.reload = 0xffffffff; -} - -/* rectangle fill - i.e. workspace and window background color */ -void FILL_RECTANGLE_DMA(engine_token *et, uint32 colorIndex, fill_rect_params *list, uint32 count) -{ - uint32 i = 0; - uint16 subcnt; - - /*** init acc engine for fill function ***/ - /* ROP registers (Raster OPeration): - * wait for room in fifo for ROP and bitmap cmd if needed. */ - if (nv_acc_fifofree_dma(4) != B_OK) return; - /* now setup ROP (writing 2 32bit words) for GXcopy */ - nv_acc_cmd_dma(NV_ROP5_SOLID, NV_ROP5_SOLID_SETROP5, 1); - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0xcc; /* SetRop5 */ - /* now setup fill color (writing 2 32bit words) */ - nv_acc_cmd_dma(NV4_GDI_RECTANGLE_TEXT, NV4_GDI_RECTANGLE_TEXT_COLOR1A, 1); - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = colorIndex; /* Color1A */ - - /*** draw each rectangle ***/ - while (count) - { - /* break up the list in sublists to minimize calls, while making sure long - * lists still get executed without trouble */ - subcnt = 32; - if (count < 32) subcnt = count; - count -= subcnt; - - /* wait for room in fifo for bitmap cmd if needed. */ - if (nv_acc_fifofree_dma(1 + (2 * subcnt)) != B_OK) return; - - /* issue fill command once... */ - nv_acc_cmd_dma(NV4_GDI_RECTANGLE_TEXT, NV4_GDI_RECTANGLE_TEXT_UCR0_LEFTTOP, (2 * subcnt)); - /* ... and send multiple rects (engine cmd supports 32 max) */ - while (subcnt--) - { - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = - (((list[i].left) << 16) | ((list[i].top) & 0x0000ffff)); /* Unclipped Rect 0 LeftTop */ - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = - (((((list[i].right)+1) - (list[i].left)) << 16) | - (((list[i].bottom-list[i].top)+1) & 0x0000ffff)); /* Unclipped Rect 0 WidthHeight */ - - i++; - } - - /* tell the engine to fetch the commands in the DMA buffer that where not - * executed before. */ - nv_start_dma(); - } - - /* tell 3D add-ons that they should reload their rendering states and surfaces */ - si->engine.threeD.reload = 0xffffffff; -} - -/* span fill - i.e. (selected) menuitem background color (Dano) */ -void FILL_SPAN_DMA(engine_token *et, uint32 colorIndex, uint16 *list, uint32 count) -{ - uint32 i = 0; - uint16 subcnt; - - /*** init acc engine for fill function ***/ - /* ROP registers (Raster OPeration): - * wait for room in fifo for ROP and bitmap cmd if needed. */ - if (nv_acc_fifofree_dma(4) != B_OK) return; - /* now setup ROP (writing 2 32bit words) for GXcopy */ - nv_acc_cmd_dma(NV_ROP5_SOLID, NV_ROP5_SOLID_SETROP5, 1); - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0xcc; /* SetRop5 */ - /* now setup fill color (writing 2 32bit words) */ - nv_acc_cmd_dma(NV4_GDI_RECTANGLE_TEXT, NV4_GDI_RECTANGLE_TEXT_COLOR1A, 1); - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = colorIndex; /* Color1A */ - - /*** draw each span ***/ - while (count) - { - /* break up the list in sublists to minimize calls, while making sure long - * lists still get executed without trouble */ - subcnt = 32; - if (count < 32) subcnt = count; - count -= subcnt; - - /* wait for room in fifo for bitmap cmd if needed. */ - if (nv_acc_fifofree_dma(1 + (2 * subcnt)) != B_OK) return; - - /* issue fill command once... */ - nv_acc_cmd_dma(NV4_GDI_RECTANGLE_TEXT, NV4_GDI_RECTANGLE_TEXT_UCR0_LEFTTOP, (2 * subcnt)); - /* ... and send multiple rects (spans) (engine cmd supports 32 max) */ - while (subcnt--) - { - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = - (((list[i+1]) << 16) | ((list[i]) & 0x0000ffff)); /* Unclipped Rect 0 LeftTop */ - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = - ((((list[i+2]+1) - (list[i+1])) << 16) | 0x00000001); /* Unclipped Rect 0 WidthHeight */ - - i+=3; - } - - /* tell the engine to fetch the commands in the DMA buffer that where not - * executed before. */ - nv_start_dma(); - } - - /* tell 3D add-ons that they should reload their rendering states and surfaces */ - si->engine.threeD.reload = 0xffffffff; -} - -/* rectangle invert - i.e. text cursor and text selection */ -void INVERT_RECTANGLE_DMA(engine_token *et, fill_rect_params *list, uint32 count) -{ - uint32 i = 0; - uint16 subcnt; - - /*** init acc engine for invert function ***/ - /* ROP registers (Raster OPeration): - * wait for room in fifo for ROP and bitmap cmd if needed. */ - if (nv_acc_fifofree_dma(4) != B_OK) return; - /* now setup ROP (writing 2 32bit words) for GXinvert */ - nv_acc_cmd_dma(NV_ROP5_SOLID, NV_ROP5_SOLID_SETROP5, 1); - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0x55; /* SetRop5 */ - /* now reset fill color (writing 2 32bit words) */ - nv_acc_cmd_dma(NV4_GDI_RECTANGLE_TEXT, NV4_GDI_RECTANGLE_TEXT_COLOR1A, 1); - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0x00000000; /* Color1A */ - - /*** invert each rectangle ***/ - while (count) - { - /* break up the list in sublists to minimize calls, while making sure long - * lists still get executed without trouble */ - subcnt = 32; - if (count < 32) subcnt = count; - count -= subcnt; - - /* wait for room in fifo for bitmap cmd if needed. */ - if (nv_acc_fifofree_dma(1 + (2 * subcnt)) != B_OK) return; - - /* issue fill command once... */ - nv_acc_cmd_dma(NV4_GDI_RECTANGLE_TEXT, NV4_GDI_RECTANGLE_TEXT_UCR0_LEFTTOP, (2 * subcnt)); - /* ... and send multiple rects (engine cmd supports 32 max) */ - while (subcnt--) - { - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = - (((list[i].left) << 16) | ((list[i].top) & 0x0000ffff)); /* Unclipped Rect 0 LeftTop */ - ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = - (((((list[i].right)+1) - (list[i].left)) << 16) | - (((list[i].bottom-list[i].top)+1) & 0x0000ffff)); /* Unclipped Rect 0 WidthHeight */ - - i++; - } - - /* tell the engine to fetch the commands in the DMA buffer that where not - * executed before. */ - nv_start_dma(); - } - - /* tell 3D add-ons that they should reload their rendering states and surfaces */ - si->engine.threeD.reload = 0xffffffff; -} diff --git a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_crtc.c b/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_crtc.c deleted file mode 100644 index 6f14818092..0000000000 --- a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_crtc.c +++ /dev/null @@ -1,826 +0,0 @@ -/* CTRC functionality */ -/* Author: - Rudolf Cornelissen 11/2002-6/2008 -*/ - -#define MODULE_BIT 0x00040000 - -#include "nv_std.h" - -/* - Enable/Disable interrupts. Just a wrapper around the - ioctl() to the kernel driver. -*/ -status_t nv_crtc_interrupt_enable(bool flag) -{ - status_t result = B_OK; - nv_set_vblank_int svi; - - if (si->ps.int_assigned) - { - /* set the magic number so the driver knows we're for real */ - svi.magic = NV_PRIVATE_DATA_MAGIC; - svi.crtc = 0; - svi.do_it = flag; - /* contact driver and get a pointer to the registers and shared data */ - result = ioctl(fd, NV_RUN_INTERRUPTS, &svi, sizeof(svi)); - } - - return result; -} - -status_t nv_crtc_update_fifo() -{ - return B_OK; -} - -/* Adjust passed parameters to a valid mode line */ -status_t nv_crtc_validate_timing( - uint16 *hd_e,uint16 *hs_s,uint16 *hs_e,uint16 *ht, - uint16 *vd_e,uint16 *vs_s,uint16 *vs_e,uint16 *vt -) -{ -/* horizontal */ - /* make all parameters multiples of 8 */ - *hd_e &= 0xfff8; - *hs_s &= 0xfff8; - *hs_e &= 0xfff8; - *ht &= 0xfff8; - - /* confine to required number of bits, taking logic into account */ - if (*hd_e > ((0x01ff - 2) << 3)) *hd_e = ((0x01ff - 2) << 3); - if (*hs_s > ((0x01ff - 1) << 3)) *hs_s = ((0x01ff - 1) << 3); - if (*hs_e > ( 0x01ff << 3)) *hs_e = ( 0x01ff << 3); - if (*ht > ((0x01ff + 5) << 3)) *ht = ((0x01ff + 5) << 3); - - /* NOTE: keep horizontal timing at multiples of 8! */ - /* confine to a reasonable width */ - if (*hd_e < 640) *hd_e = 640; - if (*hd_e > 2048) *hd_e = 2048; - - /* if hor. total does not leave room for a sensible sync pulse, increase it! */ - if (*ht < (*hd_e + 80)) *ht = (*hd_e + 80); - - /* if hor. total does not adhere to max. blanking pulse width, decrease it! */ - if (*ht > (*hd_e + 0x3f8)) *ht = (*hd_e + 0x3f8); - - /* make sure sync pulse is not during display */ - if (*hs_e > (*ht - 8)) *hs_e = (*ht - 8); - if (*hs_s < (*hd_e + 8)) *hs_s = (*hd_e + 8); - - /* correct sync pulse if it is too long: - * there are only 5 bits available to save this in the card registers! */ - if (*hs_e > (*hs_s + 0xf8)) *hs_e = (*hs_s + 0xf8); - -/*vertical*/ - /* confine to required number of bits, taking logic into account */ - //fixme if needed: on GeForce cards there are 12 instead of 11 bits... - if (*vd_e > (0x7ff - 2)) *vd_e = (0x7ff - 2); - if (*vs_s > (0x7ff - 1)) *vs_s = (0x7ff - 1); - if (*vs_e > 0x7ff ) *vs_e = 0x7ff ; - if (*vt > (0x7ff + 2)) *vt = (0x7ff + 2); - - /* confine to a reasonable height */ - if (*vd_e < 480) *vd_e = 480; - if (*vd_e > 1536) *vd_e = 1536; - - /*if vertical total does not leave room for a sync pulse, increase it!*/ - if (*vt < (*vd_e + 3)) *vt = (*vd_e + 3); - - /* if vert. total does not adhere to max. blanking pulse width, decrease it! */ - if (*vt > (*vd_e + 0xff)) *vt = (*vd_e + 0xff); - - /* make sure sync pulse is not during display */ - if (*vs_e > (*vt - 1)) *vs_e = (*vt - 1); - if (*vs_s < (*vd_e + 1)) *vs_s = (*vd_e + 1); - - /* correct sync pulse if it is too long: - * there are only 4 bits available to save this in the card registers! */ - if (*vs_e > (*vs_s + 0x0f)) *vs_e = (*vs_s + 0x0f); - - return B_OK; -} - -/*set a mode line - inputs are in pixels*/ -status_t nv_crtc_set_timing(display_mode target) -{ - uint8 temp; - - uint32 htotal; /*total horizontal total VCLKs*/ - uint32 hdisp_e; /*end of horizontal display (begins at 0)*/ - uint32 hsync_s; /*begin of horizontal sync pulse*/ - uint32 hsync_e; /*end of horizontal sync pulse*/ - uint32 hblnk_s; /*begin horizontal blanking*/ - uint32 hblnk_e; /*end horizontal blanking*/ - - uint32 vtotal; /*total vertical total scanlines*/ - uint32 vdisp_e; /*end of vertical display*/ - uint32 vsync_s; /*begin of vertical sync pulse*/ - uint32 vsync_e; /*end of vertical sync pulse*/ - uint32 vblnk_s; /*begin vertical blanking*/ - uint32 vblnk_e; /*end vertical blanking*/ - - uint32 linecomp; /*split screen and vdisp_e interrupt*/ - - LOG(4,("CRTC: setting timing\n")); - - /* setup tuned internal modeline for flatpanel if connected and active */ - /* notes: - * - the CRTC modeline must end earlier than the panel modeline to keep correct - * sync going; - * - if the CRTC modeline ends too soon, pixelnoise will occur in 8 (or so) pixel - * wide horizontal stripes. This can be observed earliest on fullscreen overlay, - * and if it gets worse, also normal desktop output will suffer. The stripes - * are mainly visible at the left of the screen, over the entire screen height. */ - if (si->ps.tmds1_active) - { - LOG(2,("CRTC: DFP active: tuning modeline\n")); - - /* horizontal timing */ - target.timing.h_sync_start = - ((uint16)((si->ps.p1_timing.h_sync_start / ((float)si->ps.p1_timing.h_display)) * - target.timing.h_display)) & 0xfff8; - - target.timing.h_sync_end = - ((uint16)((si->ps.p1_timing.h_sync_end / ((float)si->ps.p1_timing.h_display)) * - target.timing.h_display)) & 0xfff8; - - target.timing.h_total = - (((uint16)((si->ps.p1_timing.h_total / ((float)si->ps.p1_timing.h_display)) * - target.timing.h_display)) & 0xfff8) - 8; - - /* in native mode the CRTC needs some extra time to keep synced correctly; - * OTOH the overlay unit distorts if we reserve too much time! */ - if (target.timing.h_display == si->ps.p1_timing.h_display) - { - /* confirmed NV34 with 1680x1050 panel */ - target.timing.h_total -= 32; - } - - if (target.timing.h_sync_start == target.timing.h_display) - target.timing.h_sync_start += 8; - if (target.timing.h_sync_end == target.timing.h_total) - target.timing.h_sync_end -= 8; - - /* vertical timing */ - target.timing.v_sync_start = - ((uint16)((si->ps.p1_timing.v_sync_start / ((float)si->ps.p1_timing.v_display)) * - target.timing.v_display)); - - target.timing.v_sync_end = - ((uint16)((si->ps.p1_timing.v_sync_end / ((float)si->ps.p1_timing.v_display)) * - target.timing.v_display)); - - target.timing.v_total = - ((uint16)((si->ps.p1_timing.v_total / ((float)si->ps.p1_timing.v_display)) * - target.timing.v_display)) - 1; - - if (target.timing.v_sync_start == target.timing.v_display) - target.timing.v_sync_start += 1; - if (target.timing.v_sync_end == target.timing.v_total) - target.timing.v_sync_end -= 1; - - /* disable GPU scaling testmode so automatic scaling will be done */ - DACW(FP_DEBUG1, 0); - } - - /* Modify parameters as required by standard VGA */ - htotal = ((target.timing.h_total >> 3) - 5); - hdisp_e = ((target.timing.h_display >> 3) - 1); - hblnk_s = hdisp_e; - hblnk_e = (htotal + 4); - hsync_s = (target.timing.h_sync_start >> 3); - hsync_e = (target.timing.h_sync_end >> 3); - - vtotal = target.timing.v_total - 2; - vdisp_e = target.timing.v_display - 1; - vblnk_s = vdisp_e; - vblnk_e = (vtotal + 1); - vsync_s = target.timing.v_sync_start; - vsync_e = target.timing.v_sync_end; - - /* prevent memory adress counter from being reset (linecomp may not occur) */ - linecomp = target.timing.v_display; - - /* enable access to primary head */ - set_crtc_owner(0); - - /* Note for laptop and DVI flatpanels: - * CRTC timing has a seperate set of registers from flatpanel timing. - * The flatpanel timing registers have scaling registers that are used to match - * these two modelines. */ - { - LOG(4,("CRTC: Setting full timing...\n")); - - /* log the mode that will be set */ - LOG(2,("CRTC:\n\tHTOT:%x\n\tHDISPEND:%x\n\tHBLNKS:%x\n\tHBLNKE:%x\n\tHSYNCS:%x\n\tHSYNCE:%x\n\t",htotal,hdisp_e,hblnk_s,hblnk_e,hsync_s,hsync_e)); - LOG(2,("VTOT:%x\n\tVDISPEND:%x\n\tVBLNKS:%x\n\tVBLNKE:%x\n\tVSYNCS:%x\n\tVSYNCE:%x\n",vtotal,vdisp_e,vblnk_s,vblnk_e,vsync_s,vsync_e)); - - /* actually program the card! */ - /* unlock CRTC registers at index 0-7 */ - CRTCW(VSYNCE, (CRTCR(VSYNCE) & 0x7f)); - /* horizontal standard VGA regs */ - CRTCW(HTOTAL, (htotal & 0xff)); - CRTCW(HDISPE, (hdisp_e & 0xff)); - CRTCW(HBLANKS, (hblnk_s & 0xff)); - /* also unlock vertical retrace registers in advance */ - CRTCW(HBLANKE, ((hblnk_e & 0x1f) | 0x80)); - CRTCW(HSYNCS, (hsync_s & 0xff)); - CRTCW(HSYNCE, ((hsync_e & 0x1f) | ((hblnk_e & 0x20) << 2))); - - /* vertical standard VGA regs */ - CRTCW(VTOTAL, (vtotal & 0xff)); - CRTCW(OVERFLOW, - ( - ((vtotal & 0x100) >> (8 - 0)) | ((vtotal & 0x200) >> (9 - 5)) | - ((vdisp_e & 0x100) >> (8 - 1)) | ((vdisp_e & 0x200) >> (9 - 6)) | - ((vsync_s & 0x100) >> (8 - 2)) | ((vsync_s & 0x200) >> (9 - 7)) | - ((vblnk_s & 0x100) >> (8 - 3)) | ((linecomp & 0x100) >> (8 - 4)) - )); - CRTCW(PRROWSCN, 0x00); /* not used */ - CRTCW(MAXSCLIN, (((vblnk_s & 0x200) >> (9 - 5)) | ((linecomp & 0x200) >> (9 - 6)))); - CRTCW(VSYNCS, (vsync_s & 0xff)); - CRTCW(VSYNCE, ((CRTCR(VSYNCE) & 0xf0) | (vsync_e & 0x0f))); - CRTCW(VDISPE, (vdisp_e & 0xff)); - CRTCW(VBLANKS, (vblnk_s & 0xff)); - CRTCW(VBLANKE, (vblnk_e & 0xff)); - CRTCW(LINECOMP, (linecomp & 0xff)); - - /* horizontal extended regs */ - //fixme: we reset bit4. is this correct?? - CRTCW(HEB, (CRTCR(HEB) & 0xe0) | - ( - ((htotal & 0x100) >> (8 - 0)) | - ((hdisp_e & 0x100) >> (8 - 1)) | - ((hblnk_s & 0x100) >> (8 - 2)) | - ((hsync_s & 0x100) >> (8 - 3)) - )); - - /* (mostly) vertical extended regs */ - CRTCW(LSR, - ( - ((vtotal & 0x400) >> (10 - 0)) | - ((vdisp_e & 0x400) >> (10 - 1)) | - ((vsync_s & 0x400) >> (10 - 2)) | - ((vblnk_s & 0x400) >> (10 - 3)) | - ((hblnk_e & 0x040) >> (6 - 4)) - //fixme: we still miss one linecomp bit!?! is this it?? - //| ((linecomp & 0x400) >> 3) - )); - - /* more vertical extended regs */ - CRTCW(EXTRA, - ( - ((vtotal & 0x800) >> (11 - 0)) | - ((vdisp_e & 0x800) >> (11 - 2)) | - ((vsync_s & 0x800) >> (11 - 4)) | - ((vblnk_s & 0x800) >> (11 - 6)) - //fixme: do we miss another linecomp bit!?! - )); - - /* setup 'large screen' mode */ - if (target.timing.h_display >= 1280) - CRTCW(REPAINT1, (CRTCR(REPAINT1) & 0xfb)); - else - CRTCW(REPAINT1, (CRTCR(REPAINT1) | 0x04)); - - /* setup HSYNC & VSYNC polarity */ - LOG(2,("CRTC: sync polarity: ")); - temp = NV_REG8(NV8_MISCR); - if (target.timing.flags & B_POSITIVE_HSYNC) - { - LOG(2,("H:pos ")); - temp &= ~0x40; - } - else - { - LOG(2,("H:neg ")); - temp |= 0x40; - } - if (target.timing.flags & B_POSITIVE_VSYNC) - { - LOG(2,("V:pos ")); - temp &= ~0x80; - } - else - { - LOG(2,("V:neg ")); - temp |= 0x80; - } - NV_REG8(NV8_MISCW) = temp; - - LOG(2,(", MISC reg readback: $%02x\n", NV_REG8(NV8_MISCR))); - } - - /* always disable interlaced operation */ - /* (interlace is supported on upto and including NV10, NV15, and NV30 and up) */ - CRTCW(INTERLACE, 0xff); - - /* disable CRTC slaved mode unless a panel is in use */ - if (!si->ps.tmds1_active) CRTCW(PIXEL, (CRTCR(PIXEL) & 0x7f)); - - /* setup flatpanel if connected and active */ - if (si->ps.tmds1_active) - { - uint32 iscale_x, iscale_y; - - /* calculate inverse scaling factors used by hardware in 20.12 format */ - iscale_x = (((1 << 12) * target.timing.h_display) / si->ps.p1_timing.h_display); - iscale_y = (((1 << 12) * target.timing.v_display) / si->ps.p1_timing.v_display); - - /* unblock flatpanel timing programming (or something like that..) */ - CRTCW(FP_HTIMING, 0); - CRTCW(FP_VTIMING, 0); - LOG(2,("CRTC: FP_HTIMING reg readback: $%02x\n", CRTCR(FP_HTIMING))); - LOG(2,("CRTC: FP_VTIMING reg readback: $%02x\n", CRTCR(FP_VTIMING))); - - /* enable full width visibility on flatpanel */ - DACW(FP_HVALID_S, 0); - DACW(FP_HVALID_E, (si->ps.p1_timing.h_display - 1)); - /* enable full height visibility on flatpanel */ - DACW(FP_VVALID_S, 0); - DACW(FP_VVALID_E, (si->ps.p1_timing.v_display - 1)); - - /* nVidia cards support upscaling except on ??? */ - /* NV11 cards can upscale after all! */ - if (0)//si->ps.card_type == NV11) - { - /* disable last fetched line limiting */ - DACW(FP_DEBUG2, 0x00000000); - /* inform panel to scale if needed */ - if ((iscale_x != (1 << 12)) || (iscale_y != (1 << 12))) - { - LOG(2,("CRTC: DFP needs to do scaling\n")); - DACW(FP_TG_CTRL, (DACR(FP_TG_CTRL) | 0x00000100)); - } - else - { - LOG(2,("CRTC: no scaling for DFP needed\n")); - DACW(FP_TG_CTRL, (DACR(FP_TG_CTRL) & 0xfffffeff)); - } - } - else - { - float dm_aspect; - - LOG(2,("CRTC: GPU scales for DFP if needed\n")); - - /* calculate display mode aspect */ - dm_aspect = (target.timing.h_display / ((float)target.timing.v_display)); - - /* limit last fetched line if vertical scaling is done */ - if (iscale_y != (1 << 12)) - DACW(FP_DEBUG2, ((1 << 28) | ((target.timing.v_display - 1) << 16))); - else - DACW(FP_DEBUG2, 0x00000000); - - /* inform panel not to scale */ - DACW(FP_TG_CTRL, (DACR(FP_TG_CTRL) & 0xfffffeff)); - - /* GPU scaling is automatically setup by hardware, so only modify this - * scalingfactor for non 4:3 (1.33) aspect panels; - * let's consider 1280x1024 1:33 aspect (it's 1.25 aspect actually!) */ - - /* correct for widescreen panels relative to mode... - * (so if panel is more widescreen than mode being set) */ - /* BTW: known widescreen panels: - * 1280 x 800 (1.60), - * 1440 x 900 (1.60), - * 1680 x 1050 (1.60), - * 1920 x 1200 (1.60). */ - /* known 4:3 aspect non-standard resolution panels: - * 1400 x 1050 (1.33). */ - /* NOTE: - * allow 0.10 difference so 1280x1024 panels will be used fullscreen! */ - if ((iscale_x != (1 << 12)) && (si->ps.panel1_aspect > (dm_aspect + 0.10))) - { - uint16 diff; - - LOG(2,("CRTC: (relative) widescreen panel: tuning horizontal scaling\n")); - - /* X-scaling should be the same as Y-scaling */ - iscale_x = iscale_y; - /* enable testmode (b12) and program modified X-scaling factor */ - DACW(FP_DEBUG1, (((iscale_x >> 1) & 0x00000fff) | (1 << 12))); - /* center/cut-off left and right side of screen */ - diff = ((si->ps.p1_timing.h_display - - ((target.timing.h_display * (1 << 12)) / iscale_x)) - / 2); - DACW(FP_HVALID_S, diff); - DACW(FP_HVALID_E, ((si->ps.p1_timing.h_display - diff) - 1)); - } - /* correct for portrait panels... */ - /* NOTE: - * allow 0.10 difference so 1280x1024 panels will be used fullscreen! */ - if ((iscale_y != (1 << 12)) && (si->ps.panel1_aspect < (dm_aspect - 0.10))) - { - LOG(2,("CRTC: (relative) portrait panel: should tune vertical scaling\n")); - /* fixme: implement if this kind of portrait panels exist on nVidia... */ - } - } - - /* do some logging.. */ - LOG(2,("CRTC: FP_HVALID_S reg readback: $%08x\n", DACR(FP_HVALID_S))); - LOG(2,("CRTC: FP_HVALID_E reg readback: $%08x\n", DACR(FP_HVALID_E))); - LOG(2,("CRTC: FP_VVALID_S reg readback: $%08x\n", DACR(FP_VVALID_S))); - LOG(2,("CRTC: FP_VVALID_E reg readback: $%08x\n", DACR(FP_VVALID_E))); - LOG(2,("CRTC: FP_DEBUG0 reg readback: $%08x\n", DACR(FP_DEBUG0))); - LOG(2,("CRTC: FP_DEBUG1 reg readback: $%08x\n", DACR(FP_DEBUG1))); - LOG(2,("CRTC: FP_DEBUG2 reg readback: $%08x\n", DACR(FP_DEBUG2))); - LOG(2,("CRTC: FP_DEBUG3 reg readback: $%08x\n", DACR(FP_DEBUG3))); - LOG(2,("CRTC: FP_TG_CTRL reg readback: $%08x\n", DACR(FP_TG_CTRL))); - } - - return B_OK; -} - -status_t nv_crtc_depth(int mode) -{ - uint8 viddelay = 0; - uint32 genctrl = 0; - - /* set VCLK scaling */ - switch(mode) - { - case BPP8: - viddelay = 0x01; - /* genctrl b4 & b5 reset: 'direct mode' */ - genctrl = 0x00101100; - break; - case BPP15: - viddelay = 0x02; - /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ - genctrl = 0x00100130; - break; - case BPP16: - viddelay = 0x02; - /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ - genctrl = 0x00101130; - break; - case BPP24: - viddelay = 0x03; - /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ - genctrl = 0x00100130; - break; - case BPP32: - viddelay = 0x03; - /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ - genctrl = 0x00101130; - break; - } - /* enable access to primary head */ - set_crtc_owner(0); - - CRTCW(PIXEL, ((CRTCR(PIXEL) & 0xfc) | viddelay)); - DACW(GENCTRL, genctrl); - - return B_OK; -} - -status_t nv_crtc_dpms(bool display, bool h, bool v, bool do_panel) -{ - uint8 temp; - char msg[100]; - - sprintf(msg, "CRTC: setting DPMS: "); - - /* enable access to primary head */ - set_crtc_owner(0); - - /* start synchronous reset: required before turning screen off! */ - SEQW(RESET, 0x01); - - temp = SEQR(CLKMODE); - if (display) - { - /* turn screen on */ - SEQW(CLKMODE, (temp & ~0x20)); - - /* end synchronous reset because display should be enabled */ - SEQW(RESET, 0x03); - - if (do_panel && si->ps.tmds1_active) - { - if (!si->ps.laptop) - { - /* restore original panelsync and panel-enable */ - uint32 panelsync = 0x00000000; - if(si->ps.p1_timing.flags & B_POSITIVE_VSYNC) panelsync |= 0x00000001; - if(si->ps.p1_timing.flags & B_POSITIVE_HSYNC) panelsync |= 0x00000010; - /* display enable polarity (not an official flag) */ - if(si->ps.p1_timing.flags & B_BLANK_PEDESTAL) panelsync |= 0x10000000; - DACW(FP_TG_CTRL, ((DACR(FP_TG_CTRL) & 0xcfffffcc) | panelsync)); - - //fixme?: looks like we don't need this after all: - /* powerup both LVDS (laptop panellink) and TMDS (DVI panellink) - * internal transmitters... */ - /* note: - * the powerbits in this register are hardwired to the DVI connectors, - * instead of to the DACs! (confirmed NV34) */ - //fixme... - //DACW(FP_DEBUG0, (DACR(FP_DEBUG0) & 0xcfffffff)); - /* ... and powerup external TMDS transmitter if it exists */ - /* (confirmed OK on NV28 and NV34) */ - //CRTCW(0x59, (CRTCR(0x59) | 0x01)); - - sprintf(msg, "%s(panel-)", msg); - } - else - { - //fixme? linux only does this on dualhead cards... - //fixme: see if LVDS head can be determined with two panels there... - if (!si->ps.tmds2_active) - { - /* b2 = 0 = enable laptop panel backlight */ - /* note: this seems to be a write-only register. */ - NV_REG32(NV32_LVDS_PWR) = 0x00000003; - - sprintf(msg, "%s(panel-)", msg); - } - } - } - - sprintf(msg, "%sdisplay on, ", msg); - } - else - { - /* turn screen off */ - SEQW(CLKMODE, (temp | 0x20)); - - if (do_panel && si->ps.tmds1_active) - { - if (!si->ps.laptop) - { - /* shutoff panelsync and disable panel */ - DACW(FP_TG_CTRL, ((DACR(FP_TG_CTRL) & 0xcfffffcc) | 0x20000022)); - - //fixme?: looks like we don't need this after all: - /* powerdown both LVDS (laptop panellink) and TMDS (DVI panellink) - * internal transmitters... */ - /* note: - * the powerbits in this register are hardwired to the DVI connectors, - * instead of to the DACs! (confirmed NV34) */ - //fixme... - //DACW(FP_DEBUG0, (DACR(FP_DEBUG0) | 0x30000000)); - /* ... and powerdown external TMDS transmitter if it exists */ - /* (confirmed OK on NV28 and NV34) */ - //CRTCW(0x59, (CRTCR(0x59) & 0xfe)); - - sprintf(msg, "%s(panel-)", msg); - } - else - { - //fixme? linux only does this on dualhead cards... - //fixme: see if LVDS head can be determined with two panels there... - if (!si->ps.tmds2_active) - { - /* b2 = 1 = disable laptop panel backlight */ - /* note: this seems to be a write-only register. */ - NV_REG32(NV32_LVDS_PWR) = 0x00000007; - - sprintf(msg, "%s(panel-)", msg); - } - } - } - - sprintf(msg, "%sdisplay off, ", msg); - } - - if (h) - { - CRTCW(REPAINT1, (CRTCR(REPAINT1) & 0x7f)); - sprintf(msg, "%shsync enabled, ", msg); - } - else - { - CRTCW(REPAINT1, (CRTCR(REPAINT1) | 0x80)); - sprintf(msg, "%shsync disabled, ", msg); - } - if (v) - { - CRTCW(REPAINT1, (CRTCR(REPAINT1) & 0xbf)); - sprintf(msg, "%svsync enabled\n", msg); - } - else - { - CRTCW(REPAINT1, (CRTCR(REPAINT1) | 0x40)); - sprintf(msg, "%svsync disabled\n", msg); - } - - LOG(4, (msg)); - - return B_OK; -} - -status_t nv_crtc_set_display_pitch() -{ - uint32 offset; - - LOG(4,("CRTC: setting card pitch (offset between lines)\n")); - - /* figure out offset value hardware needs */ - offset = si->fbc.bytes_per_row / 8; - - LOG(2,("CRTC: offset register set to: $%04x\n", offset)); - - /* enable access to primary head */ - set_crtc_owner(0); - - /* program the card */ - CRTCW(PITCHL, (offset & 0x00ff)); - CRTCW(REPAINT0, ((CRTCR(REPAINT0) & 0x1f) | ((offset & 0x0700) >> 3))); - - return B_OK; -} - -status_t nv_crtc_set_display_start(uint32 startadd,uint8 bpp) -{ - uint32 timeout = 0; - - LOG(4,("CRTC: setting card RAM to be displayed bpp %d\n", bpp)); - - LOG(2,("CRTC: startadd: $%08x\n", startadd)); - LOG(2,("CRTC: frameRAM: $%08x\n", si->framebuffer)); - LOG(2,("CRTC: framebuffer: $%08x\n", si->fbc.frame_buffer)); - - /* we might have no retraces during setmode! */ - /* wait 25mS max. for retrace to occur (refresh > 40Hz) */ - while (((NV_REG32(NV32_RASTER) & 0x000007ff) < si->dm.timing.v_display) && - (timeout < (25000/10))) - { - /* don't snooze much longer or retrace might get missed! */ - snooze(10); - timeout++; - } - - /* enable access to primary head */ - set_crtc_owner(0); - - /* upto 4Gb RAM adressing: must be used on NV10 and later! */ - /* NOTE: - * While this register also exists on pre-NV10 cards, it will - * wrap-around at 16Mb boundaries!! */ - - /* 30bit adress in 32bit words */ - NV_REG32(NV32_NV10FBSTADD32) = (startadd & 0xfffffffc); - - /* set NV4/NV10 byte adress: (b0 - 1) */ - ATBW(HORPIXPAN, ((startadd & 0x00000003) << 1)); - - return B_OK; -} - -status_t nv_crtc_cursor_init() -{ - int i; - vuint32 * fb; - /* cursor bitmap will be stored at the start of the framebuffer */ - const uint32 curadd = 0; - - /* enable access to primary head */ - set_crtc_owner(0); - - /* set cursor bitmap adress ... */ - if (si->ps.laptop) - { - /* must be used this way on all 'Go' cards! */ - - /* cursorbitmap must start on 2Kbyte boundary: */ - /* set adress bit11-16, and set 'no doublescan' (registerbit 1 = 0) */ - CRTCW(CURCTL0, ((curadd & 0x0001f800) >> 9)); - /* set adress bit17-23, and set graphics mode cursor(?) (registerbit 7 = 1) */ - CRTCW(CURCTL1, (((curadd & 0x00fe0000) >> 17) | 0x80)); - /* set adress bit24-31 */ - CRTCW(CURCTL2, ((curadd & 0xff000000) >> 24)); - } - else - { - /* upto 4Gb RAM adressing: - * can be used on NV10 and later (except for 'Go' cards)! */ - /* NOTE: - * This register does not exist on pre-NV10 and 'Go' cards. */ - - /* cursorbitmap must still start on 2Kbyte boundary: */ - NV_REG32(NV32_NV10CURADD32) = (curadd & 0xfffff800); - } - - /* set cursor colour: not needed because of direct nature of cursor bitmap. */ - - /*clear cursor*/ - fb = (vuint32 *) si->framebuffer + curadd; - for (i=0;i<(2048/4);i++) - { - fb[i]=0; - } - - /* select 32x32 pixel, 16bit color cursorbitmap, no doublescan */ - NV_REG32(NV32_CURCONF) = 0x02000100; - - /* activate hardware-sync between cursor updates and vertical retrace */ - DACW(NV10_CURSYNC, (DACR(NV10_CURSYNC) | 0x02000000)); - - /* activate hardware cursor */ - nv_crtc_cursor_show(); - - return B_OK; -} - -status_t nv_crtc_cursor_show() -{ - LOG(4,("CRTC: enabling cursor\n")); - - /* enable access to CRTC1 on dualhead cards */ - set_crtc_owner(0); - - /* b0 = 1 enables cursor */ - CRTCW(CURCTL0, (CRTCR(CURCTL0) | 0x01)); - - /* workaround for hardware bug confirmed existing on NV43: - * Cursor visibility is not updated without a position update if its hardware - * retrace sync is enabled. */ - if (si->ps.card_arch == NV40A) DACW(CURPOS, (DACR(CURPOS))); - - return B_OK; -} - -status_t nv_crtc_cursor_hide() -{ - LOG(4,("CRTC: disabling cursor\n")); - - /* enable access to primary head */ - set_crtc_owner(0); - - /* b0 = 0 disables cursor */ - CRTCW(CURCTL0, (CRTCR(CURCTL0) & 0xfe)); - - /* workaround for hardware bug confirmed existing on NV43: - * Cursor visibility is not updated without a position update if its hardware - * retrace sync is enabled. */ - if (si->ps.card_arch == NV40A) DACW(CURPOS, (DACR(CURPOS))); - - return B_OK; -} - -/*set up cursor shape*/ -status_t nv_crtc_cursor_define(uint8* andMask,uint8* xorMask) -{ - int x, y; - uint8 b; - vuint16 *cursor; - uint16 pixel; - - /* get a pointer to the cursor */ - cursor = (vuint16*) si->framebuffer; - - /* draw the cursor */ - /* (Nvidia cards have a RGB15 direct color cursor bitmap, bit #16 is transparancy) */ - for (y = 0; y < 16; y++) - { - b = 0x80; - for (x = 0; x < 8; x++) - { - /* preset transparant */ - pixel = 0x0000; - /* set white if requested */ - if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff; - /* set black if requested */ - if ((!(*andMask & b)) && (*xorMask & b)) pixel = 0x8000; - /* set invert if requested */ - if ( (*andMask & b) && (*xorMask & b)) pixel = 0x7fff; - /* place the pixel in the bitmap */ - cursor[x + (y * 32)] = pixel; - b >>= 1; - } - xorMask++; - andMask++; - b = 0x80; - for (; x < 16; x++) - { - /* preset transparant */ - pixel = 0x0000; - /* set white if requested */ - if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff; - /* set black if requested */ - if ((!(*andMask & b)) && (*xorMask & b)) pixel = 0x8000; - /* set invert if requested */ - if ( (*andMask & b) && (*xorMask & b)) pixel = 0x7fff; - /* place the pixel in the bitmap */ - cursor[x + (y * 32)] = pixel; - b >>= 1; - } - xorMask++; - andMask++; - } - - return B_OK; -} - -/* position the cursor */ -status_t nv_crtc_cursor_position(uint16 x, uint16 y) -{ - /* the cursor position is updated during retrace by card hardware */ - /* update cursorposition */ - DACW(CURPOS, ((x & 0x0fff) | ((y & 0x0fff) << 16))); - - return B_OK; -} diff --git a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_crtc2.c b/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_crtc2.c deleted file mode 100644 index 92d2d1d388..0000000000 --- a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_crtc2.c +++ /dev/null @@ -1,825 +0,0 @@ -/* second CTRC functionality for GeForce cards */ -/* Author: - Rudolf Cornelissen 11/2002-6/2008 -*/ - -#define MODULE_BIT 0x00020000 - -#include "nv_std.h" - -/* - Enable/Disable interrupts. Just a wrapper around the - ioctl() to the kernel driver. -*/ -status_t nv_crtc2_interrupt_enable(bool flag) -{ - status_t result = B_OK; - nv_set_vblank_int svi; - - if (si->ps.int_assigned) - { - /* set the magic number so the driver knows we're for real */ - svi.magic = NV_PRIVATE_DATA_MAGIC; - svi.crtc = 1; - svi.do_it = flag; - /* contact driver and get a pointer to the registers and shared data */ - result = ioctl(fd, NV_RUN_INTERRUPTS, &svi, sizeof(svi)); - } - - return result; -} - -status_t nv_crtc2_update_fifo() -{ - return B_OK; -} - -/* Adjust passed parameters to a valid mode line */ -status_t nv_crtc2_validate_timing( - uint16 *hd_e,uint16 *hs_s,uint16 *hs_e,uint16 *ht, - uint16 *vd_e,uint16 *vs_s,uint16 *vs_e,uint16 *vt -) -{ -/* horizontal */ - /* make all parameters multiples of 8 */ - *hd_e &= 0xfff8; - *hs_s &= 0xfff8; - *hs_e &= 0xfff8; - *ht &= 0xfff8; - - /* confine to required number of bits, taking logic into account */ - if (*hd_e > ((0x01ff - 2) << 3)) *hd_e = ((0x01ff - 2) << 3); - if (*hs_s > ((0x01ff - 1) << 3)) *hs_s = ((0x01ff - 1) << 3); - if (*hs_e > ( 0x01ff << 3)) *hs_e = ( 0x01ff << 3); - if (*ht > ((0x01ff + 5) << 3)) *ht = ((0x01ff + 5) << 3); - - /* NOTE: keep horizontal timing at multiples of 8! */ - /* confine to a reasonable width */ - if (*hd_e < 640) *hd_e = 640; - if (*hd_e > 2048) *hd_e = 2048; - - /* if hor. total does not leave room for a sensible sync pulse, increase it! */ - if (*ht < (*hd_e + 80)) *ht = (*hd_e + 80); - - /* if hor. total does not adhere to max. blanking pulse width, decrease it! */ - if (*ht > (*hd_e + 0x3f8)) *ht = (*hd_e + 0x3f8); - - /* make sure sync pulse is not during display */ - if (*hs_e > (*ht - 8)) *hs_e = (*ht - 8); - if (*hs_s < (*hd_e + 8)) *hs_s = (*hd_e + 8); - - /* correct sync pulse if it is too long: - * there are only 5 bits available to save this in the card registers! */ - if (*hs_e > (*hs_s + 0xf8)) *hs_e = (*hs_s + 0xf8); - -/*vertical*/ - /* confine to required number of bits, taking logic into account */ - //fixme if needed: on GeForce cards there are 12 instead of 11 bits... - if (*vd_e > (0x7ff - 2)) *vd_e = (0x7ff - 2); - if (*vs_s > (0x7ff - 1)) *vs_s = (0x7ff - 1); - if (*vs_e > 0x7ff ) *vs_e = 0x7ff ; - if (*vt > (0x7ff + 2)) *vt = (0x7ff + 2); - - /* confine to a reasonable height */ - if (*vd_e < 480) *vd_e = 480; - if (*vd_e > 1536) *vd_e = 1536; - - /*if vertical total does not leave room for a sync pulse, increase it!*/ - if (*vt < (*vd_e + 3)) *vt = (*vd_e + 3); - - /* if vert. total does not adhere to max. blanking pulse width, decrease it! */ - if (*vt > (*vd_e + 0xff)) *vt = (*vd_e + 0xff); - - /* make sure sync pulse is not during display */ - if (*vs_e > (*vt - 1)) *vs_e = (*vt - 1); - if (*vs_s < (*vd_e + 1)) *vs_s = (*vd_e + 1); - - /* correct sync pulse if it is too long: - * there are only 4 bits available to save this in the card registers! */ - if (*vs_e > (*vs_s + 0x0f)) *vs_e = (*vs_s + 0x0f); - - return B_OK; -} - -/*set a mode line - inputs are in pixels*/ -status_t nv_crtc2_set_timing(display_mode target) -{ - uint8 temp; - - uint32 htotal; /*total horizontal total VCLKs*/ - uint32 hdisp_e; /*end of horizontal display (begins at 0)*/ - uint32 hsync_s; /*begin of horizontal sync pulse*/ - uint32 hsync_e; /*end of horizontal sync pulse*/ - uint32 hblnk_s; /*begin horizontal blanking*/ - uint32 hblnk_e; /*end horizontal blanking*/ - - uint32 vtotal; /*total vertical total scanlines*/ - uint32 vdisp_e; /*end of vertical display*/ - uint32 vsync_s; /*begin of vertical sync pulse*/ - uint32 vsync_e; /*end of vertical sync pulse*/ - uint32 vblnk_s; /*begin vertical blanking*/ - uint32 vblnk_e; /*end vertical blanking*/ - - uint32 linecomp; /*split screen and vdisp_e interrupt*/ - - LOG(4,("CRTC2: setting timing\n")); - - /* setup tuned internal modeline for flatpanel if connected and active */ - /* notes: - * - the CRTC modeline must end earlier than the panel modeline to keep correct - * sync going; - * - if the CRTC modeline ends too soon, pixelnoise will occur in 8 (or so) pixel - * wide horizontal stripes. This can be observed earliest on fullscreen overlay, - * and if it gets worse, also normal desktop output will suffer. The stripes - * are mainly visible at the left of the screen, over the entire screen height. */ - if (si->ps.tmds2_active) - { - LOG(2,("CRTC2: DFP active: tuning modeline\n")); - - /* horizontal timing */ - target.timing.h_sync_start = - ((uint16)((si->ps.p2_timing.h_sync_start / ((float)si->ps.p2_timing.h_display)) * - target.timing.h_display)) & 0xfff8; - - target.timing.h_sync_end = - ((uint16)((si->ps.p2_timing.h_sync_end / ((float)si->ps.p2_timing.h_display)) * - target.timing.h_display)) & 0xfff8; - - target.timing.h_total = - (((uint16)((si->ps.p2_timing.h_total / ((float)si->ps.p2_timing.h_display)) * - target.timing.h_display)) & 0xfff8) - 8; - - /* in native mode the CRTC needs some extra time to keep synced correctly; - * OTOH the overlay unit distorts if we reserve too much time! */ - if (target.timing.h_display == si->ps.p2_timing.h_display) - { - /* confirmed NV34 with 1680x1050 panel */ - target.timing.h_total -= 32; - } - - if (target.timing.h_sync_start == target.timing.h_display) - target.timing.h_sync_start += 8; - if (target.timing.h_sync_end == target.timing.h_total) - target.timing.h_sync_end -= 8; - - /* vertical timing */ - target.timing.v_sync_start = - ((uint16)((si->ps.p2_timing.v_sync_start / ((float)si->ps.p2_timing.v_display)) * - target.timing.v_display)); - - target.timing.v_sync_end = - ((uint16)((si->ps.p2_timing.v_sync_end / ((float)si->ps.p2_timing.v_display)) * - target.timing.v_display)); - - target.timing.v_total = - ((uint16)((si->ps.p2_timing.v_total / ((float)si->ps.p2_timing.v_display)) * - target.timing.v_display)) - 1; - - if (target.timing.v_sync_start == target.timing.v_display) - target.timing.v_sync_start += 1; - if (target.timing.v_sync_end == target.timing.v_total) - target.timing.v_sync_end -= 1; - - /* disable GPU scaling testmode so automatic scaling will be done */ - DAC2W(FP_DEBUG1, 0); - } - - /* Modify parameters as required by standard VGA */ - htotal = ((target.timing.h_total >> 3) - 5); - hdisp_e = ((target.timing.h_display >> 3) - 1); - hblnk_s = hdisp_e; - hblnk_e = (htotal + 4); - hsync_s = (target.timing.h_sync_start >> 3); - hsync_e = (target.timing.h_sync_end >> 3); - - vtotal = target.timing.v_total - 2; - vdisp_e = target.timing.v_display - 1; - vblnk_s = vdisp_e; - vblnk_e = (vtotal + 1); - vsync_s = target.timing.v_sync_start; - vsync_e = target.timing.v_sync_end; - - /* prevent memory adress counter from being reset (linecomp may not occur) */ - linecomp = target.timing.v_display; - - /* enable access to secondary head */ - set_crtc_owner(1); - - /* Note for laptop and DVI flatpanels: - * CRTC timing has a seperate set of registers from flatpanel timing. - * The flatpanel timing registers have scaling registers that are used to match - * these two modelines. */ - { - LOG(4,("CRTC2: Setting full timing...\n")); - - /* log the mode that will be set */ - LOG(2,("CRTC2:\n\tHTOT:%x\n\tHDISPEND:%x\n\tHBLNKS:%x\n\tHBLNKE:%x\n\tHSYNCS:%x\n\tHSYNCE:%x\n\t",htotal,hdisp_e,hblnk_s,hblnk_e,hsync_s,hsync_e)); - LOG(2,("VTOT:%x\n\tVDISPEND:%x\n\tVBLNKS:%x\n\tVBLNKE:%x\n\tVSYNCS:%x\n\tVSYNCE:%x\n",vtotal,vdisp_e,vblnk_s,vblnk_e,vsync_s,vsync_e)); - - /* actually program the card! */ - /* unlock CRTC registers at index 0-7 */ - CRTC2W(VSYNCE, (CRTC2R(VSYNCE) & 0x7f)); - /* horizontal standard VGA regs */ - CRTC2W(HTOTAL, (htotal & 0xff)); - CRTC2W(HDISPE, (hdisp_e & 0xff)); - CRTC2W(HBLANKS, (hblnk_s & 0xff)); - /* also unlock vertical retrace registers in advance */ - CRTC2W(HBLANKE, ((hblnk_e & 0x1f) | 0x80)); - CRTC2W(HSYNCS, (hsync_s & 0xff)); - CRTC2W(HSYNCE, ((hsync_e & 0x1f) | ((hblnk_e & 0x20) << 2))); - - /* vertical standard VGA regs */ - CRTC2W(VTOTAL, (vtotal & 0xff)); - CRTC2W(OVERFLOW, - ( - ((vtotal & 0x100) >> (8 - 0)) | ((vtotal & 0x200) >> (9 - 5)) | - ((vdisp_e & 0x100) >> (8 - 1)) | ((vdisp_e & 0x200) >> (9 - 6)) | - ((vsync_s & 0x100) >> (8 - 2)) | ((vsync_s & 0x200) >> (9 - 7)) | - ((vblnk_s & 0x100) >> (8 - 3)) | ((linecomp & 0x100) >> (8 - 4)) - )); - CRTC2W(PRROWSCN, 0x00); /* not used */ - CRTC2W(MAXSCLIN, (((vblnk_s & 0x200) >> (9 - 5)) | ((linecomp & 0x200) >> (9 - 6)))); - CRTC2W(VSYNCS, (vsync_s & 0xff)); - CRTC2W(VSYNCE, ((CRTC2R(VSYNCE) & 0xf0) | (vsync_e & 0x0f))); - CRTC2W(VDISPE, (vdisp_e & 0xff)); - CRTC2W(VBLANKS, (vblnk_s & 0xff)); - CRTC2W(VBLANKE, (vblnk_e & 0xff)); - CRTC2W(LINECOMP, (linecomp & 0xff)); - - /* horizontal extended regs */ - //fixme: we reset bit4. is this correct?? - CRTC2W(HEB, (CRTC2R(HEB) & 0xe0) | - ( - ((htotal & 0x100) >> (8 - 0)) | - ((hdisp_e & 0x100) >> (8 - 1)) | - ((hblnk_s & 0x100) >> (8 - 2)) | - ((hsync_s & 0x100) >> (8 - 3)) - )); - - /* (mostly) vertical extended regs */ - CRTC2W(LSR, - ( - ((vtotal & 0x400) >> (10 - 0)) | - ((vdisp_e & 0x400) >> (10 - 1)) | - ((vsync_s & 0x400) >> (10 - 2)) | - ((vblnk_s & 0x400) >> (10 - 3)) | - ((hblnk_e & 0x040) >> (6 - 4)) - //fixme: we still miss one linecomp bit!?! is this it?? - //| ((linecomp & 0x400) >> 3) - )); - - /* more vertical extended regs */ - CRTC2W(EXTRA, - ( - ((vtotal & 0x800) >> (11 - 0)) | - ((vdisp_e & 0x800) >> (11 - 2)) | - ((vsync_s & 0x800) >> (11 - 4)) | - ((vblnk_s & 0x800) >> (11 - 6)) - //fixme: do we miss another linecomp bit!?! - )); - - /* setup 'large screen' mode */ - if (target.timing.h_display >= 1280) - CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0xfb)); - else - CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x04)); - - /* setup HSYNC & VSYNC polarity */ - LOG(2,("CRTC2: sync polarity: ")); - temp = NV_REG8(NV8_MISCR); - if (target.timing.flags & B_POSITIVE_HSYNC) - { - LOG(2,("H:pos ")); - temp &= ~0x40; - } - else - { - LOG(2,("H:neg ")); - temp |= 0x40; - } - if (target.timing.flags & B_POSITIVE_VSYNC) - { - LOG(2,("V:pos ")); - temp &= ~0x80; - } - else - { - LOG(2,("V:neg ")); - temp |= 0x80; - } - NV_REG8(NV8_MISCW) = temp; - - LOG(2,(", MISC reg readback: $%02x\n", NV_REG8(NV8_MISCR))); - } - - /* always disable interlaced operation */ - /* (interlace is supported on upto and including NV10, NV15, and NV30 and up) */ - CRTC2W(INTERLACE, 0xff); - - /* disable CRTC slaved mode unless a panel is in use */ - if (!si->ps.tmds2_active) CRTC2W(PIXEL, (CRTC2R(PIXEL) & 0x7f)); - - /* setup flatpanel if connected and active */ - if (si->ps.tmds2_active) - { - uint32 iscale_x, iscale_y; - - /* calculate inverse scaling factors used by hardware in 20.12 format */ - iscale_x = (((1 << 12) * target.timing.h_display) / si->ps.p2_timing.h_display); - iscale_y = (((1 << 12) * target.timing.v_display) / si->ps.p2_timing.v_display); - - /* unblock flatpanel timing programming (or something like that..) */ - CRTC2W(FP_HTIMING, 0); - CRTC2W(FP_VTIMING, 0); - LOG(2,("CRTC2: FP_HTIMING reg readback: $%02x\n", CRTC2R(FP_HTIMING))); - LOG(2,("CRTC2: FP_VTIMING reg readback: $%02x\n", CRTC2R(FP_VTIMING))); - - /* enable full width visibility on flatpanel */ - DAC2W(FP_HVALID_S, 0); - DAC2W(FP_HVALID_E, (si->ps.p2_timing.h_display - 1)); - /* enable full height visibility on flatpanel */ - DAC2W(FP_VVALID_S, 0); - DAC2W(FP_VVALID_E, (si->ps.p2_timing.v_display - 1)); - - /* nVidia cards support upscaling except on ??? */ - /* NV11 cards can upscale after all! */ - if (0)//si->ps.card_type == NV11) - { - /* disable last fetched line limiting */ - DAC2W(FP_DEBUG2, 0x00000000); - /* inform panel to scale if needed */ - if ((iscale_x != (1 << 12)) || (iscale_y != (1 << 12))) - { - LOG(2,("CRTC2: DFP needs to do scaling\n")); - DAC2W(FP_TG_CTRL, (DAC2R(FP_TG_CTRL) | 0x00000100)); - } - else - { - LOG(2,("CRTC2: no scaling for DFP needed\n")); - DAC2W(FP_TG_CTRL, (DAC2R(FP_TG_CTRL) & 0xfffffeff)); - } - } - else - { - float dm_aspect; - - LOG(2,("CRTC2: GPU scales for DFP if needed\n")); - - /* calculate display mode aspect */ - dm_aspect = (target.timing.h_display / ((float)target.timing.v_display)); - - /* limit last fetched line if vertical scaling is done */ - if (iscale_y != (1 << 12)) - DAC2W(FP_DEBUG2, ((1 << 28) | ((target.timing.v_display - 1) << 16))); - else - DAC2W(FP_DEBUG2, 0x00000000); - - /* inform panel not to scale */ - DAC2W(FP_TG_CTRL, (DAC2R(FP_TG_CTRL) & 0xfffffeff)); - - /* GPU scaling is automatically setup by hardware, so only modify this - * scalingfactor for non 4:3 (1.33) aspect panels; - * let's consider 1280x1024 1:33 aspect (it's 1.25 aspect actually!) */ - - /* correct for widescreen panels relative to mode... - * (so if panel is more widescreen than mode being set) */ - /* BTW: known widescreen panels: - * 1280 x 800 (1.60), - * 1440 x 900 (1.60), - * 1680 x 1050 (1.60), - * 1920 x 1200 (1.60). */ - /* known 4:3 aspect non-standard resolution panels: - * 1400 x 1050 (1.33). */ - /* NOTE: - * allow 0.10 difference so 1280x1024 panels will be used fullscreen! */ - if ((iscale_x != (1 << 12)) && (si->ps.panel2_aspect > (dm_aspect + 0.10))) - { - uint16 diff; - - LOG(2,("CRTC2: (relative) widescreen panel: tuning horizontal scaling\n")); - - /* X-scaling should be the same as Y-scaling */ - iscale_x = iscale_y; - /* enable testmode (b12) and program new X-scaling factor */ - DAC2W(FP_DEBUG1, (((iscale_x >> 1) & 0x00000fff) | (1 << 12))); - /* center/cut-off left and right side of screen */ - diff = ((si->ps.p2_timing.h_display - - ((target.timing.h_display * (1 << 12)) / iscale_x)) - / 2); - DAC2W(FP_HVALID_S, diff); - DAC2W(FP_HVALID_E, ((si->ps.p2_timing.h_display - diff) - 1)); - } - /* correct for portrait panels... */ - /* NOTE: - * allow 0.10 difference so 1280x1024 panels will be used fullscreen! */ - if ((iscale_y != (1 << 12)) && (si->ps.panel2_aspect < (dm_aspect - 0.10))) - { - LOG(2,("CRTC2: (relative) portrait panel: should tune vertical scaling\n")); - /* fixme: implement if this kind of portrait panels exist on nVidia... */ - } - } - - /* do some logging.. */ - LOG(2,("CRTC2: FP_HVALID_S reg readback: $%08x\n", DAC2R(FP_HVALID_S))); - LOG(2,("CRTC2: FP_HVALID_E reg readback: $%08x\n", DAC2R(FP_HVALID_E))); - LOG(2,("CRTC2: FP_VVALID_S reg readback: $%08x\n", DAC2R(FP_VVALID_S))); - LOG(2,("CRTC2: FP_VVALID_E reg readback: $%08x\n", DAC2R(FP_VVALID_E))); - LOG(2,("CRTC2: FP_DEBUG0 reg readback: $%08x\n", DAC2R(FP_DEBUG0))); - LOG(2,("CRTC2: FP_DEBUG1 reg readback: $%08x\n", DAC2R(FP_DEBUG1))); - LOG(2,("CRTC2: FP_DEBUG2 reg readback: $%08x\n", DAC2R(FP_DEBUG2))); - LOG(2,("CRTC2: FP_DEBUG3 reg readback: $%08x\n", DAC2R(FP_DEBUG3))); - LOG(2,("CRTC2: FP_TG_CTRL reg readback: $%08x\n", DAC2R(FP_TG_CTRL))); - } - - return B_OK; -} - -status_t nv_crtc2_depth(int mode) -{ - uint8 viddelay = 0; - uint32 genctrl = 0; - - /* set VCLK scaling */ - switch(mode) - { - case BPP8: - viddelay = 0x01; - /* genctrl b4 & b5 reset: 'direct mode' */ - genctrl = 0x00101100; - break; - case BPP15: - viddelay = 0x02; - /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ - genctrl = 0x00100130; - break; - case BPP16: - viddelay = 0x02; - /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ - genctrl = 0x00101130; - break; - case BPP24: - viddelay = 0x03; - /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ - genctrl = 0x00100130; - break; - case BPP32: - viddelay = 0x03; - /* genctrl b4 & b5 set: 'indirect mode' (via colorpalette) */ - genctrl = 0x00101130; - break; - } - /* enable access to secondary head */ - set_crtc_owner(1); - - CRTC2W(PIXEL, ((CRTC2R(PIXEL) & 0xfc) | viddelay)); - DAC2W(GENCTRL, genctrl); - - return B_OK; -} - -status_t nv_crtc2_dpms(bool display, bool h, bool v, bool do_panel) -{ - uint8 temp; - char msg[100]; - - sprintf(msg, "CRTC2: setting DPMS: "); - - /* enable access to secondary head */ - set_crtc_owner(1); - - /* start synchronous reset: required before turning screen off! */ - SEQW(RESET, 0x01); - - temp = SEQR(CLKMODE); - if (display) - { - /* turn screen on */ - SEQW(CLKMODE, (temp & ~0x20)); - - /* end synchronous reset because display should be enabled */ - SEQW(RESET, 0x03); - - if (do_panel && si->ps.tmds2_active) - { - if (!si->ps.laptop) - { - /* restore original panelsync and panel-enable */ - uint32 panelsync = 0x00000000; - if(si->ps.p2_timing.flags & B_POSITIVE_VSYNC) panelsync |= 0x00000001; - if(si->ps.p2_timing.flags & B_POSITIVE_HSYNC) panelsync |= 0x00000010; - /* display enable polarity (not an official flag) */ - if(si->ps.p2_timing.flags & B_BLANK_PEDESTAL) panelsync |= 0x10000000; - DAC2W(FP_TG_CTRL, ((DAC2R(FP_TG_CTRL) & 0xcfffffcc) | panelsync)); - - //fixme?: looks like we don't need this after all: - /* powerup both LVDS (laptop panellink) and TMDS (DVI panellink) - * internal transmitters... */ - /* note: - * the powerbits in this register are hardwired to the DVI connectors, - * instead of to the DACs! (confirmed NV34) */ - //fixme... - //DAC2W(FP_DEBUG0, (DAC2R(FP_DEBUG0) & 0xcfffffff)); - /* ... and powerup external TMDS transmitter if it exists */ - /* (confirmed OK on NV28 and NV34) */ - //CRTC2W(0x59, (CRTC2R(0x59) | 0x01)); - - sprintf(msg, "%s(panel-)", msg); - } - else - { - //fixme: see if LVDS head can be determined with two panels there... - if (!si->ps.tmds1_active) - { - /* b2 = 0 = enable laptop panel backlight */ - /* note: this seems to be a write-only register. */ - NV_REG32(NV32_LVDS_PWR) = 0x00000003; - - sprintf(msg, "%s(panel-)", msg); - } - } - } - - sprintf(msg, "%sdisplay on, ", msg); - } - else - { - /* turn screen off */ - SEQW(CLKMODE, (temp | 0x20)); - - if (do_panel && si->ps.tmds2_active) - { - if (!si->ps.laptop) - { - /* shutoff panelsync and disable panel */ - DAC2W(FP_TG_CTRL, ((DAC2R(FP_TG_CTRL) & 0xcfffffcc) | 0x20000022)); - - //fixme?: looks like we don't need this after all: - /* powerdown both LVDS (laptop panellink) and TMDS (DVI panellink) - * internal transmitters... */ - /* note: - * the powerbits in this register are hardwired to the DVI connectors, - * instead of to the DACs! (confirmed NV34) */ - //fixme... - //DAC2W(FP_DEBUG0, (DAC2R(FP_DEBUG0) | 0x30000000)); - /* ... and powerdown external TMDS transmitter if it exists */ - /* (confirmed OK on NV28 and NV34) */ - //CRTC2W(0x59, (CRTC2R(0x59) & 0xfe)); - - sprintf(msg, "%s(panel-)", msg); - } - else - { - //fixme: see if LVDS head can be determined with two panels there... - if (!si->ps.tmds1_active) - { - /* b2 = 1 = disable laptop panel backlight */ - /* note: this seems to be a write-only register. */ - NV_REG32(NV32_LVDS_PWR) = 0x00000007; - - sprintf(msg, "%s(panel-)", msg); - } - } - } - - sprintf(msg, "%sdisplay off, ", msg); - } - - if (h) - { - CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0x7f)); - sprintf(msg, "%shsync enabled, ", msg); - } - else - { - CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x80)); - sprintf(msg, "%shsync disabled, ", msg); - } - if (v) - { - CRTC2W(REPAINT1, (CRTC2R(REPAINT1) & 0xbf)); - sprintf(msg, "%svsync enabled\n", msg); - } - else - { - CRTC2W(REPAINT1, (CRTC2R(REPAINT1) | 0x40)); - sprintf(msg, "%svsync disabled\n", msg); - } - - LOG(4, (msg)); - - return B_OK; -} - -status_t nv_crtc2_set_display_pitch() -{ - uint32 offset; - - LOG(4,("CRTC2: setting card pitch (offset between lines)\n")); - - /* figure out offset value hardware needs */ - offset = si->fbc.bytes_per_row / 8; - - LOG(2,("CRTC2: offset register set to: $%04x\n", offset)); - - /* enable access to secondary head */ - set_crtc_owner(1); - - /* program the card */ - CRTC2W(PITCHL, (offset & 0x00ff)); - CRTC2W(REPAINT0, ((CRTC2R(REPAINT0) & 0x1f) | ((offset & 0x0700) >> 3))); - - return B_OK; -} - -status_t nv_crtc2_set_display_start(uint32 startadd,uint8 bpp) -{ - uint32 timeout = 0; - - LOG(4,("CRTC2: setting card RAM to be displayed bpp %d\n", bpp)); - - LOG(2,("CRTC2: startadd: $%08x\n", startadd)); - LOG(2,("CRTC2: frameRAM: $%08x\n", si->framebuffer)); - LOG(2,("CRTC2: framebuffer: $%08x\n", si->fbc.frame_buffer)); - - /* we might have no retraces during setmode! */ - /* wait 25mS max. for retrace to occur (refresh > 40Hz) */ - while (((NV_REG32(NV32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) && - (timeout < (25000/10))) - { - /* don't snooze much longer or retrace might get missed! */ - snooze(10); - timeout++; - } - - /* enable access to secondary head */ - set_crtc_owner(1); - - /* upto 4Gb RAM adressing: must be used on NV10 and later! */ - /* NOTE: - * While this register also exists on pre-NV10 cards, it will - * wrap-around at 16Mb boundaries!! */ - - /* 30bit adress in 32bit words */ - NV_REG32(NV32_NV10FB2STADD32) = (startadd & 0xfffffffc); - - /* set byte adress: (b0 - 1) */ - ATB2W(HORPIXPAN, ((startadd & 0x00000003) << 1)); - - return B_OK; -} - -status_t nv_crtc2_cursor_init() -{ - int i; - vuint32 * fb; - /* cursor bitmap will be stored at the start of the framebuffer */ - const uint32 curadd = 0; - - /* enable access to secondary head */ - set_crtc_owner(1); - - /* set cursor bitmap adress ... */ - if (si->ps.laptop) - { - /* must be used this way on pre-NV10 and on all 'Go' cards! */ - - /* cursorbitmap must start on 2Kbyte boundary: */ - /* set adress bit11-16, and set 'no doublescan' (registerbit 1 = 0) */ - CRTC2W(CURCTL0, ((curadd & 0x0001f800) >> 9)); - /* set adress bit17-23, and set graphics mode cursor(?) (registerbit 7 = 1) */ - CRTC2W(CURCTL1, (((curadd & 0x00fe0000) >> 17) | 0x80)); - /* set adress bit24-31 */ - CRTC2W(CURCTL2, ((curadd & 0xff000000) >> 24)); - } - else - { - /* upto 4Gb RAM adressing: - * can be used on NV10 and later (except for 'Go' cards)! */ - /* NOTE: - * This register does not exist on pre-NV10 and 'Go' cards. */ - - /* cursorbitmap must still start on 2Kbyte boundary: */ - NV_REG32(NV32_NV10CUR2ADD32) = (curadd & 0xfffff800); - } - - /* set cursor colour: not needed because of direct nature of cursor bitmap. */ - - /*clear cursor*/ - fb = (vuint32 *) si->framebuffer + curadd; - for (i=0;i<(2048/4);i++) - { - fb[i]=0; - } - - /* select 32x32 pixel, 16bit color cursorbitmap, no doublescan */ - NV_REG32(NV32_2CURCONF) = 0x02000100; - - /* activate hardware-sync between cursor updates and vertical retrace */ - DAC2W(NV10_CURSYNC, (DAC2R(NV10_CURSYNC) | 0x02000000)); - - /* activate hardware cursor */ - nv_crtc2_cursor_show(); - - return B_OK; -} - -status_t nv_crtc2_cursor_show() -{ - LOG(4,("CRTC2: enabling cursor\n")); - - /* enable access to secondary head */ - set_crtc_owner(1); - - /* b0 = 1 enables cursor */ - CRTC2W(CURCTL0, (CRTC2R(CURCTL0) | 0x01)); - - /* workaround for hardware bug confirmed existing on NV43: - * Cursor visibility is not updated without a position update if its hardware - * retrace sync is enabled. */ - if (si->ps.card_arch == NV40A) DAC2W(CURPOS, (DAC2R(CURPOS))); - - return B_OK; -} - -status_t nv_crtc2_cursor_hide() -{ - LOG(4,("CRTC2: disabling cursor\n")); - - /* enable access to secondary head */ - set_crtc_owner(1); - - /* b0 = 0 disables cursor */ - CRTC2W(CURCTL0, (CRTC2R(CURCTL0) & 0xfe)); - - /* workaround for hardware bug confirmed existing on NV43: - * Cursor visibility is not updated without a position update if its hardware - * retrace sync is enabled. */ - if (si->ps.card_arch == NV40A) DAC2W(CURPOS, (DAC2R(CURPOS))); - - return B_OK; -} - -/*set up cursor shape*/ -status_t nv_crtc2_cursor_define(uint8* andMask,uint8* xorMask) -{ - int x, y; - uint8 b; - vuint16 *cursor; - uint16 pixel; - - /* get a pointer to the cursor */ - cursor = (vuint16*) si->framebuffer; - - /* draw the cursor */ - /* (Nvidia cards have a RGB15 direct color cursor bitmap, bit #16 is transparancy) */ - for (y = 0; y < 16; y++) - { - b = 0x80; - for (x = 0; x < 8; x++) - { - /* preset transparant */ - pixel = 0x0000; - /* set white if requested */ - if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff; - /* set black if requested */ - if ((!(*andMask & b)) && (*xorMask & b)) pixel = 0x8000; - /* set invert if requested */ - if ( (*andMask & b) && (*xorMask & b)) pixel = 0x7fff; - /* place the pixel in the bitmap */ - cursor[x + (y * 32)] = pixel; - b >>= 1; - } - xorMask++; - andMask++; - b = 0x80; - for (; x < 16; x++) - { - /* preset transparant */ - pixel = 0x0000; - /* set white if requested */ - if ((!(*andMask & b)) && (!(*xorMask & b))) pixel = 0xffff; - /* set black if requested */ - if ((!(*andMask & b)) && (*xorMask & b)) pixel = 0x8000; - /* set invert if requested */ - if ( (*andMask & b) && (*xorMask & b)) pixel = 0x7fff; - /* place the pixel in the bitmap */ - cursor[x + (y * 32)] = pixel; - b >>= 1; - } - xorMask++; - andMask++; - } - - return B_OK; -} - -/* position the cursor */ -status_t nv_crtc2_cursor_position(uint16 x, uint16 y) -{ - /* the cursor position is updated during retrace by card hardware */ - - /* update cursorposition */ - DAC2W(CURPOS, ((x & 0x0fff) | ((y & 0x0fff) << 16))); - - return B_OK; -} diff --git a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_dac.c b/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_dac.c deleted file mode 100644 index 277553c9f8..0000000000 --- a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_dac.c +++ /dev/null @@ -1,527 +0,0 @@ -/* program the DAC */ -/* Author: - Rudolf Cornelissen 12/2003-6/2008 -*/ - -#define MODULE_BIT 0x00010000 - -#include "nv_std.h" - -static status_t nv4_nv10_nv20_dac_pix_pll_find( - display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test); - -/* see if an analog VGA monitor is connected to connector #1 */ -bool nv_dac_crt_connected(void) -{ - uint32 output, dac; - bool present; - - /* save output connector setting */ - output = DACR(OUTPUT); - /* save DAC state */ - dac = DACR(TSTCTRL); - - /* turn on DAC */ - DACW(TSTCTRL, (DACR(TSTCTRL) & 0xfffeffff)); - if (si->ps.secondary_head) - { - /* select primary CRTC (head) and turn off CRT (and DVI?) outputs */ - DACW(OUTPUT, (output & 0x0000feee)); - } - else - { - /* turn off CRT (and DVI?) outputs */ - /* note: - * Don't touch the CRTC (head) assignment bit, as that would have undefined - * results. Confirmed NV15 cards getting into lasting RAM access trouble - * otherwise!! (goes for both system gfx RAM access and CRTC/DAC RAM access.) */ - DACW(OUTPUT, (output & 0x0000ffee)); - } - /* wait for signal lines to stabilize */ - snooze(1000); - /* re-enable CRT output */ - DACW(OUTPUT, (DACR(OUTPUT) | 0x00000001)); - - /* setup RGB test signal levels to approx 30% of DAC range and enable them */ - DACW(TSTDATA, ((0x2 << 30) | (0x140 << 20) | (0x140 << 10) | (0x140 << 0))); - /* route test signals to output */ - DACW(TSTCTRL, (DACR(TSTCTRL) | 0x00001000)); - /* wait for signal lines to stabilize */ - snooze(1000); - - /* do actual detection: all signals paths high == CRT connected */ - if (DACR(TSTCTRL) & 0x10000000) - { - present = true; - LOG(4,("DAC: CRT detected on connector #1\n")); - } - else - { - present = false; - LOG(4,("DAC: no CRT detected on connector #1\n")); - } - - /* kill test signal routing */ - DACW(TSTCTRL, (DACR(TSTCTRL) & 0xffffefff)); - - /* restore output connector setting */ - DACW(OUTPUT, output); - /* restore DAC state */ - DACW(TSTCTRL, dac); - - return present; -} - -/*set the mode, brightness is a value from 0->2 (where 1 is equivalent to direct)*/ -status_t nv_dac_mode(int mode,float brightness) -{ - uint8 *r,*g,*b; - int i, ri; - - /*set colour arrays to point to space reserved in shared info*/ - r = si->color_data; - g = r + 256; - b = g + 256; - - LOG(4,("DAC: Setting screen mode %d brightness %f\n", mode, brightness)); - /* init the palette for brightness specified */ - /* (Nvidia cards always use MSbits from screenbuffer as index for PAL) */ - for (i = 0; i < 256; i++) - { - ri = i * brightness; - if (ri > 255) ri = 255; - b[i] = g[i] = r[i] = ri; - } - - if (nv_dac_palette(r,g,b) != B_OK) return B_ERROR; - - /* disable palette RAM adressing mask */ - NV_REG8(NV8_PALMASK) = 0xff; - LOG(2,("DAC: PAL pixrdmsk readback $%02x\n", NV_REG8(NV8_PALMASK))); - - return B_OK; -} - -/*program the DAC palette using the given r,g,b values*/ -status_t nv_dac_palette(uint8 r[256],uint8 g[256],uint8 b[256]) -{ - int i; - - LOG(4,("DAC: setting palette\n")); - - /* select first PAL adress before starting programming */ - NV_REG8(NV8_PALINDW) = 0x00; - - /* loop through all 256 to program DAC */ - for (i = 0; i < 256; i++) - { - /* the 6 implemented bits are on b0-b5 of the bus */ - NV_REG8(NV8_PALDATA) = r[i]; - NV_REG8(NV8_PALDATA) = g[i]; - NV_REG8(NV8_PALDATA) = b[i]; - } - if (NV_REG8(NV8_PALINDW) != 0x00) - { - LOG(8,("DAC: PAL write index incorrect after programming\n")); - return B_ERROR; - } -if (1) - {//reread LUT - uint8 R, G, B; - - /* select first PAL adress to read (modulo 3 counter) */ - NV_REG8(NV8_PALINDR) = 0x00; - for (i = 0; i < 256; i++) - { - R = NV_REG8(NV8_PALDATA); - G = NV_REG8(NV8_PALDATA); - B = NV_REG8(NV8_PALDATA); - if ((r[i] != R) || (g[i] != G) || (b[i] != B)) - LOG(1,("DAC palette %d: w %x %x %x, r %x %x %x\n", i, r[i], g[i], b[i], R, G, B)); // apsed - } - } - - return B_OK; -} - -/*program the pixpll - frequency in kHz*/ -status_t nv_dac_set_pix_pll(display_mode target) -{ - uint8 m=0,n=0,p=0; -// uint time = 0; - - float pix_setting, req_pclk; - status_t result; - - /* we offer this option because some panels have very tight restrictions, - * and there's no overlapping settings range that makes them all work. - * note: - * this assumes the cards BIOS correctly programmed the panel (is likely) */ - //fixme: when VESA DDC EDID stuff is implemented, this option can be deleted... - if (si->ps.tmds1_active && !si->settings.pgm_panel) - { - LOG(4,("DAC: Not programming DFP refresh (specified in nv.settings)\n")); - return B_OK; - } - - /* fix a DVI or laptop flatpanel to 60Hz refresh! */ - /* Note: - * The pixelclock drives the flatpanel modeline, not the CRTC modeline. */ - if (si->ps.tmds1_active) - { - LOG(4,("DAC: Fixing DFP refresh to 60Hz!\n")); - - /* use the panel's modeline to determine the needed pixelclock */ - target.timing.pixel_clock = si->ps.p1_timing.pixel_clock; - } - - req_pclk = (target.timing.pixel_clock)/1000.0; - LOG(4,("DAC: Setting PIX PLL for pixelclock %f\n", req_pclk)); - - /* signal that we actually want to set the mode */ - result = nv_dac_pix_pll_find(target,&pix_setting,&m,&n,&p, 1); - if (result != B_OK) - { - return result; - } - - /*reprogram (disable,select,wait for stability,enable)*/ -// DXIW(PIXCLKCTRL,(DXIR(PIXCLKCTRL)&0x0F)|0x04); /*disable the PIXPLL*/ -// DXIW(PIXCLKCTRL,(DXIR(PIXCLKCTRL)&0x0C)|0x01); /*select the PIXPLL*/ - - /* program new frequency */ - DACW(PIXPLLC, ((p << 16) | (n << 8) | m)); - - /* program 2nd set N and M scalers if they exist (b31=1 enables them) */ - if (si->ps.ext_pll) DACW(PIXPLLC2, 0x80000401); - - /* Wait for the PIXPLL frequency to lock until timeout occurs */ -//fixme: do NV cards have a LOCK indication bit?? -/* while((!(DXIR(PIXPLLSTAT)&0x40)) & (time <= 2000)) - { - time++; - snooze(1); - } - - if (time > 2000) - LOG(2,("DAC: PIX PLL frequency not locked!\n")); - else - LOG(2,("DAC: PIX PLL frequency locked\n")); - DXIW(PIXCLKCTRL,DXIR(PIXCLKCTRL)&0x0B); //enable the PIXPLL -*/ - -//for now: - /* Give the PIXPLL frequency some time to lock... */ - snooze(1000); - LOG(2,("DAC: PIX PLL frequency should be locked now...\n")); - - return B_OK; -} - -/* find nearest valid pix pll */ -status_t nv_dac_pix_pll_find - (display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test) -{ - switch (si->ps.card_type) { - default: return nv4_nv10_nv20_dac_pix_pll_find(target, calc_pclk, m_result, n_result, p_result, test); - } - return B_ERROR; -} - -/* find nearest valid pixel PLL setting */ -static status_t nv4_nv10_nv20_dac_pix_pll_find( - display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test) -{ - int m = 0, n = 0, p = 0/*, m_max*/; - float error, error_best = 999999999; - int best[3]; - float f_vco, max_pclk; - float req_pclk = target.timing.pixel_clock/1000.0; - - /* determine the max. reference-frequency postscaler setting for the - * current card (see G100, G200 and G400 specs). */ -/* switch(si->ps.card_type) - { - case G100: - LOG(4,("DAC: G100 restrictions apply\n")); - m_max = 7; - break; - case G200: - LOG(4,("DAC: G200 restrictions apply\n")); - m_max = 7; - break; - default: - LOG(4,("DAC: G400/G400MAX restrictions apply\n")); - m_max = 32; - break; - } -*/ - LOG(4,("DAC: NV4/NV10/NV20 restrictions apply\n")); - - /* determine the max. pixelclock for the current videomode */ - switch (target.space) - { - case B_CMAP8: - max_pclk = si->ps.max_dac1_clock_8; - break; - case B_RGB15_LITTLE: - case B_RGB16_LITTLE: - max_pclk = si->ps.max_dac1_clock_16; - break; - case B_RGB24_LITTLE: - max_pclk = si->ps.max_dac1_clock_24; - break; - case B_RGB32_LITTLE: - max_pclk = si->ps.max_dac1_clock_32; - break; - default: - /* use fail-safe value */ - max_pclk = si->ps.max_dac1_clock_32; - break; - } - /* if some dualhead mode is active, an extra restriction might apply */ - if ((target.flags & DUALHEAD_BITS) && (target.space == B_RGB32_LITTLE)) - max_pclk = si->ps.max_dac1_clock_32dh; - - /* Make sure the requested pixelclock is within the PLL's operational limits */ - /* lower limit is min_pixel_vco divided by highest postscaler-factor */ - if (req_pclk < (si->ps.min_pixel_vco / 16.0)) - { - LOG(4,("DAC: clamping pixclock: requested %fMHz, set to %fMHz\n", - req_pclk, (float)(si->ps.min_pixel_vco / 16.0))); - req_pclk = (si->ps.min_pixel_vco / 16.0); - } - /* upper limit is given by pins in combination with current active mode */ - if (req_pclk > max_pclk) - { - LOG(4,("DAC: clamping pixclock: requested %fMHz, set to %fMHz\n", - req_pclk, (float)max_pclk)); - req_pclk = max_pclk; - } - - /* iterate through all valid PLL postscaler settings */ - for (p=0x01; p < 0x20; p = p<<1) - { - /* calculate the needed VCO frequency for this postscaler setting */ - f_vco = req_pclk * p; - - /* check if this is within range of the VCO specs */ - if ((f_vco >= si->ps.min_pixel_vco) && (f_vco <= si->ps.max_pixel_vco)) - { - /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ - if (si->ps.ext_pll) f_vco /= 4; - - /* iterate trough all valid reference-frequency postscaler settings */ - for (m = 7; m <= 14; m++) - { - /* check if phase-discriminator will be within operational limits */ - if (((si->ps.f_ref / m) < 1.0) || ((si->ps.f_ref / m) > 2.0)) continue; - - /* calculate VCO postscaler setting for current setup.. */ - n = (int)(((f_vco * m) / si->ps.f_ref) + 0.5); - - /* ..and check for validity */ - if ((n < 1) || (n > 255)) continue; - - /* find error in frequency this setting gives */ - if (si->ps.ext_pll) - { - /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ - error = fabs((req_pclk / 4) - (((si->ps.f_ref / m) * n) / p)); - } - else - error = fabs(req_pclk - (((si->ps.f_ref / m) * n) / p)); - - /* note the setting if best yet */ - if (error < error_best) - { - error_best = error; - best[0]=m; - best[1]=n; - best[2]=p; - } - } - } - } - - /* setup the scalers programming values for found optimum setting */ - m = best[0]; - n = best[1]; - p = best[2]; - - /* log the VCO frequency found */ - f_vco = ((si->ps.f_ref / m) * n); - /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ - if (si->ps.ext_pll) f_vco *= 4; - - LOG(2,("DAC: pix VCO frequency found %fMhz\n", f_vco)); - - /* return the results */ - *calc_pclk = (f_vco / p); - *m_result = m; - *n_result = n; - switch(p) - { - case 1: - p = 0x00; - break; - case 2: - p = 0x01; - break; - case 4: - p = 0x02; - break; - case 8: - p = 0x03; - break; - case 16: - p = 0x04; - break; - } - *p_result = p; - - /* display the found pixelclock values */ - LOG(2,("DAC: pix PLL check: requested %fMHz got %fMHz, mnp 0x%02x 0x%02x 0x%02x\n", - req_pclk, *calc_pclk, *m_result, *n_result, *p_result)); - - return B_OK; -} - -/* find nearest valid system PLL setting */ -status_t nv_dac_sys_pll_find( - float req_sclk, float* calc_sclk, uint8* m_result, uint8* n_result, uint8* p_result, uint8 test) -{ - int m = 0, n = 0, p = 0, m_max, p_max; - float error, error_best = 999999999; - int best[3]; - float f_vco, discr_low, discr_high; - - /* determine the max. reference-frequency postscaler setting for the - * current requested clock */ - LOG(4,("DAC: NV10/NV20/NV30 restrictions apply\n")); - /* set max. useable reference frequency postscaler divider factor; - * apparantly we would get distortions on high PLL output frequencies if - * we use the phase-discriminator at low frequencies */ - if (req_sclk > 340.0) m_max = 2; /* Fpll > 340Mhz */ - else if (req_sclk > 250.0) m_max = 6; /* 250Mhz < Fpll <= 340Mhz */ - else m_max = 14; /* Fpll < 250Mhz */ - - /* set max. useable VCO output postscaler divider factor */ - p_max = 16; - /* set phase-discriminator frequency range (Mhz) (verified) */ - discr_low = 1.0; - /* (high discriminator spec is failsafe) */ - discr_high = 14.0; - - LOG(4,("DAC: PLL reference frequency postscaler divider range is 1 - %d\n", m_max)); - LOG(4,("DAC: PLL VCO output postscaler divider range is 1 - %d\n", p_max)); - LOG(4,("DAC: PLL discriminator input frequency range is %2.2fMhz - %2.2fMhz\n", - discr_low, discr_high)); - - /* Make sure the requested clock is within the PLL's operational limits */ - /* lower limit is min_system_vco divided by highest postscaler-factor */ - if (req_sclk < (si->ps.min_system_vco / ((float)p_max))) - { - LOG(4,("DAC: clamping sysclock: requested %fMHz, set to %fMHz\n", - req_sclk, (si->ps.min_system_vco / ((float)p_max)))); - req_sclk = (si->ps.min_system_vco / ((float)p_max)); - } - /* upper limit is given by pins */ - if (req_sclk > si->ps.max_system_vco) - { - LOG(4,("DAC: clamping sysclock: requested %fMHz, set to %fMHz\n", - req_sclk, (float)si->ps.max_system_vco)); - req_sclk = si->ps.max_system_vco; - } - - /* iterate through all valid PLL postscaler settings */ - for (p=0x01; p <= p_max; p = p<<1) - { - /* calculate the needed VCO frequency for this postscaler setting */ - f_vco = req_sclk * p; - - /* check if this is within range of the VCO specs */ - if ((f_vco >= si->ps.min_system_vco) && (f_vco <= si->ps.max_system_vco)) - { - /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ - if (si->ps.ext_pll) f_vco /= 4; - - /* iterate trough all valid reference-frequency postscaler settings */ - for (m = 1; m <= m_max; m++) - { - /* check if phase-discriminator will be within operational limits */ - if (((si->ps.f_ref / m) < discr_low) || ((si->ps.f_ref / m) > discr_high)) - continue; - - /* calculate VCO postscaler setting for current setup.. */ - n = (int)(((f_vco * m) / si->ps.f_ref) + 0.5); - - /* ..and check for validity */ - if ((n < 1) || (n > 255)) continue; - - /* find error in frequency this setting gives */ - if (si->ps.ext_pll) - { - /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ - error = fabs((req_sclk / 4) - (((si->ps.f_ref / m) * n) / p)); - } - else - error = fabs(req_sclk - (((si->ps.f_ref / m) * n) / p)); - - /* note the setting if best yet */ - if (error < error_best) - { - error_best = error; - best[0]=m; - best[1]=n; - best[2]=p; - } - } - } - } - - /* setup the scalers programming values for found optimum setting */ - m = best[0]; - n = best[1]; - p = best[2]; - - /* log the VCO frequency found */ - f_vco = ((si->ps.f_ref / m) * n); - /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ - if (si->ps.ext_pll) f_vco *= 4; - - LOG(2,("DAC: sys VCO frequency found %fMhz\n", f_vco)); - - /* return the results */ - *calc_sclk = (f_vco / p); - *m_result = m; - *n_result = n; - switch(p) - { - case 1: - p = 0x00; - break; - case 2: - p = 0x01; - break; - case 4: - p = 0x02; - break; - case 8: - p = 0x03; - break; - case 16: - p = 0x04; - break; - case 32: - p = 0x05; - break; - } - *p_result = p; - - /* display the found pixelclock values */ - LOG(2,("DAC: sys PLL check: requested %fMHz got %fMHz, mnp 0x%02x 0x%02x 0x%02x\n", - req_sclk, *calc_sclk, *m_result, *n_result, *p_result)); - - return B_OK; -} diff --git a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_dac2.c b/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_dac2.c deleted file mode 100644 index e7bf63f82b..0000000000 --- a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_dac2.c +++ /dev/null @@ -1,384 +0,0 @@ -/* program the secondary DAC */ -/* Author: - Rudolf Cornelissen 12/2003-6/2008 -*/ - -#define MODULE_BIT 0x00001000 - -#include "nv_std.h" - -static status_t nv10_nv20_dac2_pix_pll_find( - display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test); - -/* see if an analog VGA monitor is connected to connector #2 */ -//fixme if possible: on NV40 arch (confirmed NV43) this routine always find a monitor! -bool nv_dac2_crt_connected() -{ - uint32 output, dac; - bool present; - - /* NOTE: - * NV11 can't do this: It will report DAC1 status instead because it HAS no - * actual secondary DAC function. */ - /* (It DOES have a secondary palette RAM and pixelclock PLL though.) */ - - /* save output connector setting */ - output = DAC2R(OUTPUT); - /* save DAC state */ - dac = DAC2R(TSTCTRL); - - /* turn on DAC2 */ - DAC2W(TSTCTRL, (DAC2R(TSTCTRL) & 0xfffeffff)); - /* select primary CRTC (head) and turn off CRT (and DVI?) outputs */ - DAC2W(OUTPUT, (output & 0x0000feee)); - /* wait for signal lines to stabilize */ - snooze(1000); - /* re-enable CRT output */ - DAC2W(OUTPUT, (DAC2R(OUTPUT) | 0x00000001)); - - /* setup RGB test signal levels to approx 30% of DAC range and enable them - * (NOTE: testsignal function block resides in DAC1 only (!)) */ - DACW(TSTDATA, ((0x2 << 30) | (0x140 << 20) | (0x140 << 10) | (0x140 << 0))); - /* route test signals to output - * (NOTE: testsignal function block resides in DAC1 only (!)) */ - DACW(TSTCTRL, (DACR(TSTCTRL) | 0x00001000)); - /* wait for signal lines to stabilize */ - snooze(1000); - - /* do actual detection: all signals paths high == CRT connected */ - if (DAC2R(TSTCTRL) & 0x10000000) - { - present = true; - LOG(4,("DAC2: CRT detected on connector #2\n")); - } - else - { - present = false; - LOG(4,("DAC2: no CRT detected on connector #2\n")); - } - - /* kill test signal routing - * (NOTE: testsignal function block resides in DAC1 only (!)) */ - DACW(TSTCTRL, (DACR(TSTCTRL) & 0xffffefff)); - - /* restore output connector setting */ - DAC2W(OUTPUT, output); - /* restore DAC state */ - DAC2W(TSTCTRL, dac); - - return present; -} - -/*set the mode, brightness is a value from 0->2 (where 1 is equivalent to direct)*/ -status_t nv_dac2_mode(int mode,float brightness) -{ - uint8 *r,*g,*b; - int i, ri; - - /*set colour arrays to point to space reserved in shared info*/ - r = si->color_data; - g = r + 256; - b = g + 256; - - LOG(4,("DAC2: Setting screen mode %d brightness %f\n", mode, brightness)); - /* init the palette for brightness specified */ - /* (Nvidia cards always use MSbits from screenbuffer as index for PAL) */ - for (i = 0; i < 256; i++) - { - ri = i * brightness; - if (ri > 255) ri = 255; - b[i] = g[i] = r[i] = ri; - } - - if (nv_dac2_palette(r,g,b) != B_OK) return B_ERROR; - - /* disable palette RAM adressing mask */ - NV_REG8(NV8_PAL2MASK) = 0xff; - LOG(2,("DAC2: PAL pixrdmsk readback $%02x\n", NV_REG8(NV8_PAL2MASK))); - - return B_OK; -} - -/*program the DAC palette using the given r,g,b values*/ -status_t nv_dac2_palette(uint8 r[256],uint8 g[256],uint8 b[256]) -{ - int i; - - LOG(4,("DAC2: setting palette\n")); - - /* select first PAL adress before starting programming */ - NV_REG8(NV8_PAL2INDW) = 0x00; - - /* loop through all 256 to program DAC */ - for (i = 0; i < 256; i++) - { - /* the 6 implemented bits are on b0-b5 of the bus */ - NV_REG8(NV8_PAL2DATA) = r[i]; - NV_REG8(NV8_PAL2DATA) = g[i]; - NV_REG8(NV8_PAL2DATA) = b[i]; - } - if (NV_REG8(NV8_PAL2INDW) != 0x00) - { - LOG(8,("DAC2: PAL write index incorrect after programming\n")); - return B_ERROR; - } -if (1) - {//reread LUT - uint8 R, G, B; - - /* select first PAL adress to read (modulo 3 counter) */ - NV_REG8(NV8_PAL2INDR) = 0x00; - for (i = 0; i < 256; i++) - { - R = NV_REG8(NV8_PAL2DATA); - G = NV_REG8(NV8_PAL2DATA); - B = NV_REG8(NV8_PAL2DATA); - if ((r[i] != R) || (g[i] != G) || (b[i] != B)) - LOG(1,("DAC2 palette %d: w %x %x %x, r %x %x %x\n", i, r[i], g[i], b[i], R, G, B)); // apsed - } - } - - return B_OK; -} - -/*program the pixpll - frequency in kHz*/ -status_t nv_dac2_set_pix_pll(display_mode target) -{ - uint8 m=0,n=0,p=0; -// uint time = 0; - - float pix_setting, req_pclk; - status_t result; - - /* we offer this option because some panels have very tight restrictions, - * and there's no overlapping settings range that makes them all work. - * note: - * this assumes the cards BIOS correctly programmed the panel (is likely) */ - //fixme: when VESA DDC EDID stuff is implemented, this option can be deleted... - if (si->ps.tmds2_active && !si->settings.pgm_panel) - { - LOG(4,("DAC2: Not programming DFP refresh (specified in nv.settings)\n")); - return B_OK; - } - - /* fix a DVI or laptop flatpanel to 60Hz refresh! */ - /* Note: - * The pixelclock drives the flatpanel modeline, not the CRTC modeline. */ - if (si->ps.tmds2_active) - { - LOG(4,("DAC2: Fixing DFP refresh to 60Hz!\n")); - - /* use the panel's modeline to determine the needed pixelclock */ - target.timing.pixel_clock = si->ps.p2_timing.pixel_clock; - } - - req_pclk = (target.timing.pixel_clock)/1000.0; - LOG(4,("DAC2: Setting PIX PLL for pixelclock %f\n", req_pclk)); - - /* signal that we actually want to set the mode */ - result = nv_dac2_pix_pll_find(target,&pix_setting,&m,&n,&p, 1); - if (result != B_OK) - { - return result; - } - - /*reprogram (disable,select,wait for stability,enable)*/ -// DXIW(PIXCLKCTRL,(DXIR(PIXCLKCTRL)&0x0F)|0x04); /*disable the PIXPLL*/ -// DXIW(PIXCLKCTRL,(DXIR(PIXCLKCTRL)&0x0C)|0x01); /*select the PIXPLL*/ - - /* program new frequency */ - DAC2W(PIXPLLC, ((p << 16) | (n << 8) | m)); - - /* program 2nd set N and M scalers if they exist (b31=1 enables them) */ - if (si->ps.ext_pll) DAC2W(PIXPLLC2, 0x80000401); - - /* Wait for the PIXPLL frequency to lock until timeout occurs */ -//fixme: do NV cards have a LOCK indication bit?? -/* while((!(DXIR(PIXPLLSTAT)&0x40)) & (time <= 2000)) - { - time++; - snooze(1); - } - - if (time > 2000) - LOG(2,("DAC: PIX PLL frequency not locked!\n")); - else - LOG(2,("DAC: PIX PLL frequency locked\n")); - DXIW(PIXCLKCTRL,DXIR(PIXCLKCTRL)&0x0B); //enable the PIXPLL -*/ - -//for now: - /* Give the PIXPLL frequency some time to lock... */ - snooze(1000); - LOG(2,("DAC2: PIX PLL frequency should be locked now...\n")); - - return B_OK; -} - -/* find nearest valid pix pll */ -status_t nv_dac2_pix_pll_find - (display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test) -{ - switch (si->ps.card_type) { - default: return nv10_nv20_dac2_pix_pll_find(target, calc_pclk, m_result, n_result, p_result, test); - } - return B_ERROR; -} - -/* find nearest valid pixel PLL setting */ -static status_t nv10_nv20_dac2_pix_pll_find( - display_mode target,float * calc_pclk,uint8 * m_result,uint8 * n_result,uint8 * p_result, uint8 test) -{ - int m = 0, n = 0, p = 0/*, m_max*/; - float error, error_best = 999999999; - int best[3]; - float f_vco, max_pclk; - float req_pclk = target.timing.pixel_clock/1000.0; - - /* determine the max. reference-frequency postscaler setting for the - * current card (see G100, G200 and G400 specs). */ -/* switch(si->ps.card_type) - { - case G100: - LOG(4,("DAC: G100 restrictions apply\n")); - m_max = 7; - break; - case G200: - LOG(4,("DAC: G200 restrictions apply\n")); - m_max = 7; - break; - default: - LOG(4,("DAC: G400/G400MAX restrictions apply\n")); - m_max = 32; - break; - } -*/ - LOG(4,("DAC2: NV10/NV20 restrictions apply\n")); - - /* determine the max. pixelclock for the current videomode */ - switch (target.space) - { - case B_CMAP8: - max_pclk = si->ps.max_dac2_clock_8; - break; - case B_RGB15_LITTLE: - case B_RGB16_LITTLE: - max_pclk = si->ps.max_dac2_clock_16; - break; - case B_RGB24_LITTLE: - max_pclk = si->ps.max_dac2_clock_24; - break; - case B_RGB32_LITTLE: - max_pclk = si->ps.max_dac2_clock_32; - break; - default: - /* use fail-safe value */ - max_pclk = si->ps.max_dac2_clock_32; - break; - } - /* if some dualhead mode is active, an extra restriction might apply */ - if ((target.flags & DUALHEAD_BITS) && (target.space == B_RGB32_LITTLE)) - max_pclk = si->ps.max_dac2_clock_32dh; - - /* Make sure the requested pixelclock is within the PLL's operational limits */ - /* lower limit is min_pixel_vco divided by highest postscaler-factor */ - if (req_pclk < (si->ps.min_video_vco / 16.0)) - { - LOG(4,("DAC2: clamping pixclock: requested %fMHz, set to %fMHz\n", - req_pclk, (float)(si->ps.min_video_vco / 16.0))); - req_pclk = (si->ps.min_video_vco / 16.0); - } - /* upper limit is given by pins in combination with current active mode */ - if (req_pclk > max_pclk) - { - LOG(4,("DAC2: clamping pixclock: requested %fMHz, set to %fMHz\n", - req_pclk, (float)max_pclk)); - req_pclk = max_pclk; - } - - /* iterate through all valid PLL postscaler settings */ - for (p=0x01; p < 0x20; p = p<<1) - { - /* calculate the needed VCO frequency for this postscaler setting */ - f_vco = req_pclk * p; - - /* check if this is within range of the VCO specs */ - if ((f_vco >= si->ps.min_video_vco) && (f_vco <= si->ps.max_video_vco)) - { - /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ - if (si->ps.ext_pll) f_vco /= 4; - - /* iterate trough all valid reference-frequency postscaler settings */ - for (m = 7; m <= 14; m++) - { - /* check if phase-discriminator will be within operational limits */ - if (((si->ps.f_ref / m) < 1.0) || ((si->ps.f_ref / m) > 2.0)) continue; - - /* calculate VCO postscaler setting for current setup.. */ - n = (int)(((f_vco * m) / si->ps.f_ref) + 0.5); - /* ..and check for validity */ - if ((n < 1) || (n > 255)) continue; - - /* find error in frequency this setting gives */ - if (si->ps.ext_pll) - { - /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ - error = fabs((req_pclk / 4) - (((si->ps.f_ref / m) * n) / p)); - } - else - error = fabs(req_pclk - (((si->ps.f_ref / m) * n) / p)); - - /* note the setting if best yet */ - if (error < error_best) - { - error_best = error; - best[0]=m; - best[1]=n; - best[2]=p; - } - } - } - } - - /* setup the scalers programming values for found optimum setting */ - m = best[0]; - n = best[1]; - p = best[2]; - - /* log the VCO frequency found */ - f_vco = ((si->ps.f_ref / m) * n); - /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ - if (si->ps.ext_pll) f_vco *= 4; - - LOG(2,("DAC2: pix VCO frequency found %fMhz\n", f_vco)); - - /* return the results */ - *calc_pclk = (f_vco / p); - *m_result = m; - *n_result = n; - switch(p) - { - case 1: - p = 0x00; - break; - case 2: - p = 0x01; - break; - case 4: - p = 0x02; - break; - case 8: - p = 0x03; - break; - case 16: - p = 0x04; - break; - } - *p_result = p; - - /* display the found pixelclock values */ - LOG(2,("DAC2: pix PLL check: requested %fMHz got %fMHz, mnp 0x%02x 0x%02x 0x%02x\n", - req_pclk, *calc_pclk, *m_result, *n_result, *p_result)); - - return B_OK; -} diff --git a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_general.c b/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_general.c deleted file mode 100644 index 2f13b683f3..0000000000 --- a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_general.c +++ /dev/null @@ -1,901 +0,0 @@ -/* Authors: - Mark Watson 12/1999, - Apsed, - Rudolf Cornelissen 10/2002-6/2008 -*/ - -#define MODULE_BIT 0x00008000 - -#include "nv_std.h" - -static status_t test_ram(void); -static status_t nvxx_general_powerup (void); -static void unlock_card(void); -static status_t nv_general_bios_to_powergraphics(void); - -static void nv_dump_configuration_space (void) -{ -#define DUMP_CFG(reg, type) if (si->ps.card_type >= type) do { \ - uint32 value = CFGR(reg); \ - MSG(("configuration_space 0x%02x %20s 0x%08x\n", \ - NVCFG_##reg, #reg, value)); \ -} while (0) - DUMP_CFG (DEVID, 0); - DUMP_CFG (DEVCTRL, 0); - DUMP_CFG (CLASS, 0); - DUMP_CFG (HEADER, 0); - DUMP_CFG (BASE1REGS,0); - DUMP_CFG (BASE2FB, 0); - DUMP_CFG (BASE3, 0); - DUMP_CFG (BASE4, 0); - DUMP_CFG (BASE5, 0); - DUMP_CFG (BASE6, 0); - DUMP_CFG (BASE7, 0); - DUMP_CFG (SUBSYSID1,0); - DUMP_CFG (ROMBASE, 0); - DUMP_CFG (CAPPTR, 0); - DUMP_CFG (CFG_1, 0); - DUMP_CFG (INTERRUPT,0); - DUMP_CFG (SUBSYSID2,0); - DUMP_CFG (AGPREF, 0); - DUMP_CFG (AGPSTAT, 0); - DUMP_CFG (AGPCMD, 0); - DUMP_CFG (ROMSHADOW,0); - DUMP_CFG (VGA, 0); - DUMP_CFG (SCHRATCH, 0); - DUMP_CFG (CFG_10, 0); - DUMP_CFG (CFG_11, 0); - DUMP_CFG (CFG_12, 0); - DUMP_CFG (CFG_13, 0); - DUMP_CFG (CFG_14, 0); - DUMP_CFG (CFG_15, 0); - DUMP_CFG (CFG_16, 0); - DUMP_CFG (PCIEREF, 0); - DUMP_CFG (PCIEDCAP, 0); - DUMP_CFG (PCIEDCTST,0); - DUMP_CFG (PCIELCAP, 0); - DUMP_CFG (PCIELCTST,0); - DUMP_CFG (CFG_22, 0); - DUMP_CFG (CFG_23, 0); - DUMP_CFG (CFG_24, 0); - DUMP_CFG (CFG_25, 0); - DUMP_CFG (CFG_26, 0); - DUMP_CFG (CFG_27, 0); - DUMP_CFG (CFG_28, 0); - DUMP_CFG (CFG_29, 0); - DUMP_CFG (CFG_30, 0); - DUMP_CFG (CFG_31, 0); - DUMP_CFG (CFG_32, 0); - DUMP_CFG (CFG_33, 0); - DUMP_CFG (CFG_34, 0); - DUMP_CFG (CFG_35, 0); - DUMP_CFG (CFG_36, 0); - DUMP_CFG (CFG_37, 0); - DUMP_CFG (CFG_38, 0); - DUMP_CFG (CFG_39, 0); - DUMP_CFG (CFG_40, 0); - DUMP_CFG (CFG_41, 0); - DUMP_CFG (CFG_42, 0); - DUMP_CFG (CFG_43, 0); - DUMP_CFG (CFG_44, 0); - DUMP_CFG (CFG_45, 0); - DUMP_CFG (CFG_46, 0); - DUMP_CFG (CFG_47, 0); - DUMP_CFG (CFG_48, 0); - DUMP_CFG (CFG_49, 0); - DUMP_CFG (CFG_50, 0); -#undef DUMP_CFG -} - -status_t nv_general_powerup() -{ - status_t status; - - LOG(1,("POWERUP: Haiku nVidia-gpgpu Accelerant 0.00 running.\n")); - - /* log VBLANK INT usability status */ - if (si->ps.int_assigned) - LOG(4,("POWERUP: Usable INT assigned to HW; Vblank semaphore enabled\n")); - else - LOG(4,("POWERUP: No (usable) INT assigned to HW; Vblank semaphore disabled\n")); - - /* preset no laptop */ - si->ps.laptop = false; - - /* WARNING: - * _adi.name_ and _adi.chipset_ can contain 31 readable characters max.!!! */ - - /* detect card type and power it up */ - switch(CFGR(DEVID)) - { - /* Vendor Nvidia */ - case 0x019110de: /* Nvidia GeForce 8800 GTX */ - case 0x019310de: /* Nvidia GeForce 8800 GTS */ - si->ps.card_type = G80; - si->ps.card_arch = NV50A; - sprintf(si->adi.name, "Nvidia GeForce 8800"); - sprintf(si->adi.chipset, "G80"); - status = nvxx_general_powerup(); - break; - case 0x040010de: /* Nvidia GeForce 8600 GTS */ - case 0x040210de: /* Nvidia GeForce 8600 GT */ - si->ps.card_type = G84; - si->ps.card_arch = NV50A; - sprintf(si->adi.name, "Nvidia GeForce 8600"); - sprintf(si->adi.chipset, "G84"); - status = nvxx_general_powerup(); - break; - case 0x040710de: /* Nvidia GeForce 8600M GT */ - si->ps.card_type = G86; - si->ps.card_arch = NV50A; - si->ps.laptop = true; - sprintf(si->adi.name, "Nvidia GeForce 8600M GT"); - sprintf(si->adi.chipset, "G86"); - status = nvxx_general_powerup(); - break; - case 0x042110de: /* Nvidia GeForce 8500 GT */ - si->ps.card_type = G86; - si->ps.card_arch = NV50A; - sprintf(si->adi.name, "Nvidia GeForce 8500 GT"); - sprintf(si->adi.chipset, "G86"); - status = nvxx_general_powerup(); - break; - case 0x042210de: /* Nvidia GeForce 8400 GS */ - si->ps.card_type = G86; - si->ps.card_arch = NV50A; - sprintf(si->adi.name, "Nvidia GeForce 8400 GS"); - sprintf(si->adi.chipset, "G86"); - status = nvxx_general_powerup(); - break; - case 0x042310de: /* Nvidia GeForce 8300 GS */ - si->ps.card_type = G86; - si->ps.card_arch = NV50A; - sprintf(si->adi.name, "Nvidia GeForce 8300 GS"); - sprintf(si->adi.chipset, "G86"); - status = nvxx_general_powerup(); - break; - default: - LOG(8,("POWERUP: Failed to detect valid card 0x%08x\n",CFGR(DEVID))); - return B_ERROR; - } - - return status; -} - -static status_t test_ram() -{ - uint32 value, offset; - status_t result = B_OK; - - /* make sure we don't corrupt the hardware cursor by using fbc.frame_buffer. */ - if (si->fbc.frame_buffer == NULL) - { - LOG(8,("INIT: test_ram detected NULL pointer.\n")); - return B_ERROR; - } - - for (offset = 0, value = 0x55aa55aa; offset < 256; offset++) - { - /* write testpattern to cardRAM */ - ((uint32 *)si->fbc.frame_buffer)[offset] = value; - /* toggle testpattern */ - value = 0xffffffff - value; - } - - for (offset = 0, value = 0x55aa55aa; offset < 256; offset++) - { - /* readback and verify testpattern from cardRAM */ - if (((uint32 *)si->fbc.frame_buffer)[offset] != value) result = B_ERROR; - /* toggle testpattern */ - value = 0xffffffff - value; - } - return result; -} - -/* NOTE: - * This routine *has* to be done *after* SetDispplayMode has been executed, - * or test results will not be representative! - * (CAS latency is dependant on NV setup on some (DRAM) boards) */ -status_t nv_set_cas_latency() -{ - status_t result = B_ERROR; - uint8 latency = 0; - - /* check current RAM access to see if we need to change anything */ - if (test_ram() == B_OK) - { - LOG(4,("INIT: RAM access OK.\n")); - return B_OK; - } - - /* check if we read PINS at starttime so we have valid registersettings at our disposal */ - if (si->ps.pins_status != B_OK) - { - LOG(4,("INIT: RAM access errors; not fixable: PINS was not read from cardBIOS.\n")); - return B_ERROR; - } - - /* OK. We might have a problem, try to fix it now.. */ - LOG(4,("INIT: RAM access errors; tuning CAS latency if prudent...\n")); - - switch(si->ps.card_type) - { - default: - LOG(4,("INIT: RAM CAS tuning not implemented for this card, aborting.\n")); - return B_OK; - break; - } - if (result == B_OK) - LOG(4,("INIT: RAM access OK. CAS latency set to %d cycles.\n", latency)); - else - LOG(4,("INIT: RAM access not fixable. CAS latency set to %d cycles.\n", latency)); - - return result; -} - -void setup_virtualized_heads(bool cross) -{ - if (cross) - { - head1_interrupt_enable = (crtc_interrupt_enable) nv_crtc2_interrupt_enable; - head1_update_fifo = (crtc_update_fifo) nv_crtc2_update_fifo; - head1_validate_timing = (crtc_validate_timing) nv_crtc2_validate_timing; - head1_set_timing = (crtc_set_timing) nv_crtc2_set_timing; - head1_depth = (crtc_depth) nv_crtc2_depth; - head1_dpms = (crtc_dpms) nv_crtc2_dpms; - head1_set_display_pitch = (crtc_set_display_pitch) nv_crtc2_set_display_pitch; - head1_set_display_start = (crtc_set_display_start) nv_crtc2_set_display_start; - head1_cursor_init = (crtc_cursor_init) nv_crtc2_cursor_init; - head1_cursor_show = (crtc_cursor_show) nv_crtc2_cursor_show; - head1_cursor_hide = (crtc_cursor_hide) nv_crtc2_cursor_hide; - head1_cursor_define = (crtc_cursor_define) nv_crtc2_cursor_define; - head1_cursor_position = (crtc_cursor_position) nv_crtc2_cursor_position; - - head1_mode = (dac_mode) nv_dac2_mode; - head1_palette = (dac_palette) nv_dac2_palette; - head1_set_pix_pll = (dac_set_pix_pll) nv_dac2_set_pix_pll; - head1_pix_pll_find = (dac_pix_pll_find) nv_dac2_pix_pll_find; - - head2_interrupt_enable = (crtc_interrupt_enable) nv_crtc_interrupt_enable; - head2_update_fifo = (crtc_update_fifo) nv_crtc_update_fifo; - head2_validate_timing = (crtc_validate_timing) nv_crtc_validate_timing; - head2_set_timing = (crtc_set_timing) nv_crtc_set_timing; - head2_depth = (crtc_depth) nv_crtc_depth; - head2_dpms = (crtc_dpms) nv_crtc_dpms; - head2_set_display_pitch = (crtc_set_display_pitch) nv_crtc_set_display_pitch; - head2_set_display_start = (crtc_set_display_start) nv_crtc_set_display_start; - head2_cursor_init = (crtc_cursor_init) nv_crtc_cursor_init; - head2_cursor_show = (crtc_cursor_show) nv_crtc_cursor_show; - head2_cursor_hide = (crtc_cursor_hide) nv_crtc_cursor_hide; - head2_cursor_define = (crtc_cursor_define) nv_crtc_cursor_define; - head2_cursor_position = (crtc_cursor_position) nv_crtc_cursor_position; - - head2_mode = (dac_mode) nv_dac_mode; - head2_palette = (dac_palette) nv_dac_palette; - head2_set_pix_pll = (dac_set_pix_pll) nv_dac_set_pix_pll; - head2_pix_pll_find = (dac_pix_pll_find) nv_dac_pix_pll_find; - } - else - { - head1_interrupt_enable = (crtc_interrupt_enable) nv_crtc_interrupt_enable; - head1_update_fifo = (crtc_update_fifo) nv_crtc_update_fifo; - head1_validate_timing = (crtc_validate_timing) nv_crtc_validate_timing; - head1_set_timing = (crtc_set_timing) nv_crtc_set_timing; - head1_depth = (crtc_depth) nv_crtc_depth; - head1_dpms = (crtc_dpms) nv_crtc_dpms; - head1_set_display_pitch = (crtc_set_display_pitch) nv_crtc_set_display_pitch; - head1_set_display_start = (crtc_set_display_start) nv_crtc_set_display_start; - head1_cursor_init = (crtc_cursor_init) nv_crtc_cursor_init; - head1_cursor_show = (crtc_cursor_show) nv_crtc_cursor_show; - head1_cursor_hide = (crtc_cursor_hide) nv_crtc_cursor_hide; - head1_cursor_define = (crtc_cursor_define) nv_crtc_cursor_define; - head1_cursor_position = (crtc_cursor_position) nv_crtc_cursor_position; - - head1_mode = (dac_mode) nv_dac_mode; - head1_palette = (dac_palette) nv_dac_palette; - head1_set_pix_pll = (dac_set_pix_pll) nv_dac_set_pix_pll; - head1_pix_pll_find = (dac_pix_pll_find) nv_dac_pix_pll_find; - - head2_interrupt_enable = (crtc_interrupt_enable) nv_crtc2_interrupt_enable; - head2_update_fifo = (crtc_update_fifo) nv_crtc2_update_fifo; - head2_validate_timing = (crtc_validate_timing) nv_crtc2_validate_timing; - head2_set_timing = (crtc_set_timing) nv_crtc2_set_timing; - head2_depth = (crtc_depth) nv_crtc2_depth; - head2_dpms = (crtc_dpms) nv_crtc2_dpms; - head2_set_display_pitch = (crtc_set_display_pitch) nv_crtc2_set_display_pitch; - head2_set_display_start = (crtc_set_display_start) nv_crtc2_set_display_start; - head2_cursor_init = (crtc_cursor_init) nv_crtc2_cursor_init; - head2_cursor_show = (crtc_cursor_show) nv_crtc2_cursor_show; - head2_cursor_hide = (crtc_cursor_hide) nv_crtc2_cursor_hide; - head2_cursor_define = (crtc_cursor_define) nv_crtc2_cursor_define; - head2_cursor_position = (crtc_cursor_position) nv_crtc2_cursor_position; - - head2_mode = (dac_mode) nv_dac2_mode; - head2_palette = (dac_palette) nv_dac2_palette; - head2_set_pix_pll = (dac_set_pix_pll) nv_dac2_set_pix_pll; - head2_pix_pll_find = (dac_pix_pll_find) nv_dac2_pix_pll_find; - } -} - -void set_crtc_owner(bool head) -{ - if (si->ps.secondary_head) - { - if (!head) - { - /* note: 'OWNER' is a non-standard register in behaviour(!) on NV11's, - * while non-NV11 cards behave normally. - * - * Double-write action needed on those strange NV11 cards: */ - /* RESET: needed on NV11 */ - CRTCW(OWNER, 0xff); - /* enable access to CRTC1, SEQ1, GRPH1, ATB1, ??? */ - CRTCW(OWNER, 0x00); - } - else - { - /* note: 'OWNER' is a non-standard register in behaviour(!) on NV11's, - * while non-NV11 cards behave normally. - * - * Double-write action needed on those strange NV11 cards: */ - /* RESET: needed on NV11 */ - CRTC2W(OWNER, 0xff); - /* enable access to CRTC2, SEQ2, GRPH2, ATB2, ??? */ - CRTC2W(OWNER, 0x03); - } - } -} - -static status_t nvxx_general_powerup() -{ - LOG(4, ("INIT: NV powerup\n")); - LOG(4,("POWERUP: Detected %s (%s)\n", si->adi.name, si->adi.chipset)); - -//for now keeping it (need to get a system up and running to test.. - if (si->ps.card_arch >= NV50A) - { - LOG(8,("POWERUP: G80 and higher support not implemented: different architecture!\n")); - return B_ERROR; - } - - /* setup cardspecs */ - /* note: - * this MUST be done before the driver attempts a card coldstart */ - set_specs(); - - /* only process BIOS for finetuning specs and coldstarting card if requested - * by the user; - * note: - * this in fact frees the driver from relying on the BIOS to be executed - * at system power-up POST time. */ - if (!si->settings.usebios) - { - LOG(2, ("INIT: Attempting card coldstart!\n")); - /* update the cardspecs in the shared_info PINS struct according to reported - * specs as much as is possible; - * this also coldstarts the card if possible (executes BIOS CMD script(s)) */ -// parse_pins(); - } - else - { - LOG(2, ("INIT: Skipping card coldstart!\n")); - } - -// unlock_card(); - - /* get RAM size and do fake panel startup (panel init code is still missing). */ -// fake_panel_start(); - - /* log the final card specifications */ - dump_pins(); - - /* dump config space as it is after a possible coldstart attempt */ - if (si->settings.logmask & 0x80000000) nv_dump_configuration_space(); - - /* setup CRTC and DAC functions access: determined in fake_panel_start */ - setup_virtualized_heads(si->ps.crtc2_prim); - - /* do powerup needed from pre-inited card state as done by system POST cardBIOS - * execution or driver coldstart above */ - return nv_general_bios_to_powergraphics(); -} - -/* this routine switches the CRTC/DAC sets to 'connectors', but only for analog - * outputs. We need this to make sure the analog 'switch' is set in the same way the - * digital 'switch' is set by the BIOS or we might not be able to use dualhead. */ -status_t nv_general_output_select(bool cross) -{ - /* make sure this call is warranted */ - if (si->ps.secondary_head) - { - if (cross) - { - LOG(4,("INIT: switching analog outputs to be cross-connected\n")); - - /* enable head 2 on connector 1 */ - /* (b8 = select CRTC (head) for output, - * b4 = ??? (confirmed not to be a FP switch), - * b0 = enable CRT) */ - DACW(OUTPUT, 0x00000101); - /* enable head 1 on connector 2 */ - DAC2W(OUTPUT, 0x00000001); - } - else - { - LOG(4,("INIT: switching analog outputs to be straight-through\n")); - - /* enable head 1 on connector 1 */ - DACW(OUTPUT, 0x00000001); - /* enable head 2 on connector 2 */ - DAC2W(OUTPUT, 0x00000101); - } - return B_OK; - } - else - { - return B_ERROR; - } -} - -/* this routine switches CRTC/DAC set use. We need this because it's unknown howto - * switch digital panels to/from a specific CRTC/DAC set. */ -status_t nv_general_head_select(bool cross) -{ - /* make sure this call is warranted */ - if (si->ps.secondary_head) - { - /* invert CRTC/DAC use to do switching */ - if (cross) - { - LOG(4,("INIT: switching CRTC/DAC use to be cross-connected\n")); - si->crtc_switch_mode = !si->ps.crtc2_prim; - } - else - { - LOG(4,("INIT: switching CRTC/DAC use to be straight-through\n")); - si->crtc_switch_mode = si->ps.crtc2_prim; - } - /* update CRTC and DAC functions access */ - setup_virtualized_heads(si->crtc_switch_mode); - - return B_OK; - } - else - { - return B_ERROR; - } -} - -static void unlock_card(void) -{ - /* power-up all nvidia hardware function blocks */ - /* bit 28: OVERLAY ENGINE (BES), - * bit 25: CRTC2, (> NV04A) - * bit 24: CRTC1, - * bit 20: framebuffer, - * bit 16: PPMI, - * bit 12: PGRAPH, - * bit 8: PFIFO, - * bit 4: PMEDIA, - * bit 0: TVOUT. (> NV04A) */ - NV_REG32(NV32_PWRUPCTRL) = 0x13111111; - - /* select colormode CRTC registers base adresses */ - NV_REG8(NV8_MISCW) = 0xcb; - - /* enable access to primary head */ - set_crtc_owner(0); - /* unlock head's registers for R/W access */ - CRTCW(LOCK, 0x57); - CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f)); - if (si->ps.secondary_head) - { - /* enable access to secondary head */ - set_crtc_owner(1); - /* unlock head's registers for R/W access */ - CRTC2W(LOCK, 0x57); - CRTC2W(VSYNCE ,(CRTCR(VSYNCE) & 0x7f)); - } -} - -/* basic change of card state from VGA to enhanced mode: - * Should work from VGA BIOS POST init state. */ -static status_t nv_general_bios_to_powergraphics() -{ -return B_OK; - /* let acc engine make power off/power on cycle to start 'fresh' */ - NV_REG32(NV32_PWRUPCTRL) = 0x13110011; - snooze(1000); - NV_REG32(NV32_PWRUPCTRL) = 0x13111111; - - unlock_card(); - - /* turn off both displays and the hardcursors (also disables transfers) */ - head1_dpms(false, false, false, true); - head1_cursor_hide(); - if (si->ps.secondary_head) - { - head2_dpms(false, false, false, true); - head2_cursor_hide(); - } - - if (si->ps.secondary_head) - { - /* switch overlay engine and TV encoder to CRTC1 */ - /* bit 17: GPU FP port #1 (confirmed NV25, NV28, confirmed not on NV34), - * bit 16: GPU FP port #2 (confirmed NV25, NV28, NV34), - * bit 12: overlay engine (all cards), - * bit 9: TVout chip #2 (confirmed on NV18, NV25, NV28), - * bit 8: TVout chip #1 (all cards), - * bit 4: both I2C busses (all cards) */ - NV_REG32(NV32_2FUNCSEL) &= ~0x00001100; - NV_REG32(NV32_FUNCSEL) |= 0x00001100; - } - - /* enable 'enhanced' mode on primary head: */ - /* enable access to primary head */ - set_crtc_owner(0); - /* note: 'BUFFER' is a non-standard register in behaviour(!) on most - * NV11's like the GeForce2 MX200, while the MX400 and non-NV11 cards - * behave normally. - * Also readback is not nessesarily what was written before! - * - * Double-write action needed on those strange NV11 cards: */ - /* RESET: don't doublebuffer CRTC access: set programmed values immediately... */ - CRTCW(BUFFER, 0xff); - /* ... and use fine pitched CRTC granularity on > NV4 cards (b2 = 0) */ - /* note: this has no effect on possible bandwidth issues. */ - CRTCW(BUFFER, 0xfb); - /* select VGA mode (old VGA register) */ - CRTCW(MODECTL, 0xc3); - /* select graphics mode (old VGA register) */ - SEQW(MEMMODE, 0x0e); - /* select 8 dots character clocks (old VGA register) */ - SEQW(CLKMODE, 0x21); - /* select VGA mode (old VGA register) */ - GRPHW(MODE, 0x00); - /* select graphics mode (old VGA register) */ - GRPHW(MISC, 0x01); - /* select graphics mode (old VGA register) */ - ATBW(MODECTL, 0x01); - /* enable 'enhanced mode', enable Vsync & Hsync, - * set DAC palette to 8-bit width, disable large screen */ - CRTCW(REPAINT1, 0x04); - - /* enable 'enhanced' mode on secondary head: */ - if (si->ps.secondary_head) - { - /* enable access to secondary head */ - set_crtc_owner(1); - /* select colormode CRTC2 registers base adresses */ - NV_REG8(NV8_MISCW) = 0xcb; - /* note: 'BUFFER' is a non-standard register in behaviour(!) on most - * NV11's like the GeForce2 MX200, while the MX400 and non-NV11 cards - * behave normally. - * Also readback is not nessesarily what was written before! - * - * Double-write action needed on those strange NV11 cards: */ - /* RESET: don't doublebuffer CRTC2 access: set programmed values immediately... */ - CRTC2W(BUFFER, 0xff); - /* ... and use fine pitched CRTC granularity on > NV4 cards (b2 = 0) */ - /* note: this has no effect on possible bandwidth issues. */ - CRTC2W(BUFFER, 0xfb); - /* select VGA mode (old VGA register) */ - CRTC2W(MODECTL, 0xc3); - /* select graphics mode (old VGA register) */ - SEQW(MEMMODE, 0x0e); - /* select 8 dots character clocks (old VGA register) */ - SEQW(CLKMODE, 0x21); - /* select VGA mode (old VGA register) */ - GRPHW(MODE, 0x00); - /* select graphics mode (old VGA register) */ - GRPHW(MISC, 0x01); - /* select graphics mode (old VGA register) */ - ATB2W(MODECTL, 0x01); - /* enable 'enhanced mode', enable Vsync & Hsync, - * set DAC palette to 8-bit width, disable large screen */ - CRTC2W(REPAINT1, 0x04); - } - - /* enable palettes */ - DACW(GENCTRL, 0x00100100); - if (si->ps.secondary_head) DAC2W(GENCTRL, 0x00100100); - - /* enable programmable PLLs */ - /* (confirmed PLLSEL to be a write-only register on NV04 and NV11!) */ - if (si->ps.secondary_head) - DACW(PLLSEL, 0x30000f00); - else - DACW(PLLSEL, 0x10000700); - - /* turn on DAC and make sure detection testsignal routing is disabled - * (b16 = disable DAC, - * b12 = enable testsignal output */ - //fixme note: b20 ('DACTM_TEST') when set apparantly blocks a DAC's video output - //(confirmed NV43), while it's timing remains operational (black screen). - //It feels like in some screen configurations it can move the output to the other - //output connector as well... - DACW(TSTCTRL, (DACR(TSTCTRL) & 0xfffeefff)); - /* turn on DAC2 if it exists - * (NOTE: testsignal function block resides in DAC1 only (!)) */ - if (si->ps.secondary_head) DAC2W(TSTCTRL, (DAC2R(TSTCTRL) & 0xfffeefff)); - - /* NV40 and NV45 need a 'tweak' to make sure the CRTC FIFO's/shiftregisters get - * their data in time (otherwise momentarily ghost images of windows or such - * may appear on heavy acceleration engine use for instance, especially in 32-bit - * colordepth) */ - if ((si->ps.card_type == NV40) || (si->ps.card_type == NV45)) - { - /* clear b15: some framebuffer config item (unknown) */ - NV_REG32(NV32_PFB_CLS_PAGE2) &= 0xffff7fff; - } - - /* tweak card GPU-core and RAM speeds if requested (hoping we'll survive)... */ - if (si->settings.gpu_clk) - { - LOG(2,("INIT: tweaking GPU clock!\n")); - - set_pll(NV32_COREPLL, si->settings.gpu_clk); - snooze(1000); - } - if (si->settings.ram_clk) - { - LOG(2,("INIT: tweaking cardRAM clock!\n")); - - set_pll(NV32_MEMPLL, si->settings.ram_clk); - snooze(1000); - } - - return B_OK; -} - -/* Check if mode virtual_size adheres to the cards _maximum_ contraints, and modify - * virtual_size to the nearest valid maximum for the mode on the card if not so. - * Also: check if virtual_width adheres to the cards granularity constraints, and - * create mode slopspace if not so. - * We use acc or crtc granularity constraints based on the 'worst case' scenario. - * - * Mode slopspace is reflected in fbc->bytes_per_row BTW. */ -status_t nv_general_validate_pic_size (display_mode *target, uint32 *bytes_per_row, bool *acc_mode) -{ - uint32 video_pitch; - uint32 acc_mask, crtc_mask; - uint32 max_crtc_width, max_acc_width; - uint8 depth = 8; - - /* determine pixel multiple based on acceleration engine constraints */ - /* note: - * because of the seemingly 'random' variations in these constraints we take - * a reasonable 'lowest common denominator' instead of always true constraints. */ - - /* confirmed for: - * GeForce4 Ti4200 (NV28), GeForceFX 5600 (NV31) in PIO acc mode; - * confirmed for: - * GeForce2 MX400 (NV11), GeForce4 MX440 (NV18), GeForcePCX 5750 (NV36), - * GeForcePCX 6600 GT (NV43) in DMA acc mode. */ - switch (target->space) - { - case B_CMAP8: acc_mask = 0x3f; depth = 8; break; - case B_RGB15: acc_mask = 0x1f; depth = 16; break; - case B_RGB16: acc_mask = 0x1f; depth = 16; break; - case B_RGB24: acc_mask = 0x3f; depth = 24; break; - case B_RGB32: acc_mask = 0x0f; depth = 32; break; - default: - LOG(8,("INIT: unknown color space: 0x%08x\n", target->space)); - return B_ERROR; - } - - /* determine pixel multiple based on CRTC memory pitch constraints: - * -> all NV cards have same granularity constraints on CRTC1 and CRTC2, - * provided that the CRTC1 and CRTC2 BUFFER register b2 = 0; - * - * (Note: Don't mix this up with CRTC timing contraints! Those are - * multiples of 8 for horizontal, 1 for vertical timing.) */ - switch (si->ps.card_type) - { - default: -// case NV04: - /* confirmed for: - * TNT1 always; - * TNT2, TNT2-M64, GeForce2 MX400, GeForce4 MX440, GeForce4 Ti4200, - * GeForceFX 5200: if the CRTC1 (and CRTC2) BUFFER register b2 = 0 */ - /* NOTE: - * Unfortunately older cards have a hardware fault that prevents use. - * We need doubled granularity on those to prevent the single top line - * from shifting to the left! - * This is confirmed for TNT2, GeForce2 MX200, GeForce2 MX400. - * Confirmed OK are: - * GeForce4 MX440, GeForce4 Ti4200, GeForceFX 5200. */ - switch (target->space) - { - case B_CMAP8: crtc_mask = 0x0f; break; /* 0x07 */ - case B_RGB15: crtc_mask = 0x07; break; /* 0x03 */ - case B_RGB16: crtc_mask = 0x07; break; /* 0x03 */ - case B_RGB24: crtc_mask = 0x0f; break; /* 0x07 */ - case B_RGB32: crtc_mask = 0x03; break; /* 0x01 */ - default: - LOG(8,("INIT: unknown color space: 0x%08x\n", target->space)); - return B_ERROR; - } - break; -// default: - /* confirmed for: - * TNT2, TNT2-M64, GeForce2 MX400, GeForce4 MX440, GeForce4 Ti4200, - * GeForceFX 5200: if the CRTC1 (and CRTC2) BUFFER register b2 = 1 */ -/* switch (target->space) - { - case B_CMAP8: crtc_mask = 0x1f; break; - case B_RGB15: crtc_mask = 0x0f; break; - case B_RGB16: crtc_mask = 0x0f; break; - case B_RGB24: crtc_mask = 0x1f; break; - case B_RGB32: crtc_mask = 0x07; break; - default: - LOG(8,("INIT: unknown color space: 0x%08x\n", target->space)); - return B_ERROR; - } - break; -*/ } - - /* set virtual_width limit for accelerated modes */ - /* note: - * because of the seemingly 'random' variations in these constraints we take - * a reasonable 'lowest common denominator' instead of always true constraints. */ - - /* confirmed for: - * GeForce4 Ti4200 (NV28), GeForceFX 5600 (NV31) in PIO acc mode; - * GeForce2 MX400 (NV11), GeForce4 MX440 (NV18), GeForceFX 5200 (NV34) can do - * 16368/8184/8184/5456/4092, so a bit better in PIO acc mode; - * confirmed for: - * GeForce2 MX400 (NV11), GeForce4 MX440 (NV18), GeForcePCX 5750 (NV36), - * GeForcePCX 6600 GT (NV43) in DMA acc mode; - * GeForce4 Ti4200 (NV28), GeForceFX 5200 (NV34) can do - * 16368/8184/8184/5456/4092, so a bit better in DMA acc mode. */ - switch(target->space) - { - case B_CMAP8: max_acc_width = 16320; break; - case B_RGB15: max_acc_width = 8160; break; - case B_RGB16: max_acc_width = 8160; break; - case B_RGB24: max_acc_width = 5440; break; - case B_RGB32: max_acc_width = 4080; break; - default: - LOG(8,("INIT: unknown color space: 0x%08x\n", target->space)); - return B_ERROR; - } - - /* set virtual_width limit for unaccelerated modes */ - switch (si->ps.card_type) - { - default: -// case NV04: - /* confirmed for: - * TNT1 always; - * TNT2, TNT2-M64, GeForce2 MX400, GeForce4 MX440, GeForce4 Ti4200, - * GeForceFX 5200: if the CRTC1 (and CRTC2) BUFFER register b2 = 0 */ - /* NOTE: - * Unfortunately older cards have a hardware fault that prevents use. - * We need doubled granularity on those to prevent the single top line - * from shifting to the left! - * This is confirmed for TNT2, GeForce2 MX200, GeForce2 MX400. - * Confirmed OK are: - * GeForce4 MX440, GeForce4 Ti4200, GeForceFX 5200. */ - switch(target->space) - { - case B_CMAP8: max_crtc_width = 16368; break; /* 16376 */ - case B_RGB15: max_crtc_width = 8184; break; /* 8188 */ - case B_RGB16: max_crtc_width = 8184; break; /* 8188 */ - case B_RGB24: max_crtc_width = 5456; break; /* 5456 */ - case B_RGB32: max_crtc_width = 4092; break; /* 4094 */ - default: - LOG(8,("INIT: unknown color space: 0x%08x\n", target->space)); - return B_ERROR; - } - break; -// default: - /* confirmed for: - * TNT2, TNT2-M64, GeForce2 MX400, GeForce4 MX440, GeForce4 Ti4200, - * GeForceFX 5200: if the CRTC1 (and CRTC2) BUFFER register b2 = 1 */ -/* switch(target->space) - { - case B_CMAP8: max_crtc_width = 16352; break; - case B_RGB15: max_crtc_width = 8176; break; - case B_RGB16: max_crtc_width = 8176; break; - case B_RGB24: max_crtc_width = 5440; break; - case B_RGB32: max_crtc_width = 4088; break; - default: - LOG(8,("INIT: unknown color space: 0x%08x\n", target->space)); - return B_ERROR; - } - break; -*/ } - - /* check for acc capability, and adjust mode to adhere to hardware constraints */ - if (max_acc_width <= max_crtc_width) - { - /* check if we can setup this mode with acceleration */ - *acc_mode = true; - //no acc support for G8x yet! - if (si->ps.card_arch >= NV50A) *acc_mode = false; - - /* virtual_width */ - if (target->virtual_width > max_acc_width) *acc_mode = false; - /* virtual_height */ - /* (NV cards can even do more than this(?)... - * but 4096 is confirmed on all cards at max. accelerated width.) */ - if (target->virtual_height > 4096) *acc_mode = false; - - /* now check virtual_size based on CRTC constraints */ - if (target->virtual_width > max_crtc_width) target->virtual_width = max_crtc_width; - /* virtual_height: The only constraint here is the cards memory size which is - * checked later on in ProposeMode: virtual_height is adjusted then if needed. - * 'Limiting here' to the variable size that's at least available (uint16). */ - if (target->virtual_height > 65535) target->virtual_height = 65535; - - /* OK, now we know that virtual_width is valid, and it's needing no slopspace if - * it was confined above, so we can finally calculate safely if we need slopspace - * for this mode... */ - if (*acc_mode) - { - /* the mode needs to adhere to the largest granularity imposed... */ - if (acc_mask < crtc_mask) - video_pitch = ((target->virtual_width + crtc_mask) & ~crtc_mask); - else - video_pitch = ((target->virtual_width + acc_mask) & ~acc_mask); - } - else /* unaccelerated mode */ - video_pitch = ((target->virtual_width + crtc_mask) & ~crtc_mask); - } - else /* max_acc_width > max_crtc_width */ - { - /* check if we can setup this mode with acceleration */ - *acc_mode = true; - //no acc support for G8x yet! - if (si->ps.card_arch >= NV50A) *acc_mode = false; - /* (we already know virtual_width will be no problem) */ - /* virtual_height */ - /* (NV cards can even do more than this(?)... - * but 4096 is confirmed on all cards at max. accelerated width.) */ - if (target->virtual_height > 4096) *acc_mode = false; - - /* now check virtual_size based on CRTC constraints */ - if (*acc_mode) - { - /* note that max_crtc_width already adheres to crtc_mask */ - if (target->virtual_width > (max_crtc_width & ~acc_mask)) - target->virtual_width = (max_crtc_width & ~acc_mask); - } - else /* unaccelerated mode */ - { - if (target->virtual_width > max_crtc_width) - target->virtual_width = max_crtc_width; - } - /* virtual_height: The only constraint here is the cards memory size which is - * checked later on in ProposeMode: virtual_height is adjusted then if needed. - * 'Limiting here' to the variable size that's at least available (uint16). */ - if (target->virtual_height > 65535) target->virtual_height = 65535; - - /* OK, now we know that virtual_width is valid, and it's needing no slopspace if - * it was confined above, so we can finally calculate safely if we need slopspace - * for this mode... */ - if (*acc_mode) - { - /* the mode needs to adhere to the largest granularity imposed... */ - if (acc_mask < crtc_mask) - video_pitch = ((target->virtual_width + crtc_mask) & ~crtc_mask); - else - video_pitch = ((target->virtual_width + acc_mask) & ~acc_mask); - } - else /* unaccelerated mode */ - video_pitch = ((target->virtual_width + crtc_mask) & ~crtc_mask); - } - - LOG(2,("INIT: memory pitch will be set to %d pixels for colorspace 0x%08x\n", - video_pitch, target->space)); - if (target->virtual_width != video_pitch) - LOG(2,("INIT: effective mode slopspace is %d pixels\n", - (video_pitch - target->virtual_width))); - - /* now calculate bytes_per_row for this mode */ - *bytes_per_row = video_pitch * (depth >> 3); - - return B_OK; -} diff --git a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_globals.c b/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_globals.c deleted file mode 100644 index 18905a9aab..0000000000 --- a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_globals.c +++ /dev/null @@ -1,36 +0,0 @@ -/* - Copyright 1999, Be Incorporated. All Rights Reserved. - This file may be used under the terms of the Be Sample Code License. - - Other authors: - Mark Watson, - Rudolf Cornelissen 8/2004-5/2005 -*/ - -#include "nv_std.h" - -int fd; -shared_info *si; -area_id shared_info_area; -area_id dma_cmd_buf_area; -vuint32 *regs; -area_id regs_area; -display_mode *my_mode_list; -area_id my_mode_list_area; -int accelerantIsClone; - -nv_get_set_pci nv_pci_access= - { - NV_PRIVATE_DATA_MAGIC, - 0, - 4, - 0 - }; - -nv_in_out_isa nv_isa_access= - { - NV_PRIVATE_DATA_MAGIC, - 0, - 1, - 0 - }; diff --git a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_globals.h b/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_globals.h deleted file mode 100644 index 8c51383865..0000000000 --- a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_globals.h +++ /dev/null @@ -1,69 +0,0 @@ -extern int fd; -extern shared_info *si; -extern area_id shared_info_area; -extern area_id dma_cmd_buf_area; -extern area_id regs_area; -extern vuint32 *regs; -extern display_mode *my_mode_list; -extern area_id my_mode_list_area; -extern int accelerantIsClone; - -extern nv_get_set_pci nv_pci_access; -extern nv_in_out_isa nv_isa_access; - -typedef status_t (*crtc_interrupt_enable)(bool); -typedef status_t (*crtc_update_fifo)(void); -typedef status_t (*crtc_validate_timing)(uint16*, uint16*, uint16*, uint16*, uint16*, uint16*, uint16*, uint16*); -typedef status_t (*crtc_set_timing)(display_mode); -typedef status_t (*crtc_depth)(int); -typedef status_t (*crtc_dpms)(bool, bool, bool, bool); -typedef status_t (*crtc_set_display_pitch)(void); -typedef status_t (*crtc_set_display_start)(uint32, uint8); -typedef status_t (*crtc_cursor_init)(void); -typedef status_t (*crtc_cursor_show)(void); -typedef status_t (*crtc_cursor_hide)(void); -typedef status_t (*crtc_cursor_define)(uint8*, uint8*); -typedef status_t (*crtc_cursor_position)(uint16, uint16); - -typedef status_t (*dac_mode)(int, float); -typedef status_t (*dac_palette)(uint8[256], uint8[256], uint8[256]); -typedef status_t (*dac_set_pix_pll)(display_mode); -typedef status_t (*dac_pix_pll_find)(display_mode, float*, uint8*, uint8*, uint8*, uint8); - -crtc_interrupt_enable head1_interrupt_enable; -crtc_update_fifo head1_update_fifo; -crtc_validate_timing head1_validate_timing; -crtc_set_timing head1_set_timing; -crtc_depth head1_depth; -crtc_dpms head1_dpms; -crtc_set_display_pitch head1_set_display_pitch; -crtc_set_display_start head1_set_display_start; -crtc_cursor_init head1_cursor_init; -crtc_cursor_show head1_cursor_show; -crtc_cursor_hide head1_cursor_hide; -crtc_cursor_define head1_cursor_define; -crtc_cursor_position head1_cursor_position; - -crtc_interrupt_enable head2_interrupt_enable; -crtc_update_fifo head2_update_fifo; -crtc_validate_timing head2_validate_timing; -crtc_set_timing head2_set_timing; -crtc_depth head2_depth; -crtc_dpms head2_dpms; -crtc_set_display_pitch head2_set_display_pitch; -crtc_set_display_start head2_set_display_start; -crtc_cursor_init head2_cursor_init; -crtc_cursor_show head2_cursor_show; -crtc_cursor_hide head2_cursor_hide; -crtc_cursor_define head2_cursor_define; -crtc_cursor_position head2_cursor_position; - -dac_mode head1_mode; -dac_palette head1_palette; -dac_set_pix_pll head1_set_pix_pll; -dac_pix_pll_find head1_pix_pll_find; - -dac_mode head2_mode; -dac_palette head2_palette; -dac_set_pix_pll head2_set_pix_pll; -dac_pix_pll_find head2_pix_pll_find; diff --git a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_i2c.c b/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_i2c.c deleted file mode 100644 index 1106604377..0000000000 --- a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_i2c.c +++ /dev/null @@ -1,344 +0,0 @@ -/* - * i2c interface. - * Bus should be run at max. 100kHz: see original Philips I2C specification - * - * Rudolf Cornelissen 12/2002-10/2005 - */ - -#define MODULE_BIT 0x00004000 - -#include "nv_std.h" - -char i2c_flag_error (char ErrNo) -//error code list: -//0 - OK status -//1 - SCL locked low by device (bus is still busy) -//2 - SDA locked low by device (bus is still busy) -//3 - No Acknowledge from device (no handshake) -//4 - SDA not released for master to generate STOP bit -{ - static char I2CError = 0; - - if (!I2CError) I2CError = ErrNo; - if (ErrNo == -1) I2CError = 0; - return I2CError; -} - -static void i2c_select_bus_set(bool set) -{ - /* I/O pins set selection is only valid on dualhead cards */ - if (!si->ps.secondary_head) return; - - /* select GPU I/O pins set to connect to I2C 'registers' */ - if (set) - { - NV_REG32(NV32_FUNCSEL) &= ~0x00000010; - NV_REG32(NV32_2FUNCSEL) |= 0x00000010; - } - else - { - NV_REG32(NV32_2FUNCSEL) &= ~0x00000010; - NV_REG32(NV32_FUNCSEL) |= 0x00000010; - } -} - -static void OutSCL(uint8 BusNR, bool Bit) -{ - uint8 data; - - if (BusNR & 0x01) - { - data = (CRTCR(WR_I2CBUS_1) & 0xf0) | 0x01; - if (Bit) - CRTCW(WR_I2CBUS_1, (data | 0x20)); - else - CRTCW(WR_I2CBUS_1, (data & ~0x20)); - } - else - { - data = (CRTCR(WR_I2CBUS_0) & 0xf0) | 0x01; - if (Bit) - CRTCW(WR_I2CBUS_0, (data | 0x20)); - else - CRTCW(WR_I2CBUS_0, (data & ~0x20)); - } -} - -static void OutSDA(uint8 BusNR, bool Bit) -{ - uint8 data; - - if (BusNR & 0x01) - { - data = (CRTCR(WR_I2CBUS_1) & 0xf0) | 0x01; - if (Bit) - CRTCW(WR_I2CBUS_1, (data | 0x10)); - else - CRTCW(WR_I2CBUS_1, (data & ~0x10)); - } - else - { - data = (CRTCR(WR_I2CBUS_0) & 0xf0) | 0x01; - if (Bit) - CRTCW(WR_I2CBUS_0, (data | 0x10)); - else - CRTCW(WR_I2CBUS_0, (data & ~0x10)); - } -} - -static bool InSCL(uint8 BusNR) -{ - if (BusNR & 0x01) - { - if ((CRTCR(RD_I2CBUS_1) & 0x04)) return true; - } - else - { - if ((CRTCR(RD_I2CBUS_0) & 0x04)) return true; - } - - return false; -} - -static bool InSDA(uint8 BusNR) -{ - if (BusNR & 0x01) - { - if ((CRTCR(RD_I2CBUS_1) & 0x08)) return true; - } - else - { - if ((CRTCR(RD_I2CBUS_0) & 0x08)) return true; - } - - return false; -} - -static void TXBit (uint8 BusNR, bool Bit) -{ - /* send out databit */ - if (Bit) - { - OutSDA(BusNR, true); - snooze(3); - if (!InSDA(BusNR)) i2c_flag_error (2); - } - else - { - OutSDA(BusNR, false); - } - /* generate clock pulse */ - snooze(6); - OutSCL(BusNR, true); - snooze(3); - if (!InSCL(BusNR)) i2c_flag_error (1); - snooze(6); - OutSCL(BusNR, false); - snooze(6); -} - -static uint8 RXBit (uint8 BusNR) -{ - uint8 Bit = 0; - - /* set SDA so input is possible */ - OutSDA(BusNR, true); - /* generate clock pulse */ - snooze(6); - OutSCL(BusNR, true); - snooze(3); - if (!InSCL(BusNR)) i2c_flag_error (1); - snooze(3); - /* read databit */ - if (InSDA(BusNR)) Bit = 1; - /* finish clockpulse */ - OutSCL(BusNR, false); - snooze(6); - - return Bit; -} - -void i2c_bstart (uint8 BusNR) -{ - /* select GPU I/O pins set */ - i2c_select_bus_set(BusNR & 0x02); - - /* enable access to primary head */ - set_crtc_owner(0); - - /* make sure SDA is high */ - OutSDA(BusNR, true); - snooze(3); - OutSCL(BusNR, true); - snooze(3); - if (!InSCL(BusNR)) i2c_flag_error (1); - snooze(6); - /* clear SDA while SCL set (bus-start condition) */ - OutSDA(BusNR, false); - snooze(6); - OutSCL(BusNR, false); - snooze(6); - - LOG(4,("I2C: START condition generated on bus %d; status is %d\n", - BusNR, i2c_flag_error (0))); -} - -void i2c_bstop (uint8 BusNR) -{ - /* select GPU I/O pins set */ - i2c_select_bus_set(BusNR & 0x02); - - /* enable access to primary head */ - set_crtc_owner(0); - - /* make sure SDA is low */ - OutSDA(BusNR, false); - snooze(3); - OutSCL(BusNR, true); - snooze(3); - if (!InSCL(BusNR)) i2c_flag_error (1); - snooze(6); - /* set SDA while SCL set (bus-stop condition) */ - OutSDA(BusNR, true); - snooze(3); - if (!InSDA(BusNR)) i2c_flag_error (4); - snooze(3); - - LOG(4,("I2C: STOP condition generated on bus %d; status is %d\n", - BusNR, i2c_flag_error (0))); -} - -uint8 i2c_readbyte(uint8 BusNR, bool Ack) -{ - uint8 cnt, bit, byte = 0; - - /* select GPU I/O pins set */ - i2c_select_bus_set(BusNR & 0x02); - - /* enable access to primary head */ - set_crtc_owner(0); - - /* read data */ - for (cnt = 8; cnt > 0; cnt--) - { - byte <<= 1; - bit = RXBit (BusNR); - byte += bit; - } - /* send acknowledge */ - TXBit (BusNR, Ack); - - LOG(4,("I2C: read byte ($%02x) from bus #%d; status is %d\n", - byte, BusNR, i2c_flag_error(0))); - - return byte; -} - -bool i2c_writebyte (uint8 BusNR, uint8 byte) -{ - uint8 cnt; - bool bit; - uint8 tmp = byte; - - /* select GPU I/O pins set */ - i2c_select_bus_set(BusNR & 0x02); - - /* enable access to primary head */ - set_crtc_owner(0); - - /* write data */ - for (cnt = 8; cnt > 0; cnt--) - { - bit = (tmp & 0x80); - TXBit (BusNR, bit); - tmp <<= 1; - } - /* read acknowledge */ - bit = RXBit (BusNR); - if (bit) i2c_flag_error (3); - - LOG(4,("I2C: written byte ($%02x) to bus #%d; status is %d\n", - byte, BusNR, i2c_flag_error(0))); - - return bit; -} - -void i2c_readbuffer (uint8 BusNR, uint8* buf, uint8 size) -{ - uint8 cnt; - - for (cnt = 0; cnt < size; cnt++) - { - buf[cnt] = i2c_readbyte(BusNR, buf[cnt]); - } -} - -void i2c_writebuffer (uint8 BusNR, uint8* buf, uint8 size) -{ - uint8 cnt; - - for (cnt = 0; cnt < size; cnt++) - { - i2c_writebyte(BusNR, buf[cnt]); - } -} - -status_t i2c_init(void) -{ - uint8 bus, buses; - bool *i2c_bus = &(si->ps.i2c_bus0); - status_t result = B_ERROR; - - LOG(4,("I2C: searching for wired I2C buses...\n")); - - /* enable access to primary head */ - set_crtc_owner(0); - - /* preset no board wired buses */ - si->ps.i2c_bus0 = false; - si->ps.i2c_bus1 = false; - si->ps.i2c_bus2 = false; - si->ps.i2c_bus3 = false; - - /* set number of buses to test for */ - buses = 2; - if (si->ps.secondary_head) buses = 4; - - /* find existing buses */ - for (bus = 0; bus < buses; bus++) - { - /* reset status */ - i2c_flag_error (-1); - snooze(6); - /* init and/or stop I2C bus */ - i2c_bstop(bus); - /* check for hardware coupling of SCL and SDA -out and -in lines */ - snooze(6); - OutSCL(bus, false); - OutSDA(bus, true); - snooze(3); - if (InSCL(bus) || !InSDA(bus)) continue; - snooze(3); - OutSCL(bus, true); - OutSDA(bus, false); - snooze(3); - if (!InSCL(bus) || InSDA(bus)) continue; - i2c_bus[bus] = true; - snooze(3); - /* re-init bus */ - i2c_bstop(bus); - } - - for (bus = 0; bus < buses; bus++) - { - if (i2c_bus[bus]) - { - LOG(4,("I2C: bus #%d wiring check: passed\n", bus)); - result = B_OK; - } - else - LOG(4,("I2C: bus #%d wiring check: failed\n", bus)); - } - - return result; -} diff --git a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_info.c b/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_info.c deleted file mode 100644 index f899a7ee50..0000000000 --- a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_info.c +++ /dev/null @@ -1,2692 +0,0 @@ -/* Read initialisation information from card */ -/* some bits are hacks, where PINS is not known */ -/* Author: - Rudolf Cornelissen 7/2003-6/2008 -*/ - -#define MODULE_BIT 0x00002000 - -#include "nv_std.h" - -/* pins V5.16 and up ROM infoblock stuff */ -typedef struct { - uint16 InitScriptTablePtr; /* ptr to list of ptrs to scripts to exec */ - uint16 MacroIndexTablePtr; /* ptr to list with indexes and sizes of items in MacroTable */ - uint16 MacroTablePtr; /* ptr to list with items containing multiple 32bit reg writes */ - uint16 ConditionTablePtr; /* ptr to list of PCI regs and bits to tst for exec mode */ - uint16 IOConditionTablePtr; /* ptr to list of ISA regs and bits to tst for exec mode */ - uint16 IOFlagConditionTablePtr;/* ptr to list of ISA regs and bits to tst, ref'd to a matrix, for exec mode */ - uint16 InitFunctionTablePtr; /* ptr to list of startadresses of fixed ROM init routines */ -} PinsTables; - -static void detect_panels(void); -static void setup_output_matrix(void); - -static void pinsnv30_arch_fake(void); -static void getRAMsize_arch_nv10_20_30_40(void); -static void getstrap_arch_nv10_20_30_40(void); -static status_t pins2_read(uint8 *rom, uint32 offset); -static status_t pins3_5_read(uint8 *rom, uint32 offset); -static status_t coldstart_card(uint8* rom, uint16 init1, uint16 init2, uint16 init_size, uint16 ram_tab); -static status_t coldstart_card_516_up(uint8* rom, PinsTables tabs, uint16 ram_tab); -static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16 ram_tab); -static status_t exec_type2_script(uint8* rom, uint16 adress, int16* size, PinsTables tabs, uint16 ram_tab); -static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size, PinsTables tabs, uint16 ram_tab, bool* exec); -static void exec_cmd_39_type2(uint8* rom, uint32 data, PinsTables tabs, bool* exec); -static void log_pll(uint32 reg, uint32 freq); -static void setup_ram_config(uint8* rom, uint16 ram_tab); -static void setup_ram_config_nv10_up(uint8* rom); -static status_t translate_ISA_PCI(uint32* reg); -static status_t nv_crtc_setup_fifo(void); - -/* Parse the BIOS PINS structure if there */ -status_t parse_pins () -{ - uint8 *rom; - uint8 chksum = 0; - int i; - uint32 offset; - status_t result = B_ERROR; - - /* preset PINS read status to failed */ - si->ps.pins_status = B_ERROR; - - /* check the validity of PINS */ - LOG(2,("INFO: Reading PINS info\n")); - rom = (uint8 *) si->rom_mirror; - /* check BIOS signature - this is defined in the PCI standard */ - if (rom[0]!=0x55 || rom[1]!=0xaa) - { - LOG(8,("INFO: BIOS signature not found\n")); - return B_ERROR; - } - LOG(2,("INFO: BIOS signature $AA55 found OK\n")); - - /* find the PINS struct adress */ - for (offset = 0; offset < 65536; offset++) - { - if (rom[offset ] != 0xff) continue; - if (rom[offset + 1] != 0x7f) continue; - if (rom[offset + 2] != 0x4e) continue; /* N */ - if (rom[offset + 3] != 0x56) continue; /* V */ - if (rom[offset + 4] != 0x00) continue; - - LOG(8,("INFO: PINS signature found\n")); - break; - } - - if (offset > 65535) - { - LOG(8,("INFO: PINS signature not found\n")); - return B_ERROR; - } - - /* verify PINS checksum */ - for (i = 0; i < 8; i++) - { - chksum += rom[offset + i]; - } - if (chksum) - { - LOG(8,("INFO: PINS checksum error\n")); - return B_ERROR; - } - - /* checkout PINS struct version */ - LOG(2,("INFO: PINS checksum is OK; PINS version is %d.%d\n", - rom[offset + 5], rom[offset + 6])); - - /* update the si->ps struct as far as is possible and coldstart card */ - //fixme: NV40 and up(?) nolonger use this system... - switch (rom[offset + 5]) - { - case 2: - result = pins2_read(rom, offset); - break; - case 3: - case 4: - case 5: - result = pins3_5_read(rom, offset); - break; - default: - LOG(8,("INFO: unknown PINS version\n")); - return B_ERROR; - break; - } - - /* check PINS read result */ - if (result == B_ERROR) - { - LOG(8,("INFO: PINS read/decode/execute error\n")); - return B_ERROR; - } - /* PINS scan succeeded */ - si->ps.pins_status = B_OK; - LOG(2,("INFO: PINS scan completed succesfully\n")); - return B_OK; -} - -static status_t pins2_read(uint8 *rom, uint32 offset) -{ - uint16 init1 = rom[offset + 18] + (rom[offset + 19] * 256); - uint16 init2 = rom[offset + 20] + (rom[offset + 21] * 256); - uint16 init_size = rom[offset + 22] + (rom[offset + 23] * 256) + 1; - /* confirmed by comparing cards */ - uint16 ram_tab = init1 - 0x0010; - /* fixme: PPC BIOSes (might) return NULL pointers for messages here */ - char* signon_msg = &(rom[(rom[offset + 24] + (rom[offset + 25] * 256))]); - char* vendor_name = &(rom[(rom[offset + 40] + (rom[offset + 41] * 256))]); - char* product_name = &(rom[(rom[offset + 42] + (rom[offset + 43] * 256))]); - char* product_rev = &(rom[(rom[offset + 44] + (rom[offset + 45] * 256))]); - - LOG(8,("INFO: cmdlist 1: $%04x, 2: $%04x, max. size $%04x\n", init1, init2, init_size)); - LOG(8,("INFO: signon msg:\n%s\n", signon_msg)); - LOG(8,("INFO: vendor name: %s\n", vendor_name)); - LOG(8,("INFO: product name: %s\n", product_name)); - LOG(8,("INFO: product rev: %s\n", product_rev)); - - return coldstart_card(rom, init1, init2, init_size, ram_tab); -} - -static status_t pins3_5_read(uint8 *rom, uint32 offset) -{ - uint16 init1 = rom[offset + 18] + (rom[offset + 19] * 256); - uint16 init2 = rom[offset + 20] + (rom[offset + 21] * 256); - uint16 init_size = rom[offset + 22] + (rom[offset + 23] * 256) + 1; - /* confirmed on a TNT2-M64 with pins V5.1 */ - uint16 ram_tab = rom[offset + 24] + (rom[offset + 25] * 256); - /* fixme: PPC BIOSes (might) return NULL pointers for messages here */ - char* signon_msg = &(rom[(rom[offset + 30] + (rom[offset + 31] * 256))]); - char* vendor_name = &(rom[(rom[offset + 46] + (rom[offset + 47] * 256))]); - char* product_name = &(rom[(rom[offset + 48] + (rom[offset + 49] * 256))]); - char* product_rev = &(rom[(rom[offset + 50] + (rom[offset + 51] * 256))]); - - LOG(8,("INFO: pre PINS 5.16 cmdlist 1: $%04x, 2: $%04x, max. size $%04x\n", init1, init2, init_size)); - LOG(8,("INFO: signon msg:\n%s\n", signon_msg)); - LOG(8,("INFO: vendor name: %s\n", vendor_name)); - LOG(8,("INFO: product name: %s\n", product_name)); - LOG(8,("INFO: product rev: %s\n", product_rev)); - - /* pins 5.06 and higher has VCO range info */ - if (((rom[offset + 5]) == 5) && ((rom[offset + 6]) >= 0x06)) - { - /* get PLL VCO range info */ - uint32 fvco_max = *((uint32*)(&(rom[offset + 67]))); - uint32 fvco_min = *((uint32*)(&(rom[offset + 71]))); - - LOG(8,("INFO: PLL VCO range is %dkHz - %dkHz\n", fvco_min, fvco_max)); - - /* modify presets to reflect card capability */ - si->ps.min_system_vco = fvco_min / 1000; - si->ps.max_system_vco = fvco_max / 1000; - //fixme: enable and modify PLL code... - //si->ps.min_pixel_vco = fvco_min / 1000; - //si->ps.max_pixel_vco = fvco_max / 1000; - //si->ps.min_video_vco = fvco_min / 1000; - //si->ps.max_video_vco = fvco_max / 1000; - } - - //fixme: add 'parsing scripts while not actually executing' as warmstart method, - // instead of not parsing at all: this will update the driver's speeds - // as below, while logging the scripts as well (for our learning pleasure :) - - /* pins 5.16 and higher is more extensive, and works differently from before */ - if (((rom[offset + 5]) == 5) && ((rom[offset + 6]) >= 0x10)) - { - /* pins 5.16 and up have a more extensive command list table, and have more - * commands to choose from as well. */ - PinsTables tabs; - tabs.InitScriptTablePtr = rom[offset + 75] + (rom[offset + 76] * 256); - tabs.MacroIndexTablePtr = rom[offset + 77] + (rom[offset + 78] * 256); - tabs.MacroTablePtr = rom[offset + 79] + (rom[offset + 80] * 256); - tabs.ConditionTablePtr = rom[offset + 81] + (rom[offset + 82] * 256); - tabs.IOConditionTablePtr = rom[offset + 83] + (rom[offset + 84] * 256); - tabs.IOFlagConditionTablePtr = rom[offset + 85] + (rom[offset + 86] * 256); - tabs.InitFunctionTablePtr = rom[offset + 87] + (rom[offset + 88] * 256); - - LOG(8,("INFO: PINS 5.16 and later cmdlist pointers:\n")); - LOG(8,("INFO: InitScriptTablePtr: $%04x\n", tabs.InitScriptTablePtr)); - LOG(8,("INFO: MacroIndexTablePtr: $%04x\n", tabs.MacroIndexTablePtr)); - LOG(8,("INFO: MacroTablePtr: $%04x\n", tabs.MacroTablePtr)); - LOG(8,("INFO: ConditionTablePtr: $%04x\n", tabs.ConditionTablePtr)); - LOG(8,("INFO: IOConditionTablePtr: $%04x\n", tabs.IOConditionTablePtr)); - LOG(8,("INFO: IOFlagConditionTablePtr: $%04x\n", tabs.IOFlagConditionTablePtr)); - LOG(8,("INFO: InitFunctionTablePtr: $%04x\n", tabs.InitFunctionTablePtr)); - - return coldstart_card_516_up(rom, tabs, ram_tab); - } - else - { - /* pre 'pins 5.16' still uses the 'old' method in which the command list - * table always has two entries. */ - return coldstart_card(rom, init1, init2, init_size, ram_tab); - } -} - -static status_t coldstart_card(uint8* rom, uint16 init1, uint16 init2, uint16 init_size, uint16 ram_tab) -{ - status_t result = B_OK; - int16 size = init_size; - - LOG(8,("INFO: now executing coldstart...\n")); - - /* select colormode CRTC registers base adresses */ - NV_REG8(NV8_MISCW) = 0xcb; - - /* unknown.. */ - NV_REG8(NV8_VSE2) = 0x01; - - /* enable access to primary head */ - set_crtc_owner(0); - /* unlock head's registers for R/W access */ - CRTCW(LOCK, 0x57); - CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f)); - /* disable RMA as it's not used */ - /* (RMA is the cmd register for the 32bit port in the GPU to access 32bit registers - * and framebuffer via legacy ISA I/O space.) */ - CRTCW(RMA, 0x00); - - if (si->ps.secondary_head) - { - /* enable access to secondary head */ - set_crtc_owner(1); - /* unlock head's registers for R/W access */ - CRTC2W(LOCK, 0x57); - CRTC2W(VSYNCE ,(CRTCR(VSYNCE) & 0x7f)); - } - - /* turn off both displays and the hardcursors (also disables transfers) */ - nv_crtc_dpms(false, false, false, true); - nv_crtc_cursor_hide(); - if (si->ps.secondary_head) - { - nv_crtc2_dpms(false, false, false, true); - nv_crtc2_cursor_hide(); - } - - /* execute BIOS coldstart script(s) */ - if (init1 || init2) - { - if (init1) - if (exec_type1_script(rom, init1, &size, ram_tab) != B_OK) result = B_ERROR; - if (init2 && (result == B_OK)) - if (exec_type1_script(rom, init2, &size, ram_tab) != B_OK) result = B_ERROR; - - /* now enable ROM shadow or the card will remain shut-off! */ - CFGW(ROMSHADOW, (CFGR(ROMSHADOW) |= 0x00000001)); - - //temporary: should be called from setmode probably.. - nv_crtc_setup_fifo(); - } - else - { - result = B_ERROR; - } - - if (result != B_OK) - LOG(8,("INFO: coldstart failed.\n")); - else - LOG(8,("INFO: coldstart execution completed OK.\n")); - - return result; -} - -static status_t coldstart_card_516_up(uint8* rom, PinsTables tabs, uint16 ram_tab) -{ - status_t result = B_OK; - uint16 adress; - - LOG(8,("INFO: now executing coldstart...\n")); - - /* select colormode CRTC registers base adresses */ - NV_REG8(NV8_MISCW) = 0xcb; - - /* unknown.. */ - NV_REG8(NV8_VSE2) = 0x01; - - /* enable access to primary head */ - set_crtc_owner(0); - /* unlock head's registers for R/W access */ - CRTCW(LOCK, 0x57); - CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f)); - /* disable RMA as it's not used */ - /* (RMA is the cmd register for the 32bit port in the GPU to access 32bit registers - * and framebuffer via legacy ISA I/O space.) */ - CRTCW(RMA, 0x00); - - if (si->ps.secondary_head) - { - /* enable access to secondary head */ - set_crtc_owner(1); - /* unlock head's registers for R/W access */ - CRTC2W(LOCK, 0x57); - CRTC2W(VSYNCE ,(CRTCR(VSYNCE) & 0x7f)); - } - - /* turn off both displays and the hardcursors (also disables transfers) */ - nv_crtc_dpms(false, false, false, true); - nv_crtc_cursor_hide(); - if (si->ps.secondary_head) - { - nv_crtc2_dpms(false, false, false, true); - nv_crtc2_cursor_hide(); - } - - /* execute all BIOS coldstart script(s) */ - if (tabs.InitScriptTablePtr) - { - /* size is nolonger used, keeping it anyway for testing purposes :) */ - int16 size = 32767; - uint16 index = tabs.InitScriptTablePtr; - - adress = *((uint16*)(&(rom[index]))); - if (!adress) - { - LOG(8,("INFO: no cmdlist found!\n")); - result = B_ERROR; - } - - while (adress && (result == B_OK)) - { - result = exec_type2_script(rom, adress, &size, tabs, ram_tab); - /* next command script, please */ - index += 2; - adress = *((uint16*)(&(rom[index]))); - } - - /* now enable ROM shadow or the card will remain shut-off! */ - CFGW(ROMSHADOW, (CFGR(ROMSHADOW) |= 0x00000001)); - - //temporary: should be called from setmode probably.. - nv_crtc_setup_fifo(); - } - else - { - result = B_ERROR; - } - - if (result != B_OK) - LOG(8,("INFO: coldstart failed.\n")); - else - LOG(8,("INFO: coldstart execution completed OK.\n")); - - return result; -} - -/* This routine is complete, and is used for pre-NV10 cards. It's tested on a Elsa - * Erazor III with TNT2 (NV05) and on two no-name TNT2-M64's. All cards coldstart - * perfectly. */ -static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16 ram_tab) -{ - status_t result = B_OK; - bool end = false; - bool exec = true; - uint8 index, byte; - uint32 reg, data, data2, and_out, or_in; - - LOG(8,("\nINFO: executing type1 script at adress $%04x...\n", adress)); - LOG(8,("INFO: ---Executing following command(s):\n")); - - while (!end) - { - LOG(8,("INFO: $%04x ($%02x); ", adress, rom[adress])); - - switch (rom[adress]) - { - case 0x59: - *size -= 7; - if (*size < 0) - { - LOG(8,("script size error, aborting!\n\n")); - end = true; - result = B_ERROR; - break; - } - - /* execute */ - adress += 1; - reg = *((uint32*)(&(rom[adress]))); - adress += 4; - data = *((uint16*)(&(rom[adress]))); - adress += 2; - data2 = *((uint16*)(&(rom[data]))); - LOG(8,("cmd 'calculate indirect and set PLL 32bit reg $%08x for %.3fMHz'\n", - reg, ((float)data2))); - if (exec) - { - float calced_clk; - uint8 m, n, p; - nv_dac_sys_pll_find(((float)data2), &calced_clk, &m, &n, &p, 0); - NV_REG32(reg) = ((p << 16) | (n << 8) | m); - } - log_pll(reg, data2); - break; - case 0x5a: - *size -= 7; - if (*size < 0) - { - LOG(8,("script size error, aborting!\n\n")); - end = true; - result = B_ERROR; - break; - } - - /* execute */ - adress += 1; - reg = *((uint32*)(&(rom[adress]))); - adress += 4; - data = *((uint16*)(&(rom[adress]))); - adress += 2; - data2 = *((uint32*)(&(rom[data]))); - LOG(8,("cmd 'WR indirect 32bit reg' $%08x = $%08x\n", reg, data2)); - if (exec) NV_REG32(reg) = data2; - break; - case 0x63: - *size -= 1; - if (*size < 0) - { - LOG(8,("script size error, aborting!\n\n")); - end = true; - result = B_ERROR; - break; - } - - /* execute */ - adress += 1; - LOG(8,("cmd 'setup RAM config' (always done)\n")); - /* always done */ - setup_ram_config(rom, ram_tab); - break; - case 0x65: - *size -= 13; - if (*size < 0) - { - LOG(8,("script size error, aborting!\n\n")); - end = true; - result = B_ERROR; - break; - } - - /* execute */ - adress += 1; - reg = *((uint32*)(&(rom[adress]))); - adress += 4; - data = *((uint32*)(&(rom[adress]))); - adress += 4; - data2 = *((uint32*)(&(rom[adress]))); - adress += 4; - LOG(8,("cmd 'WR 32bit reg $%08x = $%08x, then = $%08x' (always done)\n", - reg, data, data2)); - /* always done */ - NV_REG32(reg) = data; - NV_REG32(reg) = data2; - CFGW(ROMSHADOW, (CFGR(ROMSHADOW) & 0xfffffffe)); - break; - case 0x69: - *size -= 5; - if (*size < 0) - { - LOG(8,("script size error, aborting!\n\n")); - end = true; - result = B_ERROR; - break; - } - - /* execute */ - adress += 1; - reg = *((uint16*)(&(rom[adress]))); - adress += 2; - and_out = *((uint8*)(&(rom[adress]))); - adress += 1; - or_in = *((uint8*)(&(rom[adress]))); - adress += 1; - LOG(8,("cmd 'RD 8bit ISA reg $%04x, AND-out = $%02x, OR-in = $%02x, WR-bk'\n", - reg, and_out, or_in)); - if (exec) - { - translate_ISA_PCI(®); - byte = NV_REG8(reg); - byte &= (uint8)and_out; - byte |= (uint8)or_in; - NV_REG8(reg) = byte; - } - break; - case 0x6d: - *size -= 3; - if (*size < 0) - { - LOG(8,("script size error, aborting!\n\n")); - end = true; - result = B_ERROR; - break; - } - - /* execute */ - adress += 1; - data = NV_REG32(NV32_NV4STRAPINFO); - and_out = *((uint8*)(&(rom[adress]))); - adress += 1; - byte = *((uint8*)(&(rom[adress]))); - adress += 1; - data &= (uint32)and_out; - LOG(8,("cmd 'CHK bits AND-out $%02x RAMCFG for $%02x'\n", - and_out, byte)); - if (((uint8)data) != byte) - { - LOG(8,("INFO: ---No match: not executing following command(s):\n")); - exec = false; - } - else - { - LOG(8,("INFO: ---Match, so this cmd has no effect.\n")); - } - break; - case 0x6e: - *size -= 13; - if (*size < 0) - { - LOG(8,("script size error, aborting!\n\n")); - end = true; - result = B_ERROR; - break; - } - - /* execute */ - adress += 1; - reg = *((uint32*)(&(rom[adress]))); - adress += 4; - and_out = *((uint32*)(&(rom[adress]))); - adress += 4; - or_in = *((uint32*)(&(rom[adress]))); - adress += 4; - LOG(8,("cmd 'RD 32bit reg $%08x, AND-out = $%08x, OR-in = $%08x, WR-bk'\n", - reg, and_out, or_in)); - if (exec) - { - data = NV_REG32(reg); - data &= and_out; - data |= or_in; - NV_REG32(reg) = data; - } - break; - case 0x71: - LOG(8,("cmd 'END', execution completed.\n\n")); - end = true; - - *size -= 1; - if (*size < 0) - { - LOG(8,("script size error!\n\n")); - result = B_ERROR; - } - break; - case 0x72: - *size -= 1; - if (*size < 0) - { - LOG(8,("script size error!\n\n")); - result = B_ERROR; - } - - /* execute */ - adress += 1; - LOG(8,("cmd 'PGM commands'\n")); - LOG(8,("INFO: ---Executing following command(s):\n")); - exec = true; - break; - case 0x73: - *size -= 9; - if (*size < 0) - { - LOG(8,("script size error, aborting!\n\n")); - end = true; - result = B_ERROR; - break; - } - - /* execute */ - adress += 1; - data = NV_REG32(NV32_NVSTRAPINFO2); - and_out = *((uint32*)(&(rom[adress]))); - adress += 4; - data2 = *((uint32*)(&(rom[adress]))); - adress += 4; - data &= and_out; - LOG(8,("cmd 'CHK bits AND-out $%08x STRAPCFG2 for $%08x'\n", - and_out, data2)); - if (data != data2) - { - LOG(8,("INFO: ---No match: not executing following command(s):\n")); - exec = false; - } - else - { - LOG(8,("INFO: ---Match, so this cmd has no effect.\n")); - } - break; - case 0x74: - *size -= 3; - if (*size < 0) - { - LOG(8,("script size error, aborting!\n\n")); - end = true; - result = B_ERROR; - break; - } - - /* execute */ - adress += 1; - data = *((uint16*)(&(rom[adress]))); - adress += 2; - LOG(8,("cmd 'SNOOZE for %d ($%04x) microSeconds' (always done)\n", data, data)); - /* always done */ - snooze(data); - break; - case 0x77: - *size -= 7; - if (*size < 0) - { - LOG(8,("script size error, aborting!\n\n")); - end = true; - result = B_ERROR; - break; - } - - /* execute */ - adress += 1; - reg = *((uint32*)(&(rom[adress]))); - adress += 4; - data = *((uint16*)(&(rom[adress]))); - adress += 2; - LOG(8,("cmd 'WR 32bit reg' $%08x = $%08x (b31-16 = '0', b15-0 = data)\n", - reg, data)); - if (exec) NV_REG32(reg) = data; - break; - case 0x78: - *size -= 6; - if (*size < 0) - { - LOG(8,("script size error, aborting!\n\n")); - end = true; - result = B_ERROR; - break; - } - - /* execute */ - adress += 1; - reg = *((uint16*)(&(rom[adress]))); - adress += 2; - index = *((uint8*)(&(rom[adress]))); - adress += 1; - and_out = *((uint8*)(&(rom[adress]))); - adress += 1; - or_in = *((uint8*)(&(rom[adress]))); - adress += 1; - LOG(8,("cmd 'RD idx ISA reg $%02x via $%04x, AND-out = $%02x, OR-in = $%02x, WR-bk'\n", - index, reg, and_out, or_in)); - if (exec) - { - translate_ISA_PCI(®); - NV_REG8(reg) = index; - byte = NV_REG8(reg + 1); - byte &= (uint8)and_out; - byte |= (uint8)or_in; - NV_REG8(reg + 1) = byte; - } - break; - case 0x79: - *size -= 7; - if (*size < 0) - { - LOG(8,("script size error, aborting!\n\n")); - end = true; - result = B_ERROR; - break; - } - - /* execute */ - adress += 1; - reg = *((uint32*)(&(rom[adress]))); - adress += 4; - data = *((uint16*)(&(rom[adress]))); - adress += 2; - LOG(8,("cmd 'calculate and set PLL 32bit reg $%08x for %.3fMHz'\n", reg, (data / 100.0))); - if (exec) - { - float calced_clk; - uint8 m, n, p; - nv_dac_sys_pll_find((data / 100.0), &calced_clk, &m, &n, &p, 0); - NV_REG32(reg) = ((p << 16) | (n << 8) | m); - } - log_pll(reg, (data / 100)); - break; - case 0x7a: - *size -= 9; - if (*size < 0) - { - LOG(8,("script size error, aborting!\n\n")); - end = true; - result = B_ERROR; - break; - } - - /* execute */ - adress += 1; - reg = *((uint32*)(&(rom[adress]))); - adress += 4; - data = *((uint32*)(&(rom[adress]))); - adress += 4; - LOG(8,("cmd 'WR 32bit reg' $%08x = $%08x\n", reg, data)); - if (exec) NV_REG32(reg) = data; - break; - default: - LOG(8,("unknown cmd, aborting!\n\n")); - end = true; - result = B_ERROR; - break; - } - } - - return result; -} - -static void log_pll(uint32 reg, uint32 freq) -{ - switch (reg) - { - case NV32_MEMPLL: - LOG(8,("INFO: ---Memory PLL accessed.\n")); - /* update the card's specs */ - si->ps.std_memory_clock = freq; - break; - case NV32_COREPLL: - LOG(8,("INFO: ---Core PLL accessed.\n")); - /* update the card's specs */ - si->ps.std_engine_clock = freq; - break; - case NVDAC_PIXPLLC: - LOG(8,("INFO: ---DAC1 PLL accessed.\n")); - break; - case NVDAC2_PIXPLLC: - LOG(8,("INFO: ---DAC2 PLL accessed.\n")); - break; - /* unexpected cases, here for learning goals... */ - case NV32_MEMPLL2: - LOG(8,("INFO: ---NV31/NV36 extension to memory PLL accessed only!\n")); - break; - case NV32_COREPLL2: - LOG(8,("INFO: ---NV31/NV36 extension to core PLL accessed only!\n")); - break; - case NVDAC_PIXPLLC2: - LOG(8,("INFO: ---NV31/NV36 extension to DAC1 PLL accessed only!\n")); - break; - case NVDAC2_PIXPLLC2: - LOG(8,("INFO: ---NV31/NV36 extension to DAC2 PLL accessed only!\n")); - break; - default: - LOG(8,("INFO: ---Unknown PLL accessed!\n")); - break; - } -} - -static void setup_ram_config(uint8* rom, uint16 ram_tab) -{ - uint32 ram_cfg, data; - uint8 cnt; - - /* set MRS = 256 */ - NV_REG32(NV32_PFB_DEBUG_0) &= 0xffffffef; - /* read RAM config hardware(?) strap */ - ram_cfg = ((NV_REG32(NV32_NVSTRAPINFO2) >> 2) & 0x0000000f); - LOG(8,("INFO: ---RAM config strap is $%01x\n", ram_cfg)); - /* use it as a pointer in a BIOS table for prerecorded RAM configurations */ - ram_cfg = *((uint16*)(&(rom[(ram_tab + (ram_cfg * 2))]))); - /* log info */ - switch (ram_cfg & 0x00000003) - { - case 0: - LOG(8,("INFO: ---32Mb RAM should be connected\n")); - break; - case 1: - LOG(8,("INFO: ---4Mb RAM should be connected\n")); - break; - case 2: - LOG(8,("INFO: ---8Mb RAM should be connected\n")); - break; - case 3: - LOG(8,("INFO: ---16Mb RAM should be connected\n")); - break; - } - if (ram_cfg & 0x00000004) - LOG(8,("INFO: ---RAM should be 128bits wide\n")); - else - LOG(8,("INFO: ---RAM should be 64bits wide\n")); - switch ((ram_cfg & 0x00000038) >> 3) - { - case 0: - LOG(8,("INFO: ---RAM type: 8Mbit SGRAM\n")); - break; - case 1: - LOG(8,("INFO: ---RAM type: 16Mbit SGRAM\n")); - break; - case 2: - LOG(8,("INFO: ---RAM type: 4 banks of 16Mbit SGRAM\n")); - break; - case 3: - LOG(8,("INFO: ---RAM type: 16Mbit SDRAM\n")); - break; - case 4: - LOG(8,("INFO: ---RAM type: 64Mbit SDRAM\n")); - break; - case 5: - LOG(8,("INFO: ---RAM type: 64Mbit x16 SDRAM\n")); - break; - } - /* set RAM amount, width and type */ - data = (NV_REG32(NV32_NV4STRAPINFO) & 0xffffffc0); - NV_REG32(NV32_NV4STRAPINFO) = (data | (ram_cfg & 0x0000003f)); - /* setup write to read delay (?) */ - data = (NV_REG32(NV32_PFB_CONFIG_1) & 0xff8ffffe); - data |= ((ram_cfg & 0x00000700) << 12); - /* force update via b0 = 0... */ - NV_REG32(NV32_PFB_CONFIG_1) = data; - /* ... followed by b0 = 1(?) */ - NV_REG32(NV32_PFB_CONFIG_1) = (data | 0x00000001); - - /* do RAM width test to confirm RAM width set to be correct */ - /* write testpattern to first 128 bits of graphics memory... */ - data = 0x4e563541; - for (cnt = 0; cnt < 4; cnt++) - ((volatile uint32 *)si->framebuffer)[cnt] = data; - /* ... if second 64 bits does not contain the testpattern we are apparantly - * set to 128bits width while we should be set to 64bits width, so correct. */ - if (((volatile uint32 *)si->framebuffer)[3] != data) - { - LOG(8,("INFO: ---RAM width tested: width is 64bits, correcting settings.\n")); - NV_REG32(NV32_NV4STRAPINFO) &= ~0x00000004; - } - else - { - LOG(8,("INFO: ---RAM width tested: access is OK.\n")); - } - - /* do RAM size test to confirm RAM size set to be correct */ - ram_cfg = (NV_REG32(NV32_NV4STRAPINFO) & 0x00000003); - data = 0x4e563542; - /* first check for 32Mb... */ - if (!ram_cfg) - { - /* write testpattern to just above the 16Mb boundary */ - ((volatile uint32 *)si->framebuffer)[(16 * 1024 * 1024) >> 2] = data; - /* check if pattern reads back */ - if (((volatile uint32 *)si->framebuffer)[(16 * 1024 * 1024) >> 2] == data) - { - /* write second testpattern to base adress */ - data = 0x4135564e; - ((volatile uint32 *)si->framebuffer)[0] = data; - if (((volatile uint32 *)si->framebuffer)[0] == data) - { - LOG(8,("INFO: ---RAM size tested: size was set OK (32Mb).\n")); - return; - } - } - /* one of the two tests for 32Mb failed, we must have 16Mb */ - ram_cfg = 0x00000003; - LOG(8,("INFO: ---RAM size tested: size is 16Mb, correcting settings.\n")); - NV_REG32(NV32_NV4STRAPINFO) = - (((NV_REG32(NV32_NV4STRAPINFO)) & 0xfffffffc) | ram_cfg); - return; - } - /* ... now check for 16Mb... */ - if (ram_cfg == 0x00000003) - { - /* increment testpattern */ - data++; - /* write testpattern to just above the 8Mb boundary */ - ((volatile uint32 *)si->framebuffer)[(8 * 1024 * 1024) >> 2] = data; - /* check if pattern reads back */ - if (((volatile uint32 *)si->framebuffer)[(8 * 1024 * 1024) >> 2] == data) - { - LOG(8,("INFO: ---RAM size tested: size was set OK (16Mb).\n")); - return; - } - else - { - /* assuming 8Mb: retesting below! */ - ram_cfg = 0x00000002; - LOG(8,("INFO: ---RAM size tested: size is NOT 16Mb, testing for 8Mb...\n")); - NV_REG32(NV32_NV4STRAPINFO) = - (((NV_REG32(NV32_NV4STRAPINFO)) & 0xfffffffc) | ram_cfg); - } - } - /* ... and now check for 8Mb! (ram_cfg will be 'pre'set to 4Mb or 8Mb here) */ - { - /* increment testpattern (again) */ - data++; - /* write testpattern to just above the 4Mb boundary */ - ((volatile uint32 *)si->framebuffer)[(4 * 1024 * 1024) >> 2] = data; - /* check if pattern reads back */ - if (((volatile uint32 *)si->framebuffer)[(4 * 1024 * 1024) >> 2] == data) - { - /* we have 8Mb, make sure this is set. */ - ram_cfg = 0x00000002; - LOG(8,("INFO: ---RAM size tested: size is 8Mb, setting 8Mb.\n")); - /* fixme? assuming this should be done here! */ - NV_REG32(NV32_NV4STRAPINFO) = - (((NV_REG32(NV32_NV4STRAPINFO)) & 0xfffffffc) | ram_cfg); - return; - } - else - { - /* we must have 4Mb, make sure this is set. */ - ram_cfg = 0x00000001; - LOG(8,("INFO: ---RAM size tested: size is 4Mb, setting 4Mb.\n")); - NV_REG32(NV32_NV4STRAPINFO) = - (((NV_REG32(NV32_NV4STRAPINFO)) & 0xfffffffc) | ram_cfg); - return; - } - } -} - -/* this routine is used for NV10 and later */ -static status_t exec_type2_script(uint8* rom, uint16 adress, int16* size, PinsTables tabs, uint16 ram_tab) -{ - bool exec = true; - - LOG(8,("\nINFO: executing type2 script at adress $%04x...\n", adress)); - LOG(8,("INFO: ---Executing following command(s):\n")); - - return exec_type2_script_mode(rom, &adress, size, tabs, ram_tab, &exec); -} - -/* this routine is used for NV10 and later. It's tested on a GeForce2 MX400 (NV11), - * GeForce4 MX440 (NV18), GeForce4 Ti4200 (NV28) and a GeForceFX 5200 (NV34). - * These cards coldstart perfectly. */ -static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size, PinsTables tabs, uint16 ram_tab, bool* exec) -{ - status_t result = B_OK; - bool end = false; - uint8 index, byte, byte2, shift; - uint32 reg, reg2, data, data2, and_out, and_out2, or_in, or_in2, safe32, offset32, size32; - - while (!end) - { - LOG(8,("INFO: $%04x ($%02x); ", *adress, rom[*adress])); - - /* all commands are here (verified NV11 and NV28) */ - switch (rom[*adress]) - { - case 0x31: /* new */ - *size -= (15 + ((*((uint8*)(&(rom[(*adress + 10)])))) << 2)); - if (*size < 0) - { - LOG(8,("script size error, aborting!\n\n")); - end = true; - result = B_ERROR; - break; - } - - /* execute */ - *adress += 1; - reg = *((uint32*)(&(rom[*adress]))); - *adress += 4; - and_out = *((uint32*)(&(rom[*adress]))); - *adress += 4; - shift = *((uint8*)(&(rom[*adress]))); - *adress += 1; - size32 = ((*((uint8*)(&(rom[*adress])))) << 2); - *adress += 1; - reg2 = *((uint32*)(&(rom[*adress]))); - *adress += 4; - LOG(8,("cmd 'RD 32bit reg $%08x, AND-out = $%08x, shift-right = $%02x,\n", - reg, and_out, shift)); - LOG(8,("INFO: (cont.) RD 32bit data from subtable with size $%04x, at offset (result << 2),\n", - size32)); - LOG(8,("INFO: (cont.) then WR result data to 32bit reg $%08x'\n", reg2)); - if (*exec && reg2) - { - data = NV_REG32(reg); - data &= and_out; - data >>= shift; - data2 = *((uint32*)(&(rom[(*adress + (data << 2))]))); - NV_REG32(reg2) = data2; - } - *adress += size32; - break; - case 0x32: /* new */ - *size -= (11 + ((*((uint8*)(&(rom[(*adress + 6)])))) << 2)); - if (*size < 0) - { - LOG(8,("script size error, aborting!\n\n")); - end = true; - result = B_ERROR; - break; - } - - /* execute */ - *adress += 1; - reg = *((uint16*)(&(rom[*adress]))); - *adress += 2; - index = *((uint8*)(&(rom[*adress]))); - *adress += 1; - and_out = *((uint8*)(&(rom[*adress]))); - *adress += 1; - byte2 = *((uint8*)(&(rom[*adress]))); - *adress += 1; - size32 = ((*((uint8*)(&(rom[*adress])))) << 2); - *adress += 1; - reg2 = *((uint32*)(&(rom[*adress]))); - *adress += 4; - LOG(8,("cmd 'RD idx ISA reg $%02x via $%04x, AND-out = $%02x, shift-right = $%02x,\n", - index, reg, and_out, byte2)); - LOG(8,("INFO: (cont.) RD 32bit data from subtable with size $%04x, at offset (result << 2),\n", - size32)); - LOG(8,("INFO: (cont.) then WR result data to 32bit reg $%08x'\n", reg2)); - if (*exec && reg2) - { - translate_ISA_PCI(®); - NV_REG8(reg) = index; - byte = NV_REG8(reg + 1); - byte &= (uint8)and_out; - byte >>= byte2; - offset32 = (byte << 2); - data = *((uint32*)(&(rom[(*adress + offset32)]))); - NV_REG32(reg2) = data; - } - *adress += size32; - break; - case 0x33: /* new */ - *size -= 2; - if (*size < 0) - { - LOG(8,("script size error, aborting!\n\n")); - end = true; - result = B_ERROR; - break; - } - - /* execute */ - *adress += 1; - size32 = *((uint8*)(&(rom[*adress]))); - *adress += 1; - /* executed 1-256 times */ - if (!size32) size32 = 256; - /* remember where to start each time */ - safe32 = *adress; - LOG(8,("cmd 'execute following part of this script $%03x times' (always done)\n", size32)); - for (offset32 = 0; offset32 < size32; offset32++) - { - LOG(8,("\nINFO: (#$%02x) executing part of type2 script at adress $%04x...\n", - offset32, *adress)); - LOG(8,("INFO: ---Not touching 'execution' mode at this time:\n")); - *adress = safe32; - result = exec_type2_script_mode(rom, adress, size, tabs, ram_tab, exec); - } - LOG(8,("INFO: ---Continuing script:\n")); - break; - case 0x34: /* new */ - *size -= (12 + ((*((uint8*)(&(rom[(*adress + 7)])))) << 1)); - if (*size < 0) - { - LOG(8,("script size error, aborting!\n\n")); - end = true; - result = B_ERROR; - break; - } - - /* execute */ - *adress += 1; - reg = *((uint16*)(&(rom[*adress]))); - *adress += 2; - index = *((uint8*)(&(rom[*adress]))); - *adress += 1; - and_out = *((uint8*)(&(rom[*adress]))); - *adress += 1; - shift = *((uint8*)(&(rom[*adress]))); - *adress += 1; - offset32 = *((uint8*)(&(rom[*adress]))); - *adress += 1; - size32 = ((*((uint8*)(&(rom[*adress])))) << 1); - *adress += 1; - reg2 = *((uint32*)(&(rom[*adress]))); - *adress += 4; - LOG(8,("cmd 'RD idx ISA reg $%02x via $%04x, AND-out = $%02x, shift-right = $%02x,\n", - index, reg, and_out, shift)); - LOG(8,("INFO: (cont.) RD 16bit PLL frequency to pgm from subtable with size $%04x, at offset (result << 1),\n", - size32)); - LOG(8,("INFO: (cont.) RD table-index ($%02x) for cmd $39'\n", - offset32)); - translate_ISA_PCI(®); - NV_REG8(reg) = index; - byte = NV_REG8(reg + 1); - byte &= (uint8)and_out; - data = (byte >> shift); - data <<= 1; - data2 = *((uint16*)(&(rom[(*adress + data)]))); - if (offset32 < 0x80) - { - bool double_f = true; - LOG(8,("INFO: Do subcmd ($39); ")); - exec_cmd_39_type2(rom, offset32, tabs, &double_f); - LOG(8,("INFO: (cont. cmd $34) Doubling PLL frequency to be set for cmd $34.\n")); - if (double_f) data2 <<= 1; - LOG(8,("INFO: ---Reverting to pre-subcmd ($39) 'execution' mode.\n")); - } - else - { - LOG(8,("INFO: table index is negative, not executing subcmd ($39).\n")); - } - LOG(8,("INFO: (cont.) 'calc and set PLL 32bit reg $%08x for %.3fMHz'\n", - reg2, (data2 / 100.0))); - if (*exec && reg2) - { - float calced_clk; - uint8 m, n, p; - nv_dac_sys_pll_find((data2 / 100.0), &calced_clk, &m, &n, &p, 0); - /* programming the PLL needs to be done in steps! (confirmed NV28) */ - data = NV_REG32(reg2); - NV_REG32(reg2) = ((data & 0xffff0000) | (n << 8) | m); - data = NV_REG32(reg2); - NV_REG32(reg2) = ((p << 16) | (n << 8) | m); -//fixme? - /* program 2nd set N and M scalers if they exist (b31=1 enables them) */ -// if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) -// DACW(PIXPLLC2, 0x80000401); - } - log_pll(reg2, (data2 / 100)); - *adress += size32; - break; - case 0x35: /* new */ - *size -= 2; - if (*size < 0) - { - LOG(8,("script size error, aborting!\n\n")); - end = true; - result = B_ERROR; - break; - } - - /* execute */ - *adress += 1; - byte = *((uint8*)(&(rom[*adress]))); - *adress += 1; - offset32 = (byte << 1); - offset32 += tabs.InitFunctionTablePtr; - LOG(8,("cmd 'execute fixed VGA BIOS routine #$%02x at adress $%04x'\n", - byte, offset32)); - /* note: - * This command is BIOS/'pins' version specific. Confirmed a NV28 having NO - * entries at all in InitFunctionTable! - * (BIOS version 4.28.20.05.11; 'pins' version 5.21) */ - //fixme: impl. if it turns out this cmd is used.. (didn't see that yet) - if (*exec) - { - //fixme: add BIOS/'pins' version dependancy... - switch(byte) - { - default: - LOG(8,("\n\nINFO: WARNING: function not implemented, skipping!\n\n")); - break; - } - } - break; - case 0x37: /* new */ - *size -= 11; - if (*size < 0) - { - LOG(8,("script size error, aborting!\n\n")); - end = true; - result = B_ERROR; - break; - } - - /* execute */ - *adress += 1; - reg = *((uint32*)(&(rom[*adress]))); - *adress += 4; - byte2 = *((uint8*)(&(rom[*adress]))); - *adress += 1; - and_out = *((uint8*)(&(rom[*adress]))); - *adress += 1; - reg2 = *((uint16*)(&(rom[*adress]))); - *adress += 2; - index = *((uint8*)(&(rom[*adress]))); - *adress += 1; - and_out2 = *((uint8*)(&(rom[*adress]))); - *adress += 1; - LOG(8,("cmd 'RD 32bit reg $%08x, shift-right = $%02x, AND-out lsb = $%02x,\n", - reg, byte2, and_out)); - LOG(8,("INFO: (cont.) RD 8bit ISA reg $%02x via $%04x, AND-out = $%02x, OR-in lsb result 32bit, WR-bk'\n", - index, reg2, and_out2)); - if (*exec) - { - data = NV_REG32(reg); - if (byte2 < 0x80) - { - data >>= byte2; - } - else - { - data <<= (0x0100 - byte2); - } - data &= and_out; - translate_ISA_PCI(®2); - NV_REG8(reg2) = index; - byte = NV_REG8(reg2 + 1); - byte &= (uint8)and_out2; - byte |= (uint8)data; - NV_REG8(reg2 + 1) = byte; - } - break; - case 0x38: /* new */ - *size -= 1; - if (*size < 0) - { - LOG(8,("script size error, aborting!\n\n")); - end = true; - result = B_ERROR; - break; - } - - /* execute */ - *adress += 1; - LOG(8,("cmd 'invert current mode'\n")); - *exec = !(*exec); - if (*exec) - LOG(8,("INFO: ---Executing following command(s):\n")); - else - LOG(8,("INFO: ---Not executing following command(s):\n")); - break; - case 0x39: /* new */ - *size -= 2; - if (*size < 0) - { - LOG(8,("script size error, aborting!\n\n")); - end = true; - result = B_ERROR; - break; - } - - /* execute */ - *adress += 1; - data = *((uint8*)(&(rom[*adress]))); - *adress += 1; - exec_cmd_39_type2(rom, data, tabs, exec); - break; - case 0x49: /* new */ - size32 = *((uint8*)(&(rom[*adress + 17]))); - if (!size32) size32 = 256; - *size -= (18 + (size32 << 1)); - if (*size < 0) - { - LOG(8,("script size error, aborting!\n\n")); - end = true; - result = B_ERROR; - break; - } - - /* execute */ - *adress += 1; - reg = *((uint32*)(&(rom[*adress]))); - *adress += 4; - reg2 = *((uint32*)(&(rom[*adress]))); - *adress += 4; - and_out = *((uint32*)(&(rom[*adress]))); - *adress += 4; - or_in = *((uint32*)(&(rom[*adress]))); - *adress += 4; - size32 = *((uint8*)(&(rom[*adress]))); - if (!size32) size32 = 256; - *adress += 1; - LOG(8,("cmd 'do following cmd structure $%03x time(s)':\n", size32)); - for (offset32 = 0; offset32 < size32; offset32++) - { - or_in2 = *((uint8*)(&(rom[(*adress + (offset32 << 1))]))); - data2 = *((uint8*)(&(rom[(*adress + (offset32 << 1) + 1)]))); - LOG(8,("INFO (cont.) (#$%02x) cmd 'WR 32bit reg $%08x = $%08x, RD 32bit reg $%08x,\n", - offset32, reg2, data2, reg)); - LOG(8,("INFO (cont.) AND-out $%08x, OR-in $%08x, OR-in $%08x, WR-bk'\n", - and_out, or_in, or_in2)); - } - if (*exec) - { - for (index = 0; index < size32; index++) - { - or_in2 = *((uint8*)(&(rom[*adress]))); - *adress += 1; - data2 = *((uint8*)(&(rom[*adress]))); - *adress += 1; - NV_REG32(reg2) = data2; - data = NV_REG32(reg); - data &= and_out; - data |= or_in; - data |= or_in2; - NV_REG32(reg) = data; - } - } - else - { - *adress += (size32 << 1); - } - break; - case 0x61: /* new */ - *size -= 4; - if (*size < 0) - { - LOG(8,("script size error, aborting!\n\n")); - end = true; - result = B_ERROR; - break; - } - - /* execute */ - *adress += 1; - reg = *((uint16*)(&(rom[*adress]))); - *adress += 2; - byte = *((uint8*)(&(rom[*adress]))); - *adress += 1; - LOG(8,("cmd 'WR ISA reg $%04x = $%02x'\n", reg, byte)); - if (*exec) - { - translate_ISA_PCI(®); - NV_REG8(reg) = byte; - } - break; - case 0x62: /* new */ - *size -= 5; - if (*size < 0) - { - LOG(8,("script size error, aborting!\n\n")); - end = true; - result = B_ERROR; - break; - } - - /* execute */ - *adress += 1; - reg = *((uint16*)(&(rom[*adress]))); - *adress += 2; - index = *((uint8*)(&(rom[*adress]))); - *adress += 1; - byte = *((uint8*)(&(rom[*adress]))); - *adress += 1; - LOG(8,("cmd 'WR idx ISA reg $%02x via $%04x = $%02x'\n", index, reg, byte)); - if (*exec) - { - translate_ISA_PCI(®); - NV_REG16(reg) = ((((uint16)byte) << 8) | index); - } - break; - case 0x63: /* new setup compared to pre-NV10 version */ - *size -= 1; - if (*size < 0) - { - LOG(8,("script size error, aborting!\n\n")); - end = true; - result = B_ERROR; - break; - } - - /* execute */ - *adress += 1; - LOG(8,("cmd 'setup RAM config' (always done)\n")); - /* always done */ - setup_ram_config_nv10_up(rom); - break; - case 0x65: /* identical to type1 */ - *size -= 13; - if (*size < 0) - { - LOG(8,("script size error, aborting!\n\n")); - end = true; - result = B_ERROR; - break; - } - - /* execute */ - *adress += 1; - reg = *((uint32*)(&(rom[*adress]))); - *adress += 4; - data = *((uint32*)(&(rom[*adress]))); - *adress += 4; - data2 = *((uint32*)(&(rom[*adress]))); - *adress += 4; - LOG(8,("cmd 'WR 32bit reg $%08x = $%08x, then = $%08x' (always done)\n", - reg, data, data2)); - /* always done */ - NV_REG32(reg) = data; - NV_REG32(reg) = data2; - CFGW(ROMSHADOW, (CFGR(ROMSHADOW) & 0xfffffffe)); - break; - case 0x69: /* identical to type1 */ - *size -= 5; - if (*size < 0) - { - LOG(8,("script size error, aborting!\n\n")); - end = true; - result = B_ERROR; - break; - } - - /* execute */ - *adress += 1; - reg = *((uint16*)(&(rom[*adress]))); - *adress += 2; - and_out = *((uint8*)(&(rom[*adress]))); - *adress += 1; - or_in = *((uint8*)(&(rom[*adress]))); - *adress += 1; - LOG(8,("cmd 'RD 8bit ISA reg $%04x, AND-out = $%02x, OR-in = $%02x, WR-bk'\n", - reg, and_out, or_in)); - if (*exec) - { - translate_ISA_PCI(®); - byte = NV_REG8(reg); - byte &= (uint8)and_out; - byte |= (uint8)or_in; - NV_REG8(reg) = byte; - } - break; - case 0x6a: /* new */ - *size -= 2; - if (*size < 0) - { - LOG(8,("script size error, aborting!\n\n")); - end = true; - result = B_ERROR; - break; - } - - /* execute */ - *adress += 1; - data = *((uint8*)(&(rom[*adress]))); - *adress += 1; - data2 = *((uint16*)(&(rom[(tabs.InitScriptTablePtr + (data << 1))]))); - LOG(8,("cmd 'jump to script #$%02x at adress $%04x'\n", data, data2)); - if (*exec) - { - *adress = data2; - LOG(8,("INFO: ---Jumping; not touching 'execution' mode.\n")); - } - break; - case 0x6b: /* new */ - *size -= 2; - if (*size < 0) - { - LOG(8,("script size error, aborting!\n\n")); - end = true; - result = B_ERROR; - break; - } - - /* execute */ - *adress += 1; - data = *((uint8*)(&(rom[*adress]))); - *adress += 1; - data2 = *((uint16*)(&(rom[(tabs.InitScriptTablePtr + (data << 1))]))); - LOG(8,("cmd 'gosub script #$%02x at adress $%04x'\n", data, data2)); - if (*exec && data2) - { - result = exec_type2_script(rom, data2, size, tabs, ram_tab); - LOG(8,("INFO: ---Reverting to pre-gosub 'execution' mode.\n")); - } - break; - case 0x6e: /* identical to type1 */ - *size -= 13; - if (*size < 0) - { - LOG(8,("script size error, aborting!\n\n")); - end = true; - result = B_ERROR; - break; - } - - /* execute */ - *adress += 1; - reg = *((uint32*)(&(rom[*adress]))); - *adress += 4; - and_out = *((uint32*)(&(rom[*adress]))); - *adress += 4; - or_in = *((uint32*)(&(rom[*adress]))); - *adress += 4; - LOG(8,("cmd 'RD 32bit reg $%08x, AND-out = $%08x, OR-in = $%08x, WR-bk'\n", - reg, and_out, or_in)); - if (*exec) - { - data = NV_REG32(reg); - data &= and_out; - data |= or_in; - NV_REG32(reg) = data; - } - break; - case 0x6f: /* new */ - *size -= 2; - if (*size < 0) - { - LOG(8,("script size error, aborting!\n\n")); - end = true; - result = B_ERROR; - break; - } - - /* execute */ - *adress += 1; - byte = *((uint8*)(&(rom[*adress]))); - *adress += 1; - data = tabs.MacroIndexTablePtr + (byte << 1); - offset32 = (*((uint8*)(&(rom[data]))) << 3); - size32 = *((uint8*)(&(rom[(data + 1)]))); - offset32 += tabs.MacroTablePtr; - /* note: min 1, max 255 commands can be requested */ - LOG(8,("cmd 'do $%02x time(s) a 32bit reg WR with 32bit data' (MacroIndexTable idx = $%02x):\n", - size32, byte)); - safe32 = 0; - while (safe32 < size32) - { - reg2 = *((uint32*)(&(rom[(offset32 + (safe32 << 3))]))); - data2 = *((uint32*)(&(rom[(offset32 + (safe32 << 3) + 4)]))); - LOG(8,("INFO: (cont.) (#$%02x) cmd 'WR 32bit reg' $%08x = $%08x\n", - safe32, reg2, data2)); - safe32++; - } - if (*exec) - { - safe32 = 0; - while (safe32 < size32) - { - reg2 = *((uint32*)(&(rom[(offset32 + (safe32 << 3))]))); - data2 = *((uint32*)(&(rom[(offset32 + (safe32 << 3) + 4)]))); - NV_REG32(reg2) = data2; - safe32++; - } - } - break; - case 0x36: /* new */ - case 0x66: /* new */ - case 0x67: /* new */ - case 0x68: /* new */ - case 0x6c: /* new */ - case 0x71: /* identical to type1 */ - LOG(8,("cmd 'END', execution completed.\n\n")); - end = true; - - *size -= 1; - if (*size < 0) - { - LOG(8,("script size error!\n\n")); - result = B_ERROR; - } - - /* execute */ - *adress += 1; /* needed to make cmd #$33 work correctly! */ - break; - case 0x72: /* identical to type1 */ - *size -= 1; - if (*size < 0) - { - LOG(8,("script size error!\n\n")); - result = B_ERROR; - } - - /* execute */ - *adress += 1; - LOG(8,("cmd 'PGM commands'\n")); - LOG(8,("INFO: ---Executing following command(s):\n")); - *exec = true; - break; - case 0x74: /* identical to type1 */ - //fixme? on at least NV28 this cmd hammers the CRTC PCI-timeout register - //'data' number of times instead of snoozing. - //Couldn't see any diff in behaviour though! - *size -= 3; - if (*size < 0) - { - LOG(8,("script size error, aborting!\n\n")); - end = true; - result = B_ERROR; - break; - } - - /* execute */ - *adress += 1; - data = *((uint16*)(&(rom[*adress]))); - *adress += 2; - LOG(8,("cmd 'SNOOZE for %d ($%04x) microSeconds' (always done)\n", data, data)); - /* always done */ - snooze(data); - break; - case 0x75: /* new */ - *size -= 2; - if (*size < 0) - { - LOG(8,("script size error!\n\n")); - result = B_ERROR; - } - - /* execute */ - *adress += 1; - data = *((uint8*)(&(rom[*adress]))); - *adress += 1; - data *= 12; - data += tabs.ConditionTablePtr; - reg = *((uint32*)(&(rom[data]))); - and_out = *((uint32*)(&(rom[(data + 4)]))); - data2 = *((uint32*)(&(rom[(data + 8)]))); - data = NV_REG32(reg); - data &= and_out; - LOG(8,("cmd 'CHK bits AND-out $%08x reg $%08x for $%08x'\n", - and_out, reg, data2)); - if (data != data2) - { - LOG(8,("INFO: ---No match: not executing following command(s):\n")); - *exec = false; - } - else - { - LOG(8,("INFO: ---Match, so this cmd has no effect.\n")); - } - break; - case 0x76: /* new */ - *size -= 2; - if (*size < 0) - { - LOG(8,("script size error!\n\n")); - result = B_ERROR; - } - - /* execute */ - *adress += 1; - data = *((uint8*)(&(rom[*adress]))); - *adress += 1; - data *= 5; - data += tabs.IOConditionTablePtr; - reg = *((uint16*)(&(rom[data]))); - index = *((uint8*)(&(rom[(data + 2)]))); - and_out = *((uint8*)(&(rom[(data + 3)]))); - byte2 = *((uint8*)(&(rom[(data + 4)]))); - LOG(8,("cmd 'CHK bits AND-out $%02x idx ISA reg $%02x via $%04x for $%02x'\n", - and_out, index, reg, byte2)); - translate_ISA_PCI(®); - NV_REG8(reg) = index; - byte = NV_REG8(reg + 1); - byte &= (uint8)and_out; - if (byte != byte2) - { - LOG(8,("INFO: ---No match: not executing following command(s):\n")); - *exec = false; - } - else - { - LOG(8,("INFO: ---Match, so this cmd has no effect.\n")); - } - break; - case 0x78: /* identical to type1 */ - *size -= 6; - if (*size < 0) - { - LOG(8,("script size error, aborting!\n\n")); - end = true; - result = B_ERROR; - break; - } - - /* execute */ - *adress += 1; - reg = *((uint16*)(&(rom[*adress]))); - *adress += 2; - index = *((uint8*)(&(rom[*adress]))); - *adress += 1; - and_out = *((uint8*)(&(rom[*adress]))); - *adress += 1; - or_in = *((uint8*)(&(rom[*adress]))); - *adress += 1; - LOG(8,("cmd 'RD idx ISA reg $%02x via $%04x, AND-out = $%02x, OR-in = $%02x, WR-bk'\n", - index, reg, and_out, or_in)); - if (*exec) - { - translate_ISA_PCI(®); - NV_REG8(reg) = index; - byte = NV_REG8(reg + 1); - byte &= (uint8)and_out; - byte |= (uint8)or_in; - NV_REG8(reg + 1) = byte; - } - break; - case 0x79: - *size -= 7; - if (*size < 0) - { - LOG(8,("script size error, aborting!\n\n")); - end = true; - result = B_ERROR; - break; - } - - /* execute */ - *adress += 1; - reg = *((uint32*)(&(rom[*adress]))); - *adress += 4; - data = *((uint16*)(&(rom[*adress]))); - *adress += 2; - LOG(8,("cmd 'calculate and set PLL 32bit reg $%08x for %.3fMHz'\n", reg, (data / 100.0))); - if (*exec) - { - float calced_clk; - uint8 m, n, p; - nv_dac_sys_pll_find((data / 100.0), &calced_clk, &m, &n, &p, 0); - /* programming the PLL needs to be done in steps! (confirmed NV28) */ - data2 = NV_REG32(reg); - NV_REG32(reg) = ((data2 & 0xffff0000) | (n << 8) | m); - data2 = NV_REG32(reg); - NV_REG32(reg) = ((p << 16) | (n << 8) | m); -//fixme? - /* program 2nd set N and M scalers if they exist (b31=1 enables them) */ -// if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) -// DACW(PIXPLLC2, 0x80000401); - } - log_pll(reg, (data / 100)); - break; - case 0x7a: /* identical to type1 */ - *size -= 9; - if (*size < 0) - { - LOG(8,("script size error, aborting!\n\n")); - end = true; - result = B_ERROR; - break; - } - - /* execute */ - *adress += 1; - reg = *((uint32*)(&(rom[*adress]))); - *adress += 4; - data = *((uint32*)(&(rom[*adress]))); - *adress += 4; - LOG(8,("cmd 'WR 32bit reg' $%08x = $%08x\n", reg, data)); - if (*exec) NV_REG32(reg) = data; - break; - default: - LOG(8,("unknown cmd, aborting!\n\n")); - end = true; - result = B_ERROR; - break; - } - } - - return result; -} - -static void exec_cmd_39_type2(uint8* rom, uint32 data, PinsTables tabs, bool* exec) -{ - uint8 index, byte, byte2, safe, shift; - uint32 reg, and_out, and_out2, offset32; - - data *= 9; - data += tabs.IOFlagConditionTablePtr; - reg = *((uint16*)(&(rom[data]))); - index = *((uint8*)(&(rom[(data + 2)]))); - and_out = *((uint8*)(&(rom[(data + 3)]))); - shift = *((uint8*)(&(rom[(data + 4)]))); - offset32 = *((uint16*)(&(rom[data + 5]))); - and_out2 = *((uint8*)(&(rom[(data + 7)]))); - byte2 = *((uint8*)(&(rom[(data + 8)]))); - LOG(8,("cmd 'AND-out bits $%02x idx ISA reg $%02x via $%04x, shift-right = $%02x,\n", - and_out, index, reg, shift)); - translate_ISA_PCI(®); - NV_REG8(reg) = index; - byte = NV_REG8(reg + 1); - byte &= (uint8)and_out; - offset32 += (byte >> shift); - safe = byte = *((uint8*)(&(rom[offset32]))); - byte &= (uint8)and_out2; - LOG(8,("INFO: (cont.) use result as index in table to get data $%02x,\n", - safe)); - LOG(8,("INFO: (cont.) then chk bits AND-out $%02x of data for $%02x'\n", - and_out2, byte2)); - if (byte != byte2) - { - LOG(8,("INFO: ---No match: not executing following command(s):\n")); - *exec = false; - } - else - { - LOG(8,("INFO: ---Match, so this cmd has no effect.\n")); - } -} - -static void setup_ram_config_nv10_up(uint8* rom) -{ - /* note: - * After writing data to RAM a snooze is required to make the test work. - * Confirmed a NV11: without snooze it worked OK on a low-voltage AGP2.0 slot, - * but on a higher-voltage AGP 1.0 slot it failed to identify errors correctly!! - * Adding the snooze fixed that. */ - - uint32 data, dummy; - uint8 cnt = 0; - status_t stat = B_ERROR; - - /* set 'refctrl is valid' */ - NV_REG32(NV32_PFB_REFCTRL) = 0x80000000; - - /* check RAM for 256bits buswidth(?) */ - while ((cnt < 4) && (stat != B_OK)) - { - /* reset RAM bits at offset 224-255 bits four times */ - ((volatile uint32 *)si->framebuffer)[0x07] = 0x00000000; - snooze(10); - ((volatile uint32 *)si->framebuffer)[0x07] = 0x00000000; - snooze(10); - ((volatile uint32 *)si->framebuffer)[0x07] = 0x00000000; - snooze(10); - ((volatile uint32 *)si->framebuffer)[0x07] = 0x00000000; - snooze(10); - /* write testpattern */ - ((volatile uint32 *)si->framebuffer)[0x07] = 0x4e563131; - snooze(10); - /* reset RAM bits at offset 480-511 bits */ - ((volatile uint32 *)si->framebuffer)[0x0f] = 0x00000000; - snooze(10); - /* check testpattern to have survived */ - if (((volatile uint32 *)si->framebuffer)[0x07] == 0x4e563131) stat = B_OK; - cnt++; - } - - /* if pattern did not hold modify RAM-type setup */ - if (stat != B_OK) - { - LOG(8,("INFO: ---RAM test #1 done: access errors, modified setup.\n")); - data = NV_REG32(NV32_PFB_CONFIG_0); - if (data & 0x00000010) - { - data &= 0xffffffcf; - } - else - { - data &= 0xffffffcf; - data |= 0x00000020; - } - NV_REG32(NV32_PFB_CONFIG_0) = data; - } - else - { - LOG(8,("INFO: ---RAM test #1 done: access is OK.\n")); - } - - /* check RAM bankswitching stuff(?) */ - cnt = 0; - stat = B_ERROR; - while ((cnt < 4) && (stat != B_OK)) - { - /* read RAM size */ - data = NV_REG32(NV32_NV10STRAPINFO); - /* subtract 1MB */ - data -= 0x00100000; - /* write testpattern at generated RAM adress */ - ((volatile uint32 *)si->framebuffer)[(data >> 2)] = 0x4e564441; - snooze(10); - /* reset first RAM adress */ - ((volatile uint32 *)si->framebuffer)[0x00] = 0x00000000; - snooze(10); - /* dummyread first RAM adress four times */ - dummy = ((volatile uint32 *)si->framebuffer)[0x00]; - dummy = ((volatile uint32 *)si->framebuffer)[0x00]; - dummy = ((volatile uint32 *)si->framebuffer)[0x00]; - dummy = ((volatile uint32 *)si->framebuffer)[0x00]; - /* check testpattern to have survived */ - if (((volatile uint32 *)si->framebuffer)[(data >> 2)] == 0x4e564441) stat = B_OK; - cnt++; - } - - /* if pattern did not hold modify RAM-type setup */ - if (stat != B_OK) - { - LOG(8,("INFO: ---RAM test #2 done: access errors, modified setup.\n")); - NV_REG32(NV32_PFB_CONFIG_0) &= 0xffffefff; - } - else - { - LOG(8,("INFO: ---RAM test #2 done: access is OK.\n")); - } -} - -static status_t translate_ISA_PCI(uint32* reg) -{ - switch (*reg) - { - case 0x03c0: - *reg = NV8_ATTRDATW; - break; - case 0x03c1: - *reg = NV8_ATTRDATR; - break; - case 0x03c2: - *reg = NV8_MISCW; - break; - case 0x03c4: - *reg = NV8_SEQIND; - break; - case 0x03c5: - *reg = NV8_SEQDAT; - break; - case 0x03c6: - *reg = NV8_PALMASK; - break; - case 0x03c7: - *reg = NV8_PALINDR; - break; - case 0x03c8: - *reg = NV8_PALINDW; - break; - case 0x03c9: - *reg = NV8_PALDATA; - break; - case 0x03cc: - *reg = NV8_MISCR; - break; - case 0x03ce: - *reg = NV8_GRPHIND; - break; - case 0x03cf: - *reg = NV8_GRPHDAT; - break; - case 0x03d4: - *reg = NV8_CRTCIND; - break; - case 0x03d5: - *reg = NV8_CRTCDAT; - break; - case 0x03da: - *reg = NV8_INSTAT1; - break; - default: - LOG(8,("\n\nINFO: WARNING: ISA->PCI register adress translation failed!\n\n")); - return B_ERROR; - break; - } - - return B_OK; -} - -void set_pll(uint32 reg, uint32 req_clk) -{ - uint32 data; - float calced_clk; - uint8 m, n, p; - nv_dac_sys_pll_find(req_clk, &calced_clk, &m, &n, &p, 0); - /* programming the PLL needs to be done in steps! (confirmed NV28) */ - data = NV_REG32(reg); - NV_REG32(reg) = ((data & 0xffff0000) | (n << 8) | m); - data = NV_REG32(reg); - NV_REG32(reg) = ((p << 16) | (n << 8) | m); - -//fixme? - /* program 2nd set N and M scalers if they exist (b31=1 enables them) */ - if (si->ps.ext_pll) - { - if (reg == NV32_COREPLL) NV_REG32(NV32_COREPLL2) = 0x80000401; - if (reg == NV32_MEMPLL) NV_REG32(NV32_MEMPLL2) = 0x80000401; - } - - log_pll(reg, req_clk); -} - -/* doing general fail-safe default setup here */ -static status_t nv_crtc_setup_fifo() -{ - /* enable access to primary head */ - set_crtc_owner(0); - - /* set CRTC FIFO burst size to 256 */ - CRTCW(FIFO, 0x03); - - /* set CRTC FIFO low watermark to 32 */ - CRTCW(FIFO_LWM, 0x20); - - return B_OK; -} - -/* (pre)set 'fixed' card specifications */ -void set_specs(void) -{ - LOG(8,("INFO: setting up card specifications\n")); - - /* set failsave speeds */ - switch (si->ps.card_arch) - { - case NV40A: - pinsnv30_arch_fake(); - break; - default: - /* 'failsafe' values... */ - pinsnv30_arch_fake(); - break; - } - - /* detect reference crystal frequency and dualhead */ - switch (si->ps.card_arch) - { - default: - getstrap_arch_nv10_20_30_40(); - break; - } -} - -/* this routine presumes the card was coldstarted by the card's BIOS for panel stuff */ -void fake_panel_start(void) -{ - LOG(8,("INFO: detecting RAM size\n")); - - /* detect RAM amount */ - switch (si->ps.card_arch) - { - default: - getRAMsize_arch_nv10_20_30_40(); - break; - } - - /* override memory detection if requested by user */ - if (si->settings.memory != 0) - { - LOG(2,("INFO: forcing memory size (specified in settings file)\n")); - si->ps.memory_size = si->settings.memory * 1024 * 1024; - } - - i2c_init(); - - LOG(8,("INFO: faking panel startup\n")); - - /* find out the BIOS preprogrammed panel use status... */ - detect_panels(); - - /* determine and setup output devices and heads */ - setup_output_matrix(); - - /* select other CRTC for primary head use if specified by user in settings file */ - if (si->ps.secondary_head && si->settings.switchhead) - { - LOG(2,("INFO: inverting head use (specified in settings file)\n")); - si->ps.crtc2_prim = !si->ps.crtc2_prim; - } -} - -static void detect_panels() -{ - /* detect if the BIOS enabled LCD's (internal panels or DVI) */ - - /* both external TMDS transmitters (used for LCD/DVI) and external TVencoders - * (can) use the CRTC's in slaved mode. */ - /* Note: - * DFP's are programmed with standard VESA modelines by the card's BIOS! */ - bool slaved_for_dev1 = false, slaved_for_dev2 = false; - - /* check primary head: */ - /* enable access to primary head */ - set_crtc_owner(0); - - /* unlock head's registers for R/W access */ - CRTCW(LOCK, 0x57); - CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f)); - - LOG(2,("INFO: Dumping flatpanel related CRTC registers:\n")); - /* related info PIXEL register: - * b7: 1 = slaved mode (all cards). */ - LOG(2,("CRTC1: PIXEL register: $%02x\n", CRTCR(PIXEL))); - /* info LCD register: - * b7: 1 = stereo view (shutter glasses use) (all cards), - * b5: 1 = power ext. TMDS (or something)/0 = TVout use (?) (confirmed NV17, NV28), - * b4: 1 = power ext. TMDS (or something)/0 = TVout use (?) (confirmed NV34), - * b3: 1 = ??? (not panel related probably!) (confirmed NV34), - * b1: 1 = power ext. TMDS (or something) (?) (confirmed NV05?, NV17), - * b0: 1 = select panel encoder / 0 = select TVout encoder (all cards). */ - LOG(2,("CRTC1: LCD register: $%02x\n", CRTCR(LCD))); - /* info 0x59 register: - * b0: 1 = enable ext. TMDS clock (DPMS) (confirmed NV28, NV34). */ - LOG(2,("CRTC1: register $59: $%02x\n", CRTCR(0x59))); - /* info 0x9f register: - * b4: 0 = TVout use (?). */ - LOG(2,("CRTC1: register $9f: $%02x\n", CRTCR(0x9f))); - - /* detect active slave device (if any) */ - slaved_for_dev1 = (CRTCR(PIXEL) & 0x80); - - if (si->ps.secondary_head) - { - /* check secondary head: */ - /* enable access to secondary head */ - set_crtc_owner(1); - /* unlock head's registers for R/W access */ - CRTC2W(LOCK, 0x57); - CRTC2W(VSYNCE ,(CRTC2R(VSYNCE) & 0x7f)); - - LOG(2,("CRTC2: PIXEL register: $%02x\n", CRTC2R(PIXEL))); - LOG(2,("CRTC2: LCD register: $%02x\n", CRTC2R(LCD))); - LOG(2,("CRTC2: register $59: $%02x\n", CRTC2R(0x59))); - LOG(2,("CRTC2: register $9f: $%02x\n", CRTC2R(0x9f))); - - /* detect active slave device (if any) */ - slaved_for_dev2 = (CRTC2R(PIXEL) & 0x80); - } - - LOG(2,("INFO: End flatpanel related CRTC registers dump.\n")); - - /* do some presets */ - si->ps.p1_timing.h_display = 0; - si->ps.p1_timing.v_display = 0; - si->ps.panel1_aspect = 0; - si->ps.p2_timing.h_display = 0; - si->ps.p2_timing.v_display = 0; - si->ps.panel2_aspect = 0; - si->ps.slaved_tmds1 = false; - si->ps.slaved_tmds2 = false; - si->ps.master_tmds1 = false; - si->ps.master_tmds2 = false; - si->ps.tmds1_active = false; - si->ps.tmds2_active = false; - /* determine the situation we are in... (regarding flatpanels) */ - /* fixme: add VESA DDC EDID stuff one day... */ - /* fixme: find out how to program those transmitters one day instead of - * relying on the cards BIOS to do it. - * Currently we'd loose the panel setup while not being able to restore it. */ - - /* note: (facts) - * -> a register-set's FP_TG_CTRL register, bit 31 tells you if a LVDS panel is - * connected to the primary head (0), or to the secondary head (1); - * -> for LVDS panels both registersets are programmed identically by the card's - * BIOSes; - * -> the programmed set of registers tells you where a TMDS (DVI) panel is - * connected; - * -> On all cards a CRTC is used in slaved mode when a panel is connected. */ - /* note also: - * external TMDS encoders are only used for logic-level translation: it's - * modeline registers are not used. Instead the GPU's internal modeline registers - * are used. The external encoder is not connected to a I2C bus (confirmed NV34). */ - if (slaved_for_dev1) - { - uint16 width = ((DACR(FP_HDISPEND) & 0x0000ffff) + 1); - uint16 height = ((DACR(FP_VDISPEND) & 0x0000ffff) + 1); - if ((width >= 640) && (height >= 480)) - { - si->ps.slaved_tmds1 = true; - si->ps.tmds1_active = true; - si->ps.p1_timing.h_display = width; - si->ps.p1_timing.v_display = height; - } - } - - if (si->ps.secondary_head && slaved_for_dev2) - { - uint16 width = ((DAC2R(FP_HDISPEND) & 0x0000ffff) + 1); - uint16 height = ((DAC2R(FP_VDISPEND) & 0x0000ffff) + 1); - if ((width >= 640) && (height >= 480)) - { - si->ps.slaved_tmds2 = true; - si->ps.tmds2_active = true; - si->ps.p2_timing.h_display = width; - si->ps.p2_timing.v_display = height; - } - } - - //fixme...: - //we are assuming that no DVI is used as external monitor on laptops; - //otherwise we probably get into trouble here if the checked specs match. - if (si->ps.laptop && si->ps.tmds1_active && si->ps.tmds2_active && - ((DACR(FP_TG_CTRL) & 0x80000000) == (DAC2R(FP_TG_CTRL) & 0x80000000)) && - (si->ps.p1_timing.h_display == si->ps.p2_timing.h_display) && - (si->ps.p1_timing.v_display == si->ps.p2_timing.v_display)) - { - LOG(2,("INFO: correcting double detection of single panel!\n")); - - if (DACR(FP_TG_CTRL) & 0x80000000) - { - /* LVDS panel is on CRTC2, so clear false primary detection */ - si->ps.slaved_tmds1 = false; - si->ps.master_tmds1 = false; - si->ps.tmds1_active = false; - si->ps.p1_timing.h_display = 0; - si->ps.p1_timing.v_display = 0; - } - else - { - /* LVDS panel is on CRTC1, so clear false secondary detection */ - si->ps.slaved_tmds2 = false; - si->ps.master_tmds2 = false; - si->ps.tmds2_active = false; - si->ps.p2_timing.h_display = 0; - si->ps.p2_timing.v_display = 0; - } - } - - /* fetch panel(s) modeline(s) */ - if (si->ps.tmds1_active) - { - /* determine panel aspect ratio */ - si->ps.panel1_aspect = - (si->ps.p1_timing.h_display / ((float)si->ps.p1_timing.v_display)); - /* force widescreen type if requested */ - if (si->settings.force_ws) si->ps.panel1_aspect = 1.60; - /* horizontal timing */ - si->ps.p1_timing.h_sync_start = (DACR(FP_HSYNC_S) & 0x0000ffff) + 1; - si->ps.p1_timing.h_sync_end = (DACR(FP_HSYNC_E) & 0x0000ffff) + 1; - si->ps.p1_timing.h_total = (DACR(FP_HTOTAL) & 0x0000ffff) + 1; - /* vertical timing */ - si->ps.p1_timing.v_sync_start = (DACR(FP_VSYNC_S) & 0x0000ffff) + 1; - si->ps.p1_timing.v_sync_end = (DACR(FP_VSYNC_E) & 0x0000ffff) + 1; - si->ps.p1_timing.v_total = (DACR(FP_VTOTAL) & 0x0000ffff) + 1; - /* sync polarity */ - si->ps.p1_timing.flags = 0; - if (DACR(FP_TG_CTRL) & 0x00000001) si->ps.p1_timing.flags |= B_POSITIVE_VSYNC; - if (DACR(FP_TG_CTRL) & 0x00000010) si->ps.p1_timing.flags |= B_POSITIVE_HSYNC; - /* display enable polarity (not an official flag) */ - if (DACR(FP_TG_CTRL) & 0x10000000) si->ps.p1_timing.flags |= B_BLANK_PEDESTAL; - /* refreshrate: - * fix a DVI or laptop flatpanel to 60Hz refresh! */ - si->ps.p1_timing.pixel_clock = - (si->ps.p1_timing.h_total * si->ps.p1_timing.v_total * 60) / 1000; - } - if (si->ps.tmds2_active) - { - /* determine panel aspect ratio */ - si->ps.panel2_aspect = - (si->ps.p2_timing.h_display / ((float)si->ps.p2_timing.v_display)); - /* force widescreen type if requested */ - if (si->settings.force_ws) si->ps.panel2_aspect = 1.60; - /* horizontal timing */ - si->ps.p2_timing.h_sync_start = (DAC2R(FP_HSYNC_S) & 0x0000ffff) + 1; - si->ps.p2_timing.h_sync_end = (DAC2R(FP_HSYNC_E) & 0x0000ffff) + 1; - si->ps.p2_timing.h_total = (DAC2R(FP_HTOTAL) & 0x0000ffff) + 1; - /* vertical timing */ - si->ps.p2_timing.v_sync_start = (DAC2R(FP_VSYNC_S) & 0x0000ffff) + 1; - si->ps.p2_timing.v_sync_end = (DAC2R(FP_VSYNC_E) & 0x0000ffff) + 1; - si->ps.p2_timing.v_total = (DAC2R(FP_VTOTAL) & 0x0000ffff) + 1; - /* sync polarity */ - si->ps.p2_timing.flags = 0; - if (DAC2R(FP_TG_CTRL) & 0x00000001) si->ps.p2_timing.flags |= B_POSITIVE_VSYNC; - if (DAC2R(FP_TG_CTRL) & 0x00000010) si->ps.p2_timing.flags |= B_POSITIVE_HSYNC; - /* display enable polarity (not an official flag) */ - if (DAC2R(FP_TG_CTRL) & 0x10000000) si->ps.p2_timing.flags |= B_BLANK_PEDESTAL; - /* refreshrate: - * fix a DVI or laptop flatpanel to 60Hz refresh! */ - si->ps.p2_timing.pixel_clock = - (si->ps.p2_timing.h_total * si->ps.p2_timing.v_total * 60) / 1000; - } - - /* dump some panel configuration registers... */ - LOG(2,("INFO: Dumping flatpanel registers:\n")); - LOG(2,("DUALHEAD_CTRL: $%08x\n", NV_REG32(NV32_DUALHEAD_CTRL))); - LOG(2,("DAC1: FP_HDISPEND: %d\n", DACR(FP_HDISPEND))); - LOG(2,("DAC1: FP_HTOTAL: %d\n", DACR(FP_HTOTAL))); - LOG(2,("DAC1: FP_HCRTC: %d\n", DACR(FP_HCRTC))); - LOG(2,("DAC1: FP_HSYNC_S: %d\n", DACR(FP_HSYNC_S))); - LOG(2,("DAC1: FP_HSYNC_E: %d\n", DACR(FP_HSYNC_E))); - LOG(2,("DAC1: FP_HVALID_S: %d\n", DACR(FP_HVALID_S))); - LOG(2,("DAC1: FP_HVALID_E: %d\n", DACR(FP_HVALID_E))); - - LOG(2,("DAC1: FP_VDISPEND: %d\n", DACR(FP_VDISPEND))); - LOG(2,("DAC1: FP_VTOTAL: %d\n", DACR(FP_VTOTAL))); - LOG(2,("DAC1: FP_VCRTC: %d\n", DACR(FP_VCRTC))); - LOG(2,("DAC1: FP_VSYNC_S: %d\n", DACR(FP_VSYNC_S))); - LOG(2,("DAC1: FP_VSYNC_E: %d\n", DACR(FP_VSYNC_E))); - LOG(2,("DAC1: FP_VVALID_S: %d\n", DACR(FP_VVALID_S))); - LOG(2,("DAC1: FP_VVALID_E: %d\n", DACR(FP_VVALID_E))); - - LOG(2,("DAC1: FP_CHKSUM: $%08x = (dec) %d\n", DACR(FP_CHKSUM),DACR(FP_CHKSUM))); - LOG(2,("DAC1: FP_TST_CTRL: $%08x\n", DACR(FP_TST_CTRL))); - LOG(2,("DAC1: FP_TG_CTRL: $%08x\n", DACR(FP_TG_CTRL))); - LOG(2,("DAC1: FP_DEBUG0: $%08x\n", DACR(FP_DEBUG0))); - LOG(2,("DAC1: FP_DEBUG1: $%08x\n", DACR(FP_DEBUG1))); - LOG(2,("DAC1: FP_DEBUG2: $%08x\n", DACR(FP_DEBUG2))); - LOG(2,("DAC1: FP_DEBUG3: $%08x\n", DACR(FP_DEBUG3))); - - LOG(2,("DAC1: FUNCSEL: $%08x\n", NV_REG32(NV32_FUNCSEL))); - LOG(2,("DAC1: PANEL_PWR: $%08x\n", NV_REG32(NV32_PANEL_PWR))); - - if(si->ps.secondary_head) - { - LOG(2,("DAC2: FP_HDISPEND: %d\n", DAC2R(FP_HDISPEND))); - LOG(2,("DAC2: FP_HTOTAL: %d\n", DAC2R(FP_HTOTAL))); - LOG(2,("DAC2: FP_HCRTC: %d\n", DAC2R(FP_HCRTC))); - LOG(2,("DAC2: FP_HSYNC_S: %d\n", DAC2R(FP_HSYNC_S))); - LOG(2,("DAC2: FP_HSYNC_E: %d\n", DAC2R(FP_HSYNC_E))); - LOG(2,("DAC2: FP_HVALID_S:%d\n", DAC2R(FP_HVALID_S))); - LOG(2,("DAC2: FP_HVALID_E: %d\n", DAC2R(FP_HVALID_E))); - - LOG(2,("DAC2: FP_VDISPEND: %d\n", DAC2R(FP_VDISPEND))); - LOG(2,("DAC2: FP_VTOTAL: %d\n", DAC2R(FP_VTOTAL))); - LOG(2,("DAC2: FP_VCRTC: %d\n", DAC2R(FP_VCRTC))); - LOG(2,("DAC2: FP_VSYNC_S: %d\n", DAC2R(FP_VSYNC_S))); - LOG(2,("DAC2: FP_VSYNC_E: %d\n", DAC2R(FP_VSYNC_E))); - LOG(2,("DAC2: FP_VVALID_S: %d\n", DAC2R(FP_VVALID_S))); - LOG(2,("DAC2: FP_VVALID_E: %d\n", DAC2R(FP_VVALID_E))); - - LOG(2,("DAC2: FP_CHKSUM: $%08x = (dec) %d\n", DAC2R(FP_CHKSUM),DAC2R(FP_CHKSUM))); - LOG(2,("DAC2: FP_TST_CTRL: $%08x\n", DAC2R(FP_TST_CTRL))); - LOG(2,("DAC2: FP_TG_CTRL: $%08x\n", DAC2R(FP_TG_CTRL))); - LOG(2,("DAC2: FP_DEBUG0: $%08x\n", DAC2R(FP_DEBUG0))); - LOG(2,("DAC2: FP_DEBUG1: $%08x\n", DAC2R(FP_DEBUG1))); - LOG(2,("DAC2: FP_DEBUG2: $%08x\n", DAC2R(FP_DEBUG2))); - LOG(2,("DAC2: FP_DEBUG3: $%08x\n", DAC2R(FP_DEBUG3))); - - LOG(2,("DAC2: FUNCSEL: $%08x\n", NV_REG32(NV32_2FUNCSEL))); - LOG(2,("DAC2: PANEL_PWR: $%08x\n", NV_REG32(NV32_2PANEL_PWR))); - } - - /* determine flatpanel type(s) */ - //fixme?: linux checks on (only and) all dualhead cards, and only on DAC1... -//fixme: testing... - if (/*si->ps.tmds1_active && */1) - { - /* Read a indexed register to see if it indicates LVDS or TMDS panel presence. - * b0-7 = adress, b16 = 1 = write_enable */ - DACW(FP_TMDS_CTRL, ((1 << 16) | 0x04)); - /* (b0-7 = data) */ - if (DACR(FP_TMDS_DATA) & 0x01) - LOG(2,("INFO: Flatpanel on head 1 is LVDS type\n")); - else - LOG(2,("INFO: Flatpanel on head 1 is TMDS type\n")); - } -//fixme: testing... -// if (si->ps.tmds2_active) - if (si->ps.secondary_head) - { - /* Read a indexed register to see if it indicates LVDS or TMDS panel presence. - * b0-7 = adress, b16 = 1 = write_enable */ - DAC2W(FP_TMDS_CTRL, ((1 << 16) | 0x04)); - /* (b0-7 = data) */ - if (DAC2R(FP_TMDS_DATA) & 0x01) - LOG(2,("INFO: Flatpanel on head 2 is LVDS type\n")); - else - LOG(2,("INFO: Flatpanel on head 2 is TMDS type\n")); - } - - LOG(2,("INFO: End flatpanel registers dump.\n")); -} - -static void setup_output_matrix() -{ - /* setup defaults: */ - /* no monitors (output devices) detected */ - si->ps.monitors = 0x00; - /* head 1 will be the primary head */ - si->ps.crtc2_prim = false; - - /* setup output devices and heads */ - if (si->ps.secondary_head) - { - /* setup defaults: */ - /* connect analog outputs straight through */ - nv_general_output_select(false); - - /* presetup by the card's BIOS, we can't change this (lack of info) */ - if (si->ps.tmds1_active) si->ps.monitors |= 0x01; - if (si->ps.tmds2_active) si->ps.monitors |= 0x10; - /* detect analog monitors (confirmed working OK on NV18, NV28 and NV34): */ - /* sense analog monitor on primary connector */ - if (nv_dac_crt_connected()) si->ps.monitors |= 0x02; - /* sense analog monitor on secondary connector */ - if (nv_dac2_crt_connected()) si->ps.monitors |= 0x20; - - /* setup correct output and head use */ - switch (si->ps.monitors) - { - case 0x00: /* no monitor found at all */ - LOG(2,("INFO: head 1 has nothing connected;\n")); - LOG(2,("INFO: head 2 has nothing connected:\n")); - LOG(2,("INFO: defaulting to head 1 for primary use.\n")); - break; - case 0x01: /* digital panel on head 1, nothing on head 2 */ - LOG(2,("INFO: head 1 has a digital panel;\n")); - LOG(2,("INFO: head 2 has nothing connected:\n")); - LOG(2,("INFO: defaulting to head 1 for primary use.\n")); - break; - case 0x02: /* analog panel or CRT on head 1, nothing on head 2 */ - LOG(2,("INFO: head 1 has an analog panel or CRT;\n")); - LOG(2,("INFO: head 2 has nothing connected:\n")); - LOG(2,("INFO: defaulting to head 1 for primary use.\n")); - break; - case 0x03: /* both types on head 1, nothing on head 2 */ - LOG(2,("INFO: head 1 has a digital panel AND an analog panel or CRT;\n")); - LOG(2,("INFO: head 2 has nothing connected:\n")); - LOG(2,("INFO: correcting...\n")); - /* cross connect analog outputs so analog panel or CRT gets head 2 */ - nv_general_output_select(true); - LOG(2,("INFO: head 1 has a digital panel;\n")); - LOG(2,("INFO: head 2 has an analog panel or CRT:\n")); - LOG(2,("INFO: defaulting to head 1 for primary use.\n")); - break; - case 0x10: /* nothing on head 1, digital panel on head 2 */ - LOG(2,("INFO: head 1 has nothing connected;\n")); - LOG(2,("INFO: head 2 has a digital panel:\n")); - LOG(2,("INFO: defaulting to head 2 for primary use.\n")); - si->ps.crtc2_prim = true; - break; - case 0x20: /* nothing on head 1, analog panel or CRT on head 2 */ - LOG(2,("INFO: head 1 has nothing connected;\n")); - LOG(2,("INFO: head 2 has an analog panel or CRT:\n")); - LOG(2,("INFO: defaulting to head 2 for primary use.\n")); - si->ps.crtc2_prim = true; - break; - case 0x30: /* nothing on head 1, both types on head 2 */ - LOG(2,("INFO: head 1 has nothing connected;\n")); - LOG(2,("INFO: head 2 has a digital panel AND an analog panel or CRT:\n")); - LOG(2,("INFO: correcting...\n")); - /* cross connect analog outputs so analog panel or CRT gets head 1 */ - nv_general_output_select(true); - LOG(2,("INFO: head 1 has an analog panel or CRT;\n")); - LOG(2,("INFO: head 2 has a digital panel:\n")); - LOG(2,("INFO: defaulting to head 2 for primary use.\n")); - si->ps.crtc2_prim = true; - break; - case 0x11: /* digital panels on both heads */ - LOG(2,("INFO: head 1 has a digital panel;\n")); - LOG(2,("INFO: head 2 has a digital panel:\n")); - LOG(2,("INFO: defaulting to head 1 for primary use.\n")); - break; - case 0x12: /* analog panel or CRT on head 1, digital panel on head 2 */ - LOG(2,("INFO: head 1 has an analog panel or CRT;\n")); - LOG(2,("INFO: head 2 has a digital panel:\n")); - LOG(2,("INFO: defaulting to head 2 for primary use.\n")); - si->ps.crtc2_prim = true; - break; - case 0x21: /* digital panel on head 1, analog panel or CRT on head 2 */ - LOG(2,("INFO: head 1 has a digital panel;\n")); - LOG(2,("INFO: head 2 has an analog panel or CRT:\n")); - LOG(2,("INFO: defaulting to head 1 for primary use.\n")); - break; - case 0x22: /* analog panel(s) or CRT(s) on both heads */ - LOG(2,("INFO: head 1 has an analog panel or CRT;\n")); - LOG(2,("INFO: head 2 has an analog panel or CRT:\n")); - LOG(2,("INFO: defaulting to head 1 for primary use.\n")); - break; - case 0x32: /* more than two monitors connected to just two outputs: illegal! */ - //general fixme: - //NV40 architecture contains (an) additional switch(es) to - //connect a CRTC/DAC combination to a connector. We can't work as - //usual (yet) because this interferes via BIOS card pre-programming. - // - //Also: it looks as if each pixelclock PLL can select different CRTC's - //as well now via a new register: one PLL can be driving both CRTC's - //and there's nothing we can do about that (yet). (DVI/dualhead trouble) - default: /* more than two monitors connected to just two outputs: illegal! */ - LOG(2,("INFO: illegal monitor setup ($%02x):\n", si->ps.monitors)); - LOG(2,("INFO: defaulting to head 1 for primary use.\n")); - break; - } - } - else /* singlehead cards */ - { - /* presetup by the card's BIOS, we can't change this (lack of info) */ - if (si->ps.tmds1_active) si->ps.monitors |= 0x01; - /* detect analog monitor (confirmed working OK on all cards): */ - /* sense analog monitor on primary connector */ - if (nv_dac_crt_connected()) si->ps.monitors |= 0x02; - } -} - -void get_panel_modes(display_mode *p1, display_mode *p2, bool *pan1, bool *pan2) -{ - if (si->ps.tmds1_active) - { - /* timing ('modeline') */ - p1->timing = si->ps.p1_timing; - /* setup the rest */ - p1->space = B_CMAP8; - p1->virtual_width = p1->timing.h_display; - p1->virtual_height = p1->timing.v_display; - p1->h_display_start = 0; - p1->v_display_start = 0; - p1->flags = 0; - *pan1 = true; - } - else - *pan1 = false; - - if (si->ps.tmds2_active) - { - /* timing ('modeline') */ - p2->timing = si->ps.p2_timing; - /* setup the rest */ - p2->space = B_CMAP8; - p2->virtual_width = p2->timing.h_display; - p2->virtual_height = p2->timing.v_display; - p2->h_display_start = 0; - p2->v_display_start = 0; - p2->flags = 0; - *pan2 = true; - } - else - *pan2 = false; -} - -static void pinsnv30_arch_fake(void) -{ - /* we have a extended PLL */ - si->ps.ext_pll = true; - /* carefull not to take to high limits, and high should be >= 2x low. */ - si->ps.max_system_vco = 350; - si->ps.min_system_vco = 128; - if (si->ps.ext_pll) - { - si->ps.max_pixel_vco = 600; - si->ps.min_pixel_vco = 220; - si->ps.max_video_vco = 600; - si->ps.min_video_vco = 220; - } - else - { - si->ps.max_pixel_vco = 350; - si->ps.min_pixel_vco = 128; - si->ps.max_video_vco = 350; - si->ps.min_video_vco = 128; - } - si->ps.max_dac1_clock = 350; - si->ps.max_dac1_clock_8 = 350; - si->ps.max_dac1_clock_16 = 350; - /* 'failsave' values */ - si->ps.max_dac1_clock_24 = 320; - si->ps.max_dac1_clock_32 = 280; - si->ps.max_dac1_clock_32dh = 250; - /* secondary head */ - /* GeForceFX cards have dual integrated DACs with identical capability */ - /* (called nview technology) */ - si->ps.max_dac2_clock = 350; - si->ps.max_dac2_clock_8 = 350; - si->ps.max_dac2_clock_16 = 350; - /* 'failsave' values */ - si->ps.max_dac2_clock_24 = 320; - si->ps.max_dac2_clock_32 = 280; - si->ps.max_dac2_clock_32dh = 250; - //fixme: primary & secondary_dvi should be overrule-able via nv.settings - si->ps.primary_dvi = false; - si->ps.secondary_dvi = false; - /* not used (yet) because no coldstart will be attempted (yet) */ - si->ps.std_engine_clock = 190; - si->ps.std_memory_clock = 190; -} - -static void getRAMsize_arch_nv10_20_30_40(void) -{ - uint32 dev_manID = CFGR(DEVID); - uint32 strapinfo = NV_REG32(NV32_NV10STRAPINFO); - - switch (dev_manID) - { - case 0x01a010de: /* Nvidia GeForce2 Integrated GPU */ - case 0x01f010de: /* Nvidia GeForce4 MX Integrated GPU */ - /* the kerneldriver already determined the amount of RAM these cards have at - * their disposal (UMA, values read from PCI config space in other device) */ - LOG(8,("INFO: nVidia GPU with UMA detected\n")); - break; - default: - LOG(8,("INFO: (Memory detection) Strapinfo value is: $%08x\n", strapinfo)); - - switch ((strapinfo & 0x3ff00000) >> 20) - { - case 2: - si->ps.memory_size = 2 * 1024 * 1024; - break; - case 4: - si->ps.memory_size = 4 * 1024 * 1024; - break; - case 8: - si->ps.memory_size = 8 * 1024 * 1024; - break; - case 16: - si->ps.memory_size = 16 * 1024 * 1024; - break; - case 32: - si->ps.memory_size = 32 * 1024 * 1024; - break; - case 64: - si->ps.memory_size = 64 * 1024 * 1024; - break; - case 128: - si->ps.memory_size = 128 * 1024 * 1024; - break; - case 256: - si->ps.memory_size = 256 * 1024 * 1024; - break; - case 512: - si->ps.memory_size = 512 * 1024 * 1024; - break; - default: - si->ps.memory_size = 16 * 1024 * 1024; - - LOG(8,("INFO: NV10/20/30 architecture chip with unknown RAM amount detected;\n")); - LOG(8,("INFO: Setting 16Mb\n")); - break; - } - } -} - -static void getstrap_arch_nv10_20_30_40(void) -{ - uint32 strapinfo = NV_REG32(NV32_NVSTRAPINFO2); - - /* all cards are dualhead cards these days */ - si->ps.secondary_head = true; - - /* determine PLL reference crystal frequency: three types are used... */ - if (strapinfo & 0x00000040) - si->ps.f_ref = 14.31818; - else - si->ps.f_ref = 13.50000; - - if (si->ps.secondary_head) - { - if (strapinfo & 0x00400000) si->ps.f_ref = 27.00000; - } -} - -void dump_pins(void) -{ - LOG(2,("INFO: pinsdump follows:\n")); - LOG(2,("PLL type: ")); - if (si->ps.ext_pll) LOG(2,("extended\n")); else LOG(2,("standard\n")); - LOG(2,("f_ref: %fMhz\n", si->ps.f_ref)); - LOG(2,("max_system_vco: %dMhz\n", si->ps.max_system_vco)); - LOG(2,("min_system_vco: %dMhz\n", si->ps.min_system_vco)); - LOG(2,("max_pixel_vco: %dMhz\n", si->ps.max_pixel_vco)); - LOG(2,("min_pixel_vco: %dMhz\n", si->ps.min_pixel_vco)); - LOG(2,("max_video_vco: %dMhz\n", si->ps.max_video_vco)); - LOG(2,("min_video_vco: %dMhz\n", si->ps.min_video_vco)); - LOG(2,("std_engine_clock: %dMhz\n", si->ps.std_engine_clock)); - LOG(2,("std_memory_clock: %dMhz\n", si->ps.std_memory_clock)); - LOG(2,("max_dac1_clock: %dMhz\n", si->ps.max_dac1_clock)); - LOG(2,("max_dac1_clock_8: %dMhz\n", si->ps.max_dac1_clock_8)); - LOG(2,("max_dac1_clock_16: %dMhz\n", si->ps.max_dac1_clock_16)); - LOG(2,("max_dac1_clock_24: %dMhz\n", si->ps.max_dac1_clock_24)); - LOG(2,("max_dac1_clock_32: %dMhz\n", si->ps.max_dac1_clock_32)); - LOG(2,("max_dac1_clock_32dh: %dMhz\n", si->ps.max_dac1_clock_32dh)); - LOG(2,("max_dac2_clock: %dMhz\n", si->ps.max_dac2_clock)); - LOG(2,("max_dac2_clock_8: %dMhz\n", si->ps.max_dac2_clock_8)); - LOG(2,("max_dac2_clock_16: %dMhz\n", si->ps.max_dac2_clock_16)); - LOG(2,("max_dac2_clock_24: %dMhz\n", si->ps.max_dac2_clock_24)); - LOG(2,("max_dac2_clock_32: %dMhz\n", si->ps.max_dac2_clock_32)); - LOG(2,("max_dac2_clock_32dh: %dMhz\n", si->ps.max_dac2_clock_32dh)); - LOG(2,("secondary_head: ")); - if (si->ps.secondary_head) LOG(2,("present\n")); else LOG(2,("absent\n")); -// LOG(2,("primary_dvi: ")); -// if (si->ps.primary_dvi) LOG(2,("present\n")); else LOG(2,("absent\n")); -// LOG(2,("secondary_dvi: ")); -// if (si->ps.secondary_dvi) LOG(2,("present\n")); else LOG(2,("absent\n")); - LOG(2,("card memory_size: %3.3fMb\n", (si->ps.memory_size / (1024.0 * 1024.0)))); - LOG(2,("laptop: ")); - if (si->ps.laptop) LOG(2,("yes\n")); else LOG(2,("no\n")); - if (si->ps.tmds1_active) - { - LOG(2,("found DFP (digital flatpanel) on CRTC1; CRTC1 is ")); - if (si->ps.slaved_tmds1) LOG(2,("slaved\n")); else LOG(2,("master\n")); - LOG(2,("panel width: %d, height: %d, aspect ratio: %1.2f\n", - si->ps.p1_timing.h_display, si->ps.p1_timing.v_display, si->ps.panel1_aspect)); - } - if (si->ps.tmds2_active) - { - LOG(2,("found DFP (digital flatpanel) on CRTC2; CRTC2 is ")); - if (si->ps.slaved_tmds2) LOG(2,("slaved\n")); else LOG(2,("master\n")); - LOG(2,("panel width: %d, height: %d, aspect ratio: %1.2f\n", - si->ps.p2_timing.h_display, si->ps.p2_timing.v_display, si->ps.panel2_aspect)); - } - LOG(2,("monitor (output devices) setup matrix: $%02x\n", si->ps.monitors)); - LOG(2,("INFO: end pinsdump.\n")); -} diff --git a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_proto.h b/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_proto.h deleted file mode 100644 index b72faf9867..0000000000 --- a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_proto.h +++ /dev/null @@ -1,116 +0,0 @@ -/* general card functions */ -status_t nv_general_powerup(void); -status_t nv_set_cas_latency(void); -void setup_virtualized_heads(bool); -void set_crtc_owner(bool); -status_t nv_general_output_select(bool); -status_t nv_general_head_select(bool); -status_t nv_general_validate_pic_size (display_mode *target, uint32 *bytes_per_row, bool *acc_mode); - -/* apsed: logging macros */ -#define MSG(args) do { /* if needed or si->settings with si NULL */ \ - nv_log args; \ -} while (0) -#define LOG(level_bit, args) do { \ - uint32 mod = (si->settings.logmask & 0xfffffff0) & MODULE_BIT; \ - uint32 lev = (si->settings.logmask & ~0xfffffff0) & level_bit; \ - if (mod && lev) nv_log args; \ -} while (0) - -/* support functions */ -void delay(bigtime_t i); -void nv_log(char *format, ...); - -/* i2c functions */ -char i2c_flag_error (char ErrNo); -void i2c_bstart (uint8 BusNR); -void i2c_bstop (uint8 BusNR); -uint8 i2c_readbyte(uint8 BusNR, bool Ack); -bool i2c_writebyte (uint8 BusNR, uint8 byte); -void i2c_readbuffer (uint8 BusNR, uint8* buf, uint8 size); -void i2c_writebuffer (uint8 BusNR, uint8* buf, uint8 size); -status_t i2c_init(void); - -/* card info functions */ -status_t parse_pins(void); -void set_pll(uint32 reg, uint32 clk); -void get_panel_modes(display_mode *p1, display_mode *p2, bool *pan1, bool *pan2); -void fake_panel_start(void); -void set_specs(void); -void dump_pins(void); - -/* DAC functions */ -bool nv_dac_crt_connected(void); -status_t nv_dac_mode(int,float); -status_t nv_dac_palette(uint8*,uint8*,uint8*); -status_t nv_dac_pix_pll_find(display_mode target,float * result,uint8 *,uint8 *,uint8 *, uint8); -status_t nv_dac_set_pix_pll(display_mode target); -status_t nv_dac_sys_pll_find(float, float*, uint8*, uint8*, uint8*, uint8); - -/* DAC2 functions */ -bool nv_dac2_crt_connected(void); -status_t nv_dac2_mode(int,float); -status_t nv_dac2_palette(uint8*,uint8*,uint8*); -status_t nv_dac2_pix_pll_find(display_mode target,float * result,uint8 *,uint8 *,uint8 *, uint8); -status_t nv_dac2_set_pix_pll(display_mode target); - -/* CRTC1 functions */ -status_t nv_crtc_interrupt_enable(bool); -status_t nv_crtc_update_fifo(void); -status_t nv_crtc_validate_timing( - uint16 *hd_e,uint16 *hs_s,uint16 *hs_e,uint16 *ht, - uint16 *vd_e,uint16 *vs_s,uint16 *vs_e,uint16 *vt); -status_t nv_crtc_set_timing(display_mode target); -status_t nv_crtc_depth(int mode); -status_t nv_crtc_set_display_start(uint32 startadd,uint8 bpp); -status_t nv_crtc_set_display_pitch(void); -status_t nv_crtc_dpms(bool, bool, bool, bool); -status_t nv_crtc_mem_priority(uint8); -status_t nv_crtc_cursor_init(void); -status_t nv_crtc_cursor_define(uint8*,uint8*); -status_t nv_crtc_cursor_position(uint16 x ,uint16 y); -status_t nv_crtc_cursor_show(void); -status_t nv_crtc_cursor_hide(void); - -/* CRTC2 functions */ -status_t nv_crtc2_interrupt_enable(bool); -status_t nv_crtc2_update_fifo(void); -status_t nv_crtc2_validate_timing( - uint16 *hd_e,uint16 *hs_s,uint16 *hs_e,uint16 *ht, - uint16 *vd_e,uint16 *vs_s,uint16 *vs_e,uint16 *vt); -status_t nv_crtc2_set_timing(display_mode target); -status_t nv_crtc2_depth(int mode); -status_t nv_crtc2_set_display_start(uint32 startadd,uint8 bpp); -status_t nv_crtc2_set_display_pitch(void); -status_t nv_crtc2_dpms(bool, bool, bool, bool); -status_t nv_crtc2_mem_priority(uint8); -status_t nv_crtc2_cursor_init(void); -status_t nv_crtc2_cursor_define(uint8*,uint8*); -status_t nv_crtc2_cursor_position(uint16 x ,uint16 y); -status_t nv_crtc2_cursor_show(void); -status_t nv_crtc2_cursor_hide(void); - -/* acceleration functions */ -status_t check_acc_capability(uint32 feature); -/* DMA versions */ -status_t nv_acc_wait_idle_dma(void); -status_t nv_acc_init_dma(void); -void nv_acc_assert_fifo_dma(void); -void SCREEN_TO_SCREEN_BLIT_DMA(engine_token *et, blit_params *list, uint32 count); -void SCREEN_TO_SCREEN_TRANSPARENT_BLIT_DMA(engine_token *et, uint32 transparent_colour, blit_params *list, uint32 count); -void SCREEN_TO_SCREEN_SCALED_FILTERED_BLIT_DMA(engine_token *et, scaled_blit_params *list, uint32 count); -void FILL_RECTANGLE_DMA(engine_token *et, uint32 color, fill_rect_params *list, uint32 count); -void INVERT_RECTANGLE_DMA(engine_token *et, fill_rect_params *list, uint32 count); -void FILL_SPAN_DMA(engine_token *et, uint32 color, uint16 *list, uint32 count); - -/* backend scaler functions */ -status_t check_overlay_capability(uint32 feature); -void nv_bes_move_overlay(void); -status_t nv_bes_to_crtc(bool crtc); -status_t nv_bes_init(void); -status_t nv_configure_bes - (const overlay_buffer *ob, const overlay_window *ow,const overlay_view *ov, int offset); -status_t nv_release_bes(void); - -/* driver structures and enums */ -enum{BPP8 = 0, BPP15 = 1, BPP16 = 2, BPP24 = 3, BPP32 = 4}; diff --git a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_std.h b/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_std.h deleted file mode 100644 index cc21aaecb0..0000000000 --- a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_std.h +++ /dev/null @@ -1,10 +0,0 @@ -#include -#include -#include -#include -#include "DriverInterface.h" -#include "nv_globals.h" -//apsed #include "nv_extern.h" -#include "nv_proto.h" -#include "nv_macros.h" -#include "nv_acc.h" diff --git a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_support.c b/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_support.c deleted file mode 100644 index c7dc8a1378..0000000000 --- a/src/add-ons/accelerants/nvidia_gpgpu/engine/nv_support.c +++ /dev/null @@ -1,38 +0,0 @@ -/* Some commmon support functions */ -/* Mark Watson 2/2000; - * Rudolf Cornelissen 1/2004-11/2005 */ - -#define MODULE_BIT 0x00000800 - -#include -#include "nv_std.h" - -/*delays in multiple of microseconds*/ -void delay(bigtime_t i) -{ - bigtime_t start=system_time(); - while(system_time()-startvendor_id, si->device_id, si->bus, si->device, si->function, - accelerantIsClone); - myhand=fopen(fname,"a+"); - - if (myhand == NULL) return; - - va_start(args,fmt); - vsprintf (buffer, fmt, args); - fprintf(myhand, "%s", buffer); - fclose(myhand); -} diff --git a/src/add-ons/accelerants/nvidia_gpgpu/valid_mode_list b/src/add-ons/accelerants/nvidia_gpgpu/valid_mode_list deleted file mode 100644 index 4c0f04023f..0000000000 --- a/src/add-ons/accelerants/nvidia_gpgpu/valid_mode_list +++ /dev/null @@ -1,34 +0,0 @@ -/*This file can be used to define custom timing for your monitor - * The format of each line is: - * { - * pixel clock frequency (kHz) - * width - * h-sync pulse start - * h-sync pulse end - * total pixels in line - * height - * v-sync pulse start - * v-sync pulse end - * total lines in frame - * sync polarity (0 is -ve,B_POSITIVE_HYSNC,B_POSITIVE_VSYNC) - * } - * - *To use this you must: - * Uncomment VALID MODE REQUIRED - * Fill in a number of modes that work with your display - * Change VALID MODES from three to the no. you defined - * run these commands: - * touch ProposeDisplayMode.c - * make install - */ - -//#define VALID_MODE_REQUIRED 1 - -#define VALID_MODES 3 - -/*note colour depth and mode flags are ignored*/ -static const display_timing valid_mode_list[] = { -{31500,640,648,744,840,480,481,500,500,0}, -{49500,800,808,888,1056,600,601,620,625,B_POSITIVE_HSYNC|B_POSITIVE_VSYNC}, -{78750,1024,1032,1128,1312,768,769,788,800,B_POSITIVE_HSYNC|B_POSITIVE_VSYNC} -}; diff --git a/src/add-ons/kernel/drivers/graphics/Jamfile b/src/add-ons/kernel/drivers/graphics/Jamfile index 4b0b47aec8..e1a282a73f 100644 --- a/src/add-ons/kernel/drivers/graphics/Jamfile +++ b/src/add-ons/kernel/drivers/graphics/Jamfile @@ -9,7 +9,6 @@ SubInclude HAIKU_TOP src add-ons kernel drivers graphics intel_extreme ; SubInclude HAIKU_TOP src add-ons kernel drivers graphics matrox ; SubInclude HAIKU_TOP src add-ons kernel drivers graphics neomagic ; SubInclude HAIKU_TOP src add-ons kernel drivers graphics nvidia ; -SubInclude HAIKU_TOP src add-ons kernel drivers graphics nvidia_gpgpu ; SubInclude HAIKU_TOP src add-ons kernel drivers graphics radeon ; SubInclude HAIKU_TOP src add-ons kernel drivers graphics radeon_hd ; SubInclude HAIKU_TOP src add-ons kernel drivers graphics s3 ; diff --git a/src/add-ons/kernel/drivers/graphics/nvidia_gpgpu/Jamfile b/src/add-ons/kernel/drivers/graphics/nvidia_gpgpu/Jamfile deleted file mode 100644 index 25f137c268..0000000000 --- a/src/add-ons/kernel/drivers/graphics/nvidia_gpgpu/Jamfile +++ /dev/null @@ -1,10 +0,0 @@ -SubDir HAIKU_TOP src add-ons kernel drivers graphics nvidia_gpgpu ; - -SetSubDirSupportedPlatformsBeOSCompatible ; - -UsePrivateHeaders graphics libroot ; -UsePrivateHeaders [ FDirName graphics nvidia_gpgpu ] ; - -KernelAddon nvidia_gpgpu : - driver.c -; diff --git a/src/add-ons/kernel/drivers/graphics/nvidia_gpgpu/README.html b/src/add-ons/kernel/drivers/graphics/nvidia_gpgpu/README.html deleted file mode 100644 index 67b7ef30a7..0000000000 --- a/src/add-ons/kernel/drivers/graphics/nvidia_gpgpu/README.html +++ /dev/null @@ -1,33 +0,0 @@ - - - - - Readme for Haiku Unified Nvidia GPGPU graphics driver - - -

Unified Nvidia GPGPU graphics driver for Haiku



-
-

NOTE PLEASE:
-You use this software at your own risk! Although I don't expect it to damage your PC, videocard or Monitor, I cannot guarantee this!

-
-

Supported cards (as far as is known):

-
    -
  • None yet (will be G80+, I hope, also known as General Purpose GPU architecture cards); -
-
-
-

Features:

-
    -
  • None (yet?). -
-Known limitations: -
    -
  • Everything. -
-
-
-
-Rudolf Cornelissen. -

(Page last updated on June 9, 2008)

- - diff --git a/src/add-ons/kernel/drivers/graphics/nvidia_gpgpu/UPDATE.html b/src/add-ons/kernel/drivers/graphics/nvidia_gpgpu/UPDATE.html deleted file mode 100644 index 8475f05d88..0000000000 --- a/src/add-ons/kernel/drivers/graphics/nvidia_gpgpu/UPDATE.html +++ /dev/null @@ -1,20 +0,0 @@ - - -Changes - - -

Changes done for each driverversion:

-

head (SVN 0.00, Rudolf)

-
    -Note please:
    -
      -
    • GF8xxx is recognized, but not supported. yet? -
    -
-

Still todo:

-
    -
  • Hmm, everything. -
-

- - diff --git a/src/add-ons/kernel/drivers/graphics/nvidia_gpgpu/driver.c b/src/add-ons/kernel/drivers/graphics/nvidia_gpgpu/driver.c deleted file mode 100644 index 11858429c6..0000000000 --- a/src/add-ons/kernel/drivers/graphics/nvidia_gpgpu/driver.c +++ /dev/null @@ -1,1237 +0,0 @@ -/* - Copyright 1999, Be Incorporated. All Rights Reserved. - This file may be used under the terms of the Be Sample Code License. - - Other authors: - Mark Watson; - Rudolf Cornelissen 3/2002-6/2008. -*/ - - -#include "DriverInterface.h" -#include "nv_macros.h" - -#include -#include -#include -#include -#include -#include -#include - -#include -#include -#include - -#define get_pci(o, s) (*pci_bus->read_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s)) -#define set_pci(o, s, v) (*pci_bus->write_pci_config)(pcii->bus, pcii->device, pcii->function, (o), (s), (v)) - -#define MAX_DEVICES 8 - -#ifndef __HAIKU__ -# undef B_USER_CLONEABLE_AREA -# define B_USER_CLONEABLE_AREA 0 -#endif - -/* Tell the kernel what revision of the driver API we support */ -int32 api_version = B_CUR_DRIVER_API_VERSION; - -/* these structures are private to the kernel driver */ -typedef struct device_info device_info; - -typedef struct { - timer te; /* timer entry for add_timer() */ - device_info *di; /* pointer to the owning device */ - bigtime_t when_target; /* when we're supposed to wake up */ -} timer_info; - -struct device_info { - uint32 is_open; /* a count of how many times the devices has been opened */ - area_id shared_area; /* the area shared between the driver and all of the accelerants */ - shared_info *si; /* a pointer to the shared area, for convenience */ - vuint32 *regs; /* kernel's pointer to memory mapped registers */ - pci_info pcii; /* a convenience copy of the pci info for this device */ - char name[B_OS_NAME_LENGTH]; /* where we keep the name of the device for publishing and comparing */ -}; - -typedef struct { - uint32 count; /* number of devices actually found */ - benaphore kernel; /* for serializing opens/closes */ - char *device_names[MAX_DEVICES+1]; /* device name pointer storage */ - device_info di[MAX_DEVICES]; /* device specific stuff */ -} DeviceData; - -/* prototypes for our private functions */ -static status_t open_hook(const char* name, uint32 flags, void** cookie); -static status_t close_hook(void* dev); -static status_t free_hook(void* dev); -static status_t read_hook(void* dev, off_t pos, void* buf, size_t* len); -static status_t write_hook(void* dev, off_t pos, const void* buf, size_t* len); -static status_t control_hook(void* dev, uint32 msg, void *buf, size_t len); -static status_t map_device(device_info *di); -static void unmap_device(device_info *di); -static void probe_devices(void); -static int32 nv_interrupt(void *data); - -static DeviceData *pd; -static isa_module_info *isa_bus = NULL; -static pci_module_info *pci_bus = NULL; -static device_hooks graphics_device_hooks = { - open_hook, - close_hook, - free_hook, - control_hook, - read_hook, - write_hook, - NULL, - NULL, - NULL, - NULL -}; - -#define VENDOR_ID_NVIDIA 0x10de /* Nvidia */ -#define VENDOR_ID_ELSA 0x1048 /* Elsa GmbH */ -#define VENDOR_ID_NVSTBSGS 0x12d2 /* Nvidia STB/SGS-Thompson */ -#define VENDOR_ID_VARISYS 0x1888 /* Varisys Limited */ - -static uint16 nvidia_device_list[] = { -#if 0 - // TODO: these cards are not yet supported - 0x0191, /* Nvidia GeForce 8800 GTX (G80) */ - 0x0193, /* Nvidia GeForce 8800 GTS (G80) */ - 0x0194, /* Nvidia GeForce 8800 Ultra (G80) */ - 0x0400, /* Nvidia GeForce 8600 GTS (G84) */ - 0x0401, /* Nvidia GeForce 8600 GT (G84) */ - 0x0402, /* Nvidia GeForce 8600 GT (G84) */ - 0x0403, /* Nvidia GeForce 8600 GS (G84) */ - 0x0404, /* Nvidia GeForce 8400 GS (G84) */ - 0x0406, /* Nvidia GeForce 8300 GS (G84) */ - 0x0407, /* Nvidia GeForce 8600M GT */ - 0x0420, /* Nvidia GeForce 8400 SE (G86) */ - 0x0421, /* Nvidia GeForce 8500 GT (G86) */ - 0x0422, /* Nvidia GeForce 8400 GS (G86) */ - 0x0423, /* Nvidia GeForce 8300 GS (G86) */ - 0x0424, /* Nvidia GeForce 8400 GS (G86) */ - 0x0426, /* Nvidia GeForce 8400M GT (G86M) */ - 0x0600, /* Nvidia GeForce 8800 GTS 512 (G92) */ - 0x0602, /* Nvidia GeForce 8800 GT (G92) */ - 0x0606, /* Nvidia GeForce 8800 GS (G92) */ - 0x060d, /* Nvidia GeForce 8800 GS (G92) */ - 0x0611, /* Nvidia GeForce 8800 GT (G92) */ - 0x0642, /* Nvidia GeForce 8400 GS (G96) */ - 0x06e2, /* Nvidia GeForce 8400 (G98) */ - 0x06e3, /* Nvidia GeForce 8300 GS (G98) */ - 0x06e4, /* Nvidia GeForce 8400 GS (G98) */ -#endif - 0 -}; - -static struct { - uint16 vendor; - uint16 *devices; -} SupportedDevices[] = { - {VENDOR_ID_NVIDIA, nvidia_device_list}, - {0x0000, NULL} -}; - -static nv_settings sSettings = { // see comments in nvidia_gpgpu.settings - /* for driver */ - DRIVER_PREFIX ".accelerant", - "none", // primary - false, // dumprom - /* for accelerant */ - 0x00000000, // logmask - 0, // memory - true, // usebios - true, // hardcursor - false, // switchhead - false, // pgm_panel - false, // force_sync - true, // force_ws - 0, // gpu_clk - 0, // ram_clk -}; - - -static void -dumprom(void *rom, uint32 size, pci_info pcii) -{ - int fd; - uint32 cnt; - char fname[64]; - - /* determine the romfile name: we need split-up per card in the system */ - sprintf (fname, kUserDirectory "/" DRIVER_PREFIX "." DEVICE_FORMAT ".rom", - pcii.vendor_id, pcii.device_id, pcii.bus, pcii.device, pcii.function); - - fd = open (fname, O_WRONLY | O_CREAT, 0666); - if (fd < 0) return; - - /* apparantly max. 32kb may be written at once; - * the ROM size is a multiple of that anyway. */ - for (cnt = 0; (cnt < size); cnt += 32768) - write (fd, ((void *)(((uint8 *)rom) + cnt)), 32768); - close (fd); -} - - -/*! return 1 if vblank interrupt has occured */ -static int -caused_vbi_crtc1(vuint32 * regs) -{ - return (NV_REG32(NV32_CRTC_INTS) & 0x00000001); -} - - -/*! clear the vblank interrupt */ -static void -clear_vbi_crtc1(vuint32 * regs) -{ - NV_REG32(NV32_CRTC_INTS) = 0x00000001; -} - - -static void -enable_vbi_crtc1(vuint32 * regs) -{ - /* clear the vblank interrupt */ - NV_REG32(NV32_CRTC_INTS) = 0x00000001; - /* enable nVidia interrupt source vblank */ - NV_REG32(NV32_CRTC_INTE) |= 0x00000001; - /* enable nVidia interrupt system hardware (b0-1) */ - NV_REG32(NV32_MAIN_INTE) = 0x00000001; -} - - -static void -disable_vbi_crtc1(vuint32 * regs) -{ - /* disable nVidia interrupt source vblank */ - NV_REG32(NV32_CRTC_INTE) &= 0xfffffffe; - /* clear the vblank interrupt */ - NV_REG32(NV32_CRTC_INTS) = 0x00000001; -} - - -/*! return 1 if vblank interrupt has occured */ -static int -caused_vbi_crtc2(vuint32 * regs) -{ - return (NV_REG32(NV32_CRTC2_INTS) & 0x00000001); -} - - -/*! clear the vblank interrupt */ -static void -clear_vbi_crtc2(vuint32 * regs) -{ - NV_REG32(NV32_CRTC2_INTS) = 0x00000001; -} - - -static void -enable_vbi_crtc2(vuint32 * regs) -{ - /* clear the vblank interrupt */ - NV_REG32(NV32_CRTC2_INTS) = 0x00000001; - /* enable nVidia interrupt source vblank */ - NV_REG32(NV32_CRTC2_INTE) |= 0x00000001; - /* enable nVidia interrupt system hardware (b0-1) */ - NV_REG32(NV32_MAIN_INTE) = 0x00000001; -} - - -static void -disable_vbi_crtc2(vuint32 * regs) -{ - /* disable nVidia interrupt source vblank */ - NV_REG32(NV32_CRTC2_INTE) &= 0xfffffffe; - /* clear the vblank interrupt */ - NV_REG32(NV32_CRTC2_INTS) = 0x00000001; -} - - -//fixme: -//dangerous code, on singlehead cards better not try accessing secondary head -//registers (card might react in unpredictable ways, though there's only a small -//chance we actually run into this). -//fix requires (some) card recognition code to be moved from accelerant to -//kerneldriver... -static void -disable_vbi_all(vuint32 * regs) -{ - /* disable nVidia interrupt source vblank */ - NV_REG32(NV32_CRTC_INTE) &= 0xfffffffe; - /* clear the vblank interrupt */ - NV_REG32(NV32_CRTC_INTS) = 0x00000001; - - /* disable nVidia interrupt source vblank */ - NV_REG32(NV32_CRTC2_INTE) &= 0xfffffffe; - /* clear the vblank interrupt */ - NV_REG32(NV32_CRTC2_INTS) = 0x00000001; - - /* disable nVidia interrupt system hardware (b0-1) */ - NV_REG32(NV32_MAIN_INTE) = 0x00000000; -} - - -static status_t -map_device(device_info *di) -{ - char buffer[B_OS_NAME_LENGTH]; /*memory for device name*/ - shared_info *si = di->si; - uint32 tmpUlong, tmpROMshadow; - pci_info *pcii = &(di->pcii); - system_info sysinfo; - - /* variables for making copy of ROM */ - uint8* rom_temp; - area_id rom_area = -1; - - /* Nvidia cards have registers in [0] and framebuffer in [1] */ - int registers = 0; - int frame_buffer = 1; - - /* enable memory mapped IO, disable VGA I/O - this is defined in the PCI standard */ - tmpUlong = get_pci(PCI_command, 2); - /* enable PCI access */ - tmpUlong |= PCI_command_memory; - /* enable busmastering */ - tmpUlong |= PCI_command_master; - /* disable ISA I/O access */ - tmpUlong &= ~PCI_command_io; - set_pci(PCI_command, 2, tmpUlong); - - /*work out which version of BeOS is running*/ - get_system_info(&sysinfo); - if (0)//sysinfo.kernel_build_date[0]=='J')/*FIXME - better ID version*/ - { - si->use_clone_bugfix = 1; - } - else - { - si->use_clone_bugfix = 0; - } - - /* work out a name for the register mapping */ - sprintf(buffer, DEVICE_FORMAT " regs", - di->pcii.vendor_id, di->pcii.device_id, - di->pcii.bus, di->pcii.device, di->pcii.function); - - /* get a virtual memory address for the registers*/ - si->regs_area = map_physical_memory( - buffer, - /* WARNING: Nvidia needs to map regs as viewed from PCI space! */ - di->pcii.u.h0.base_registers_pci[registers], - di->pcii.u.h0.base_register_sizes[registers], - B_ANY_KERNEL_ADDRESS, - B_USER_CLONEABLE_AREA | (si->use_clone_bugfix ? B_READ_AREA|B_WRITE_AREA : 0), - (void **)&(di->regs)); - si->clone_bugfix_regs = (uint32 *) di->regs; - - /* if mapping registers to vmem failed then pass on error */ - if (si->regs_area < 0) return si->regs_area; - - /* work out a name for the ROM mapping*/ - sprintf(buffer, DEVICE_FORMAT " rom", - di->pcii.vendor_id, di->pcii.device_id, - di->pcii.bus, di->pcii.device, di->pcii.function); - - /* preserve ROM shadowing setting, we need to restore the current state later on. */ - /* warning: - * 'don't touch': (confirmed) NV04, NV05, NV05-M64, NV11 all shutoff otherwise. - * NV18, NV28 and NV34 keep working. - * confirmed NV28 and NV34 to use upper part of shadowed ROM for scratch purposes, - * however the actual ROM content (so the used part) is intact (confirmed). */ - tmpROMshadow = get_pci(NVCFG_ROMSHADOW, 4); - /* temporary disable ROM shadowing, we want the guaranteed exact contents of the chip */ - set_pci(NVCFG_ROMSHADOW, 4, 0); - - /* get ROM memory mapped base adress - this is defined in the PCI standard */ - tmpUlong = get_pci(PCI_rom_base, 4); - //fixme?: if (!tmpUlong) try to map the ROM ourselves. Confirmed a PCIe system not - //having the ROM mapped on PCI and PCIe cards. Falling back to fetching from ISA - //legacy space will get us into trouble if we aren't the primary graphics card!! - //(as legacy space always has the primary card's ROM 'mapped'!) - if (tmpUlong) { - /* ROM was assigned an adress, so enable ROM decoding - see PCI standard */ - tmpUlong |= 0x00000001; - set_pci(PCI_rom_base, 4, tmpUlong); - - rom_area = map_physical_memory( - buffer, - di->pcii.u.h0.rom_base_pci, - di->pcii.u.h0.rom_size, - B_ANY_KERNEL_ADDRESS, - B_READ_AREA, - (void **)&(rom_temp) - ); - - /* check if we got the BIOS and signature (might fail on laptops..) */ - if (rom_area >= 0) { - if ((rom_temp[0] != 0x55) || (rom_temp[1] != 0xaa)) { - /* apparantly no ROM is mapped here */ - delete_area(rom_area); - rom_area = -1; - /* force using ISA legacy map as fall-back */ - tmpUlong = 0x00000000; - } - } else { - /* mapping failed: force using ISA legacy map as fall-back */ - tmpUlong = 0x00000000; - } - } - - if (!tmpUlong) { - /* ROM was not assigned an adress, fetch it from ISA legacy memory map! */ - rom_area = map_physical_memory(buffer, 0x000c0000, - 65536, B_ANY_KERNEL_ADDRESS, B_READ_AREA, (void **)&(rom_temp)); - } - - /* if mapping ROM to vmem failed then clean up and pass on error */ - if (rom_area < 0) { - delete_area(si->regs_area); - si->regs_area = -1; - return rom_area; - } - - /* dump ROM to file if selected in nvidia.settings - * (ROM always fits in 64Kb: checked TNT1 - FX5950) */ - if (sSettings.dumprom) - dumprom(rom_temp, 65536, di->pcii); - - /* make a copy of ROM for future reference */ - memcpy(si->rom_mirror, rom_temp, 65536); - - /* disable ROM decoding - this is defined in the PCI standard, and delete the area */ - tmpUlong = get_pci(PCI_rom_base, 4); - tmpUlong &= 0xfffffffe; - set_pci(PCI_rom_base, 4, tmpUlong); - delete_area(rom_area); - - /* restore original ROM shadowing setting to prevent trouble starting (some) cards */ - set_pci(NVCFG_ROMSHADOW, 4, tmpROMshadow); - - /* work out a name for the framebuffer mapping*/ - sprintf(buffer, DEVICE_FORMAT " framebuffer", - di->pcii.vendor_id, di->pcii.device_id, - di->pcii.bus, di->pcii.device, di->pcii.function); - - /* map the framebuffer into vmem, using Write Combining*/ - si->fb_area = map_physical_memory(buffer, - /* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */ - di->pcii.u.h0.base_registers_pci[frame_buffer], - di->pcii.u.h0.base_register_sizes[frame_buffer], - B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, - B_READ_AREA | B_WRITE_AREA, - &(si->framebuffer)); - - /*if failed with write combining try again without*/ - if (si->fb_area < 0) { - si->fb_area = map_physical_memory(buffer, - /* WARNING: Nvidia needs to map framebuffer as viewed from PCI space! */ - di->pcii.u.h0.base_registers_pci[frame_buffer], - di->pcii.u.h0.base_register_sizes[frame_buffer], - B_ANY_KERNEL_BLOCK_ADDRESS, - B_READ_AREA | B_WRITE_AREA, - &(si->framebuffer)); - } - - /* if there was an error, delete our other areas and pass on error*/ - if (si->fb_area < 0) { - delete_area(si->regs_area); - si->regs_area = -1; - return si->fb_area; - } - - //fixme: retest for card coldstart and PCI/virt_mem mapping!! - /* remember the DMA address of the frame buffer for BDirectWindow?? purposes */ - si->framebuffer_pci = (void *) di->pcii.u.h0.base_registers_pci[frame_buffer]; - - // remember settings for use here and in accelerant - si->settings = sSettings; - - /* in any case, return the result */ - return si->fb_area; -} - - -static void -unmap_device(device_info *di) -{ - shared_info *si = di->si; - uint32 tmpUlong; - pci_info *pcii = &(di->pcii); - - /* disable memory mapped IO */ - tmpUlong = get_pci(PCI_command, 4); - tmpUlong &= 0xfffffffc; - set_pci(PCI_command, 4, tmpUlong); - /* delete the areas */ - if (si->regs_area >= 0) - delete_area(si->regs_area); - if (si->fb_area >= 0) - delete_area(si->fb_area); - si->regs_area = si->fb_area = -1; - si->framebuffer = NULL; - di->regs = NULL; -} - - -static void -probe_devices(void) -{ - uint32 pci_index = 0; - uint32 count = 0; - device_info *di = pd->di; - char tmp_name[B_OS_NAME_LENGTH]; - - /* while there are more pci devices */ - while (count < MAX_DEVICES - && (*pci_bus->get_nth_pci_info)(pci_index, &(di->pcii)) == B_OK) { - int vendor = 0; - - /* if we match a supported vendor */ - while (SupportedDevices[vendor].vendor) { - if (SupportedDevices[vendor].vendor == di->pcii.vendor_id) { - uint16 *devices = SupportedDevices[vendor].devices; - /* while there are more supported devices */ - while (*devices) { - /* if we match a supported device */ - if (*devices == di->pcii.device_id ) { - /* publish the device name */ - sprintf(tmp_name, DEVICE_FORMAT, - di->pcii.vendor_id, di->pcii.device_id, - di->pcii.bus, di->pcii.device, di->pcii.function); - /* tweak the exported name to show first in the alphabetically ordered /dev/ - * hierarchy folder, so the system will use it as primary adaptor if requested - * via nvidia.settings. */ - if (strcmp(tmp_name, sSettings.primary) == 0) - sprintf(tmp_name, "-%s", sSettings.primary); - /* add /dev/ hierarchy path */ - sprintf(di->name, "graphics/%s", tmp_name); - /* remember the name */ - pd->device_names[count] = di->name; - /* mark the driver as available for R/W open */ - di->is_open = 0; - /* mark areas as not yet created */ - di->shared_area = -1; - /* mark pointer to shared data as invalid */ - di->si = NULL; - /* inc pointer to device info */ - di++; - /* inc count */ - count++; - /* break out of these while loops */ - goto next_device; - } - /* next supported device */ - devices++; - } - } - vendor++; - } -next_device: - /* next pci_info struct, please */ - pci_index++; - } - /* propagate count */ - pd->count = count; - /* terminate list of device names with a null pointer */ - pd->device_names[pd->count] = NULL; -} - - -static uint32 -thread_interrupt_work(int32 *flags, vuint32 *regs, shared_info *si) -{ - uint32 handled = B_HANDLED_INTERRUPT; - /* release the vblank semaphore */ - if (si->vblank >= 0) { - int32 blocked; - if ((get_sem_count(si->vblank, &blocked) == B_OK) && (blocked < 0)) { - release_sem_etc(si->vblank, -blocked, B_DO_NOT_RESCHEDULE); - handled = B_INVOKE_SCHEDULER; - } - } - return handled; -} - - -static int32 -nv_interrupt(void *data) -{ - int32 handled = B_UNHANDLED_INTERRUPT; - device_info *di = (device_info *)data; - shared_info *si = di->si; - int32 *flags = &(si->flags); - vuint32 *regs; - - /* is someone already handling an interrupt for this device? */ - if (atomic_or(flags, SKD_HANDLER_INSTALLED) & SKD_HANDLER_INSTALLED) goto exit0; - - /* get regs */ - regs = di->regs; - - /* was it a VBI? */ - /* note: si->ps.secondary_head was cleared by kerneldriver earlier! (at least) */ - if (si->ps.secondary_head) { - //fixme: - //rewrite once we use one driver instance 'per head' (instead of 'per card') - if (caused_vbi_crtc1(regs) || caused_vbi_crtc2(regs)) { - /* clear the interrupt(s) */ - clear_vbi_crtc1(regs); - clear_vbi_crtc2(regs); - /* release the semaphore */ - handled = thread_interrupt_work(flags, regs, si); - } - } else { - if (caused_vbi_crtc1(regs)) { - /* clear the interrupt */ - clear_vbi_crtc1(regs); - /* release the semaphore */ - handled = thread_interrupt_work(flags, regs, si); - } - } - - /* note that we're not in the handler any more */ - atomic_and(flags, ~SKD_HANDLER_INSTALLED); - -exit0: - return handled; -} - - -// #pragma mark - device hooks - - -static status_t -open_hook(const char* name, uint32 flags, void** cookie) -{ - int32 index = 0; - device_info *di; - shared_info *si; - thread_id thid; - thread_info thinfo; - status_t result = B_OK; - char shared_name[B_OS_NAME_LENGTH]; - physical_entry map[1]; - size_t net_buf_size; - void *unaligned_dma_buffer; - - /* find the device name in the list of devices */ - /* we're never passed a name we didn't publish */ - while (pd->device_names[index] - && (strcmp(name, pd->device_names[index]) != 0)) - index++; - - /* for convienience */ - di = &(pd->di[index]); - - /* make sure no one else has write access to the common data */ - AQUIRE_BEN(pd->kernel); - - /* if it's already open for writing */ - if (di->is_open) { - /* mark it open another time */ - goto mark_as_open; - } - /* create the shared_info area */ - sprintf(shared_name, DEVICE_FORMAT " shared", - di->pcii.vendor_id, di->pcii.device_id, - di->pcii.bus, di->pcii.device, di->pcii.function); - /* create this area with NO user-space read or write permissions, to prevent accidental damage */ - di->shared_area = create_area(shared_name, (void **)&(di->si), B_ANY_KERNEL_ADDRESS, - ((sizeof(shared_info) + (B_PAGE_SIZE - 1)) & ~(B_PAGE_SIZE - 1)), B_FULL_LOCK, - B_USER_CLONEABLE_AREA); - if (di->shared_area < 0) { - /* return the error */ - result = di->shared_area; - goto done; - } - - /* save a few dereferences */ - si = di->si; - - /* create the DMA command buffer area */ - //fixme? for R4.5 a workaround for cloning would be needed! - /* we want to setup a 1Mb buffer (size must be multiple of B_PAGE_SIZE) */ - net_buf_size = ((1 * 1024 * 1024) + (B_PAGE_SIZE-1)) & ~(B_PAGE_SIZE-1); - /* create the area that will hold the DMA command buffer */ - si->unaligned_dma_area = - create_area("NV DMA cmd buffer", - (void **)&unaligned_dma_buffer, - B_ANY_KERNEL_ADDRESS, - 2 * net_buf_size, /* take twice the net size so we can have MTRR-WC even on old systems */ - B_32_BIT_CONTIGUOUS, /* GPU always needs access */ - B_USER_CLONEABLE_AREA | B_READ_AREA | B_WRITE_AREA); - // TODO: Physical aligning can be done without waste using the - // private create_area_etc(). - /* on error, abort */ - if (si->unaligned_dma_area < 0) - { - /* free the already created shared_info area, and return the error */ - result = si->unaligned_dma_area; - goto free_shared; - } - /* we (also) need the physical adress our DMA buffer is at, as this needs to be - * fed into the GPU's engine later on. Get an aligned adress so we can use MTRR-WC - * even on older CPU's. */ - get_memory_map(unaligned_dma_buffer, B_PAGE_SIZE, map, 1); - si->dma_buffer_pci = (void*) - ((map[0].address + net_buf_size - 1) & ~(net_buf_size - 1)); - - /* map the net DMA command buffer into vmem, using Write Combining */ - si->dma_area = map_physical_memory( - "NV aligned DMA cmd buffer", (addr_t)si->dma_buffer_pci, net_buf_size, - B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, - B_READ_AREA | B_WRITE_AREA, &(si->dma_buffer)); - /* if failed with write combining try again without */ - if (si->dma_area < 0) { - si->dma_area = map_physical_memory( - "NV aligned DMA cmd buffer", (addr_t)si->dma_buffer_pci, - net_buf_size, B_ANY_KERNEL_BLOCK_ADDRESS, - B_READ_AREA | B_WRITE_AREA, &(si->dma_buffer)); - } - /* if there was an error, delete our other areas and pass on error*/ - if (si->dma_area < 0) - { - /* free the already created areas, and return the error */ - result = si->dma_area; - goto free_shared_and_uadma; - } - - /* save the vendor and device IDs */ - si->vendor_id = di->pcii.vendor_id; - si->device_id = di->pcii.device_id; - si->revision = di->pcii.revision; - si->bus = di->pcii.bus; - si->device = di->pcii.device; - si->function = di->pcii.function; - - /* ensure that the accelerant's INIT_ACCELERANT function can be executed */ - si->accelerant_in_use = false; - /* preset singlehead card to prevent early INT routine calls (once installed) to - * wrongly identify the INT request coming from us! */ - si->ps.secondary_head = false; - - /* note the amount of system RAM the system BIOS assigned to the card if applicable: - * unified memory architecture (UMA) */ - switch ((((uint32)(si->device_id)) << 16) | si->vendor_id) - { - case 0x01a010de: /* Nvidia GeForce2 Integrated GPU */ - /* device at bus #0, device #0, function #1 holds value at byte-index 0x7C */ - si->ps.memory_size = 1024 * 1024 * - (((((*pci_bus->read_pci_config)(0, 0, 1, 0x7c, 4)) & 0x000007c0) >> 6) + 1); - /* last 64kB RAM is used for the BIOS (or something else?) */ - si->ps.memory_size -= (64 * 1024); - break; - case 0x01f010de: /* Nvidia GeForce4 MX Integrated GPU */ - /* device at bus #0, device #0, function #1 holds value at byte-index 0x84 */ - si->ps.memory_size = 1024 * 1024 * - (((((*pci_bus->read_pci_config)(0, 0, 1, 0x84, 4)) & 0x000007f0) >> 4) + 1); - /* last 64kB RAM is used for the BIOS (or something else?) */ - si->ps.memory_size -= (64 * 1024); - break; - default: - /* all other cards have own RAM: the amount of which is determined in the - * accelerant. */ - break; - } - - /* map the device */ - result = map_device(di); - if (result < 0) goto free_shared_and_alldma; - - /* we will be returning OK status for sure now */ - result = B_OK; - - /* disable and clear any pending interrupts */ - //fixme: - //distinquish between crtc1/crtc2 once all heads get seperate driver instances! - disable_vbi_all(di->regs); - - /* preset we can't use INT related functions */ - si->ps.int_assigned = false; - - /* create a semaphore for vertical blank management */ - si->vblank = create_sem(0, di->name); - if (si->vblank < 0) goto mark_as_open; - - /* change the owner of the semaphores to the opener's team */ - /* this is required because apps can't aquire kernel semaphores */ - thid = find_thread(NULL); - get_thread_info(thid, &thinfo); - set_sem_owner(si->vblank, thinfo.team); - - /* If there is a valid interrupt line assigned then set up interrupts */ - if ((di->pcii.u.h0.interrupt_pin == 0x00) || - (di->pcii.u.h0.interrupt_line == 0xff) || /* no IRQ assigned */ - (di->pcii.u.h0.interrupt_line <= 0x02)) /* system IRQ assigned */ - { - /* delete the semaphore as it won't be used */ - delete_sem(si->vblank); - si->vblank = -1; - } - else - { - /* otherwise install our interrupt handler */ - result = install_io_interrupt_handler(di->pcii.u.h0.interrupt_line, nv_interrupt, (void *)di, 0); - /* bail if we couldn't install the handler */ - if (result != B_OK) - { - /* delete the semaphore as it won't be used */ - delete_sem(si->vblank); - si->vblank = -1; - } - else - { - /* inform accelerant(s) we can use INT related functions */ - si->ps.int_assigned = true; - } - } - -mark_as_open: - /* mark the device open */ - di->is_open++; - - /* send the cookie to the opener */ - *cookie = di; - - goto done; - - -free_shared_and_alldma: - /* clean up our aligned DMA area */ - delete_area(si->dma_area); - si->dma_area = -1; - si->dma_buffer = NULL; - -free_shared_and_uadma: - /* clean up our unaligned DMA area */ - delete_area(si->unaligned_dma_area); - si->unaligned_dma_area = -1; - si->dma_buffer_pci = NULL; - -free_shared: - /* clean up our shared area */ - delete_area(di->shared_area); - di->shared_area = -1; - di->si = NULL; - -done: - /* end of critical section */ - RELEASE_BEN(pd->kernel); - - /* all done, return the status */ - return result; -} - - -static status_t -read_hook(void* dev, off_t pos, void* buf, size_t* len) -{ - *len = 0; - return B_NOT_ALLOWED; -} - - -static status_t -write_hook(void* dev, off_t pos, const void* buf, size_t* len) -{ - *len = 0; - return B_NOT_ALLOWED; -} - - -static status_t -close_hook(void* dev) -{ - /* we don't do anything on close: there might be dup'd fd */ - return B_NO_ERROR; -} - - -static status_t -free_hook(void* dev) -{ - device_info *di = (device_info *)dev; - shared_info *si = di->si; - vuint32 *regs = di->regs; - - /* lock the driver */ - AQUIRE_BEN(pd->kernel); - - /* if opened multiple times, decrement the open count and exit */ - if (di->is_open > 1) - goto unlock_and_exit; - - /* disable and clear any pending interrupts */ - //fixme: - //distinquish between crtc1/crtc2 once all heads get seperate driver instances! - disable_vbi_all(regs); - - if (si->ps.int_assigned) { - /* remove interrupt handler */ - remove_io_interrupt_handler(di->pcii.u.h0.interrupt_line, nv_interrupt, di); - - /* delete the semaphores, ignoring any errors ('cause the owning - team may have died on us) */ - delete_sem(si->vblank); - si->vblank = -1; - } - - /* free regs and framebuffer areas */ - unmap_device(di); - - /* clean up our aligned DMA area */ - delete_area(si->dma_area); - si->dma_area = -1; - si->dma_buffer = NULL; - - /* clean up our unaligned DMA area */ - delete_area(si->unaligned_dma_area); - si->unaligned_dma_area = -1; - si->dma_buffer_pci = NULL; - - /* clean up our shared area */ - delete_area(di->shared_area); - di->shared_area = -1; - di->si = NULL; - -unlock_and_exit: - /* mark the device available */ - di->is_open--; - /* unlock the driver */ - RELEASE_BEN(pd->kernel); - /* all done */ - return B_OK; -} - - -static status_t -control_hook(void* dev, uint32 msg, void *buf, size_t len) -{ - device_info *di = (device_info *)dev; - status_t result = B_DEV_INVALID_IOCTL; - uint32 tmpUlong; - - switch (msg) { - /* the only PUBLIC ioctl */ - case B_GET_ACCELERANT_SIGNATURE: - { - strcpy((char* )buf, sSettings.accelerant); - result = B_OK; - break; - } - - /* PRIVATE ioctl from here on */ - case NV_GET_PRIVATE_DATA: - { - nv_get_private_data *gpd = (nv_get_private_data *)buf; - if (gpd->magic == NV_PRIVATE_DATA_MAGIC) { - gpd->shared_info_area = di->shared_area; - result = B_OK; - } - break; - } - - case NV_GET_PCI: - { - nv_get_set_pci *gsp = (nv_get_set_pci *)buf; - if (gsp->magic == NV_PRIVATE_DATA_MAGIC) { - pci_info *pcii = &(di->pcii); - gsp->value = get_pci(gsp->offset, gsp->size); - result = B_OK; - } - break; - } - - case NV_SET_PCI: - { - nv_get_set_pci *gsp = (nv_get_set_pci *)buf; - if (gsp->magic == NV_PRIVATE_DATA_MAGIC) { - pci_info *pcii = &(di->pcii); - set_pci(gsp->offset, gsp->size, gsp->value); - result = B_OK; - } - break; - } - - case NV_DEVICE_NAME: - { - nv_device_name *dn = (nv_device_name *)buf; - if (dn->magic == NV_PRIVATE_DATA_MAGIC) { - strcpy(dn->name, di->name); - result = B_OK; - } - break; - } - - case NV_RUN_INTERRUPTS: - { - nv_set_vblank_int *vi = (nv_set_vblank_int *)buf; - if (vi->magic == NV_PRIVATE_DATA_MAGIC) { - vuint32 *regs = di->regs; - if (!(vi->crtc)) { - if (vi->do_it) { - enable_vbi_crtc1(regs); - } else { - disable_vbi_crtc1(regs); - } - } else { - if (vi->do_it) { - enable_vbi_crtc2(regs); - } else { - disable_vbi_crtc2(regs); - } - } - result = B_OK; - } - break; - } - - case NV_ISA_OUT: - { - nv_in_out_isa *io_isa = (nv_in_out_isa *)buf; - if (io_isa->magic == NV_PRIVATE_DATA_MAGIC) { - pci_info *pcii = &(di->pcii); - - /* lock the driver: - * no other graphics card may have ISA I/O enabled when we enter */ - AQUIRE_BEN(pd->kernel); - - /* enable ISA I/O access */ - tmpUlong = get_pci(PCI_command, 2); - tmpUlong |= PCI_command_io; - set_pci(PCI_command, 2, tmpUlong); - - if (io_isa->size == 1) - isa_bus->write_io_8(io_isa->adress, (uint8)io_isa->data); - else - isa_bus->write_io_16(io_isa->adress, io_isa->data); - result = B_OK; - - /* disable ISA I/O access */ - tmpUlong = get_pci(PCI_command, 2); - tmpUlong &= ~PCI_command_io; - set_pci(PCI_command, 2, tmpUlong); - - /* end of critical section */ - RELEASE_BEN(pd->kernel); - } - break; - } - - case NV_ISA_IN: - { - nv_in_out_isa *io_isa = (nv_in_out_isa *)buf; - if (io_isa->magic == NV_PRIVATE_DATA_MAGIC) { - pci_info *pcii = &(di->pcii); - - /* lock the driver: - * no other graphics card may have ISA I/O enabled when we enter */ - AQUIRE_BEN(pd->kernel); - - /* enable ISA I/O access */ - tmpUlong = get_pci(PCI_command, 2); - tmpUlong |= PCI_command_io; - set_pci(PCI_command, 2, tmpUlong); - - if (io_isa->size == 1) - io_isa->data = isa_bus->read_io_8(io_isa->adress); - else - io_isa->data = isa_bus->read_io_16(io_isa->adress); - result = B_OK; - - /* disable ISA I/O access */ - tmpUlong = get_pci(PCI_command, 2); - tmpUlong &= ~PCI_command_io; - set_pci(PCI_command, 2, tmpUlong); - - /* end of critical section */ - RELEASE_BEN(pd->kernel); - } - break; - } - } - - return result; -} - - -// #pragma mark - driver API - - -status_t -init_hardware(void) -{ - long index = 0; - pci_info pcii; - bool found = false; - - /* choke if we can't find the PCI bus */ - if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK) - return B_ERROR; - - /* choke if we can't find the ISA bus */ - if (get_module(B_ISA_MODULE_NAME, (module_info **)&isa_bus) != B_OK) - { - put_module(B_PCI_MODULE_NAME); - return B_ERROR; - } - - /* while there are more pci devices */ - while ((*pci_bus->get_nth_pci_info)(index, &pcii) == B_NO_ERROR) { - int vendor = 0; - - /* if we match a supported vendor */ - while (SupportedDevices[vendor].vendor) { - if (SupportedDevices[vendor].vendor == pcii.vendor_id) { - uint16 *devices = SupportedDevices[vendor].devices; - /* while there are more supported devices */ - while (*devices) { - /* if we match a supported device */ - if (*devices == pcii.device_id ) { - - found = true; - goto done; - } - /* next supported device */ - devices++; - } - } - vendor++; - } - /* next pci_info struct, please */ - index++; - } - -done: - /* put away the module manager */ - put_module(B_PCI_MODULE_NAME); - return found ? B_OK : B_ERROR; -} - - -status_t -init_driver(void) -{ - void *settings; - - // get driver/accelerant settings - settings = load_driver_settings(DRIVER_PREFIX ".settings"); - if (settings != NULL) { - const char *item; - char *end; - uint32 value; - - // for driver - item = get_driver_parameter(settings, "accelerant", "", ""); - if (item[0] && strlen(item) < sizeof(sSettings.accelerant) - 1) - strcpy (sSettings.accelerant, item); - - item = get_driver_parameter(settings, "primary", "", ""); - if (item[0] && strlen(item) < sizeof(sSettings.primary) - 1) - strcpy(sSettings.primary, item); - - sSettings.dumprom = get_driver_boolean_parameter(settings, - "dumprom", false, false); - - // for accelerant - item = get_driver_parameter(settings, "logmask", - "0x00000000", "0x00000000"); - value = strtoul(item, &end, 0); - if (*end == '\0') - sSettings.logmask = value; - - item = get_driver_parameter(settings, "memory", "0", "0"); - value = strtoul(item, &end, 0); - if (*end == '\0') - sSettings.memory = value; - - sSettings.hardcursor = get_driver_boolean_parameter(settings, - "hardcursor", false, false); - sSettings.usebios = get_driver_boolean_parameter(settings, - "usebios", false, false); - sSettings.switchhead = get_driver_boolean_parameter(settings, - "switchhead", false, false); - sSettings.pgm_panel = get_driver_boolean_parameter(settings, - "pgm_panel", false, false); - sSettings.force_sync = get_driver_boolean_parameter(settings, - "force_sync", false, false); - sSettings.force_ws = get_driver_boolean_parameter(settings, - "force_ws", false, false); - - item = get_driver_parameter(settings, "gpu_clk", "0", "0"); - value = strtoul(item, &end, 0); - if (*end == '\0') - sSettings.gpu_clk = value; - - item = get_driver_parameter(settings, "ram_clk", "0", "0"); - value = strtoul(item, &end, 0); - if (*end == '\0') - sSettings.ram_clk = value; - - unload_driver_settings(settings); - } - - /* get a handle for the pci bus */ - if (get_module(B_PCI_MODULE_NAME, (module_info **)&pci_bus) != B_OK) - return B_ERROR; - - /* get a handle for the isa bus */ - if (get_module(B_ISA_MODULE_NAME, (module_info **)&isa_bus) != B_OK) { - put_module(B_PCI_MODULE_NAME); - return B_ERROR; - } - - /* driver private data */ - pd = (DeviceData *)calloc(1, sizeof(DeviceData)); - if (!pd) { - put_module(B_PCI_MODULE_NAME); - return B_ERROR; - } - /* initialize the benaphore */ - INIT_BEN(pd->kernel); - /* find all of our supported devices */ - probe_devices(); - return B_OK; -} - - -const char ** -publish_devices(void) -{ - /* return the list of supported devices */ - return (const char **)pd->device_names; -} - - -device_hooks * -find_device(const char *name) -{ - int index = 0; - while (pd->device_names[index]) { - if (strcmp(name, pd->device_names[index]) == 0) - return &graphics_device_hooks; - index++; - } - return NULL; - -} - - -void -uninit_driver(void) -{ - /* free the driver data */ - DELETE_BEN(pd->kernel); - free(pd); - pd = NULL; - - /* put the pci module away */ - put_module(B_PCI_MODULE_NAME); - put_module(B_ISA_MODULE_NAME); -} - diff --git a/src/add-ons/kernel/drivers/graphics/nvidia_gpgpu/nvidia_gpgpu.settings b/src/add-ons/kernel/drivers/graphics/nvidia_gpgpu/nvidia_gpgpu.settings deleted file mode 100644 index 8090ee00ac..0000000000 --- a/src/add-ons/kernel/drivers/graphics/nvidia_gpgpu/nvidia_gpgpu.settings +++ /dev/null @@ -1,66 +0,0 @@ -# Settings file for the nvidia_gpgpu driver and accelerant -# -# This file should be moved to the directory -# ~/config/settings/kernel/drivers/ -# - -# nv.driver parameters: -#accelerant "nvidia_gpgpu.accelerant" # if enabled selects accelerant filename to be used -#primary "10de_0110_010000" # if enabled selects device to be used as primary device ('hack') -dumprom false # dump bios rom to file (in home folder) - -# nvidia_gpgpu.accelerant parameters: -usebios true # if true rely on bios to coldstart the card -#memory 2 # in MB, override builtin memory size detection -hardcursor true # if true use on-chip cursor capabilities -#logmask 0x00000000 # nothing logged, is default -#logmask 0x08000604 # log overlay use in full to file (in home folder) -#logmask 0xffffffff # log everything to file (in home folder) -switchhead false # switch head assignment (dualhead cards only) -force_sync false # if true forces 3D rendering to be synchronized to the vertical retrace -force_ws true # if true forces widescreen type detection for all connected screens - -# WARNING: tweak alert! modify stuff below on your own risk... -pgm_panel false # if false don't program DVI and laptop panel pixelclocks (refreshrates) -#gpu_clk 150 # in Mhz, (tries to) override default GPU clockspeed (be carefull!!!) -#ram_clk 150 # in Mhz, (tries to) override default cardRAM clockspeed (be carefull!!!) - -#--------- that's all. - - -#logmask setup info: -#log level select: -#logmask 0x0000000x # lowest digit: bitmask to select logging level. - -#log modules select: -#logmask 0xxxxxxxx0 # highest 7 digits: bitmask to select individual modules to log. - -#log levels: (3D add-on adheres to this setup, 2D add-on still has to tuned) -#logmask 0x00000001 # log rendering -#logmask 0x00000002 # log state -#logmask 0x00000004 # log experimental -#logmask 0x00000008 # log errors - -#log modules: -#logmask 0x00000200 # engine: bes -#logmask 0x00000400 # overlay -#logmask 0x00000800 # engine: support -#logmask 0x00001000 # engine: dac2 -#logmask 0x00002000 # engine: info -#logmask 0x00004000 # engine: i2c -#logmask 0x00008000 # engine: general -#logmask 0x00010000 # engine: dac1 -#logmask 0x00020000 # engine: crtc2 -#logmask 0x00040000 # engine: crtc1 -#logmask 0x00080000 # engine: acc (both PIO and DMA) -#logmask 0x00200000 # set displaymode -#logmask 0x00400000 # propose displaymode -#logmask 0x00800000 # init accelerant -#logmask 0x01000000 # get timing constraints -#logmask 0x02000000 # get mode info -#logmask 0x04000000 # get device info -#logmask 0x08000000 # get accelerant hook -#logmask 0x10000000 # engine management -#logmask 0x20000000 # cursor -#logmask 0x40000000 # 2D acceleration -#logmask 0x80000000 # 3D acceleration