From 9f6aebed5fc8cc92170e6abae98819f3274fadbb Mon Sep 17 00:00:00 2001 From: Rudolf Cornelissen Date: Tue, 31 Jan 2006 10:32:15 +0000 Subject: [PATCH] updated SCALED_BLIT to do 15-bit space correctly. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@16168 a95241bf-73f2-0310-859d-f6bbb57e9c96 --- .../accelerants/nvidia/engine/nv_acc_dma.c | 27 +++++++++++++++++-- 1 file changed, 25 insertions(+), 2 deletions(-) diff --git a/src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c b/src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c index 139aa71acc..ad393ae2fd 100644 --- a/src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c +++ b/src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c @@ -1,7 +1,7 @@ /* NV Acceleration functions */ /* Author: - Rudolf Cornelissen 8/2003-12/2005. + Rudolf Cornelissen 8/2003-1/2006. This code was possible thanks to: - the Linux XFree86 NV driver, @@ -1792,7 +1792,6 @@ void SCREEN_TO_SCREEN_BLIT_DMA(engine_token *et, blit_params *list, uint32 count /* scaled and filtered screen to screen blit - i.e. video playback without overlay */ /* note: source and destination may not overlap. */ //fixme? checkout NV5 and NV10 version of cmd: faster?? (or is 0x77 a 'autoselect' version?) -//fixme: test 15-bit depth for correct space (conversion)... void SCREEN_TO_SCREEN_SCALED_FILTERED_BLIT_DMA(engine_token *et, scaled_blit_params *list, uint32 count) { uint32 i = 0; @@ -1835,6 +1834,16 @@ void SCREEN_TO_SCREEN_SCALED_FILTERED_BLIT_DMA(engine_token *et, scaled_blit_par return; } + /* modify surface depth settings for 15-bit colorspace so command works as intended */ + if (si->dm.space == B_RGB15_LITTLE) + { + /* wait for room in fifo for surface setup cmd if needed */ + if (nv_acc_fifofree_dma(2) != B_OK) return; + /* now setup 2D surface (writing 1 32bit word) */ + nv_acc_cmd_dma(NV4_SURFACE, NV4_SURFACE_FORMAT, 1); + ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0x00000002; /* Format */ + } + /* TNT1 has fixed operation mode 'SRCcopy' while the rest can be programmed: */ if (si->ps.card_type != NV04) { @@ -1923,6 +1932,20 @@ void SCREEN_TO_SCREEN_SCALED_FILTERED_BLIT_DMA(engine_token *et, scaled_blit_par nv_start_dma(); } + /* reset surface depth settings so the other engine commands works as intended */ + if (si->dm.space == B_RGB15_LITTLE) + { + /* wait for room in fifo for surface setup cmd if needed */ + if (nv_acc_fifofree_dma(2) != B_OK) return; + /* now setup 2D surface (writing 1 32bit word) */ + nv_acc_cmd_dma(NV4_SURFACE, NV4_SURFACE_FORMAT, 1); + ((uint32*)(si->dma_buffer))[si->engine.dma.current++] = 0x00000004; /* Format */ + + /* tell the engine to fetch the commands in the DMA buffer that where not + * executed before. */ + nv_start_dma(); + } + /* tell 3D add-ons that they should reload their rendering states and surfaces */ si->engine.threeD.reload = 0xffffffff; }