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openBeOS_Matrox_V0.13beta2_src

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git-svn-id: file:///srv/svn/repos/haiku/trunk/current@5539 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
shatty
2003-12-02 22:04:10 +00:00
parent 7669b69fd4
commit a0d81e7674
2 changed files with 21 additions and 18 deletions
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headers/private/graphics/matrox/DriverInterface.h
+8 -16
View File
@@ -169,28 +169,14 @@ typedef struct {
}; };
struct struct
{ {
/*specialised registers for initialisation*/ /* specialised registers for card initialisation read from MGA BIOS (pins) */
//will be deleted, will be replaced by new Pins implementation:
//these are nolonger used by G100.
uint32 mem_ctl;
uint32 mem_type;
uint8 membuf; /*memory buffer type*/
uint32 mem_rd;
uint32 mem_rfhcnt;
/*temporary extra info for G450*/
//will be deleted, will be replaced by new Pins implementation:
uint32 option;
uint32 option2;
uint32 option4;
uint32 maccess;
/* general card information */ /* general card information */
uint32 card_type; /* see card_type enum above */ uint32 card_type; /* see card_type enum above */
status_t pins_status; /* B_OK if read correctly, B_ERROR if faked */ status_t pins_status; /* B_OK if read correctly, B_ERROR if faked */
bool sdram; /* TRUE if SDRAM card: needed info for 2D acceleration */ bool sdram; /* TRUE if SDRAM card: needed info for 2D acceleration */
/* newly implemented PINS: will replace most of the above.. */ /* PINS */
float f_ref; /* PLL reference-oscillator frequency (Mhz) */ float f_ref; /* PLL reference-oscillator frequency (Mhz) */
uint32 max_system_vco; /* graphics engine PLL VCO limits (Mhz) */ uint32 max_system_vco; /* graphics engine PLL VCO limits (Mhz) */
uint32 min_system_vco; uint32 min_system_vco;
@@ -218,9 +204,15 @@ typedef struct {
bool secondary_dvi; bool secondary_dvi;
uint32 memory_size; /* memory (Mb) */ uint32 memory_size; /* memory (Mb) */
uint32 mctlwtst_reg; /* memory control waitstate register */ uint32 mctlwtst_reg; /* memory control waitstate register */
uint32 memrdbk_reg; /* memory readback register */
uint32 option_reg; /* option register */ uint32 option_reg; /* option register */
uint32 option2_reg; /* option2 register */
uint32 option3_reg; /* option3 register */
uint32 option4_reg; /* option4 register */
uint8 v3_option2_reg; /* pins v3 option2 register, not used for G100 */
uint8 v3_clk_div; /* pins v3 memory and system clock division factors */ uint8 v3_clk_div; /* pins v3 memory and system clock division factors */
uint8 v3_mem_type; /* pins v3 memory type info */ uint8 v3_mem_type; /* pins v3 memory type info */
uint16 v5_mem_type; /* pins v5 memory type info */
} ps; } ps;
/*mirror of the ROM (copied in driver, because may not be mapped permanently - only over fb)*/ /*mirror of the ROM (copied in driver, because may not be mapped permanently - only over fb)*/
headers/private/graphics/matrox/mga_macros.h
+13 -2
View File
@@ -20,7 +20,7 @@
#define MGACFG_SUBSYSIDW 0x4c // >= MYST #define MGACFG_SUBSYSIDW 0x4c // >= MYST
#define MGACFG_OPTION2 0x50 // >= G100 #define MGACFG_OPTION2 0x50 // >= G100
#define MGACFG_OPTION3 0x54 // >= G400 #define MGACFG_OPTION3 0x54 // >= G400
#define MGACFG_OPTION4 0x58 // >= G400 #define MGACFG_OPTION4 0x58 // >= G450
#define MGACFG_PM_IDENT 0xdc // >= G100 #define MGACFG_PM_IDENT 0xdc // >= G100
#define MGACFG_PM_CSR 0xe0 // >= G100 #define MGACFG_PM_CSR 0xe0 // >= G100
#define MGACFG_AGP_IDENT 0xf0 // >= MIL2 #define MGACFG_AGP_IDENT 0xf0 // >= MIL2
@@ -101,7 +101,6 @@
#define MGADXI_PIXPLLSTAT 0x4F #define MGADXI_PIXPLLSTAT 0x4F
#define MGADXI_CURCOLEXT 0x60 /*sequential from CURCOL3->15, RGB*/ #define MGADXI_CURCOLEXT 0x60 /*sequential from CURCOL3->15, RGB*/
//rudolf: missing registers!
/*(D)AC (X) (I)ndexed registers (>= g200) */ /*(D)AC (X) (I)ndexed registers (>= g200) */
#define MGADXI_KEYOPMODE 0x51 #define MGADXI_KEYOPMODE 0x51
#define MGADXI_COLMSK0RED 0x52 #define MGADXI_COLMSK0RED 0x52
@@ -111,6 +110,18 @@
#define MGADXI_COLKEY0GREEN 0x56 #define MGADXI_COLKEY0GREEN 0x56
#define MGADXI_COLKEY0BLUE 0x57 #define MGADXI_COLKEY0BLUE 0x57
/*(D)AC (X) (I)ndexed registers (>= g450?) */
#define MGADXI_TVO_IDX 0x87
#define MGADXI_TVO_DATA 0x88
#define MGADXI_OUTPUTCONN 0x8A
#define MGADXI_SYNCCTRL 0x8B
#define MGADXI_VIDPLLSTAT 0x8C
#define MGADXI_VIDPLLP 0x8D
#define MGADXI_VIDPLLM 0x8E
#define MGADXI_VIDPLLN 0x8F
#define MGADXI_PWRCTRL 0xA0
#define MGADXI_PANMODE 0xA2
/*MGA 1st CRTC registers */ /*MGA 1st CRTC registers */
#define MGACR1_VCOUNT 0x1E20 #define MGACR1_VCOUNT 0x1E20
//end rudolf. //end rudolf.