From a604c049651dd618e7fefad86deb63e2ea83ee42 Mon Sep 17 00:00:00 2001 From: Alexander von Gluck IV Date: Mon, 13 Jun 2011 14:46:52 +0000 Subject: [PATCH] * Small style fix to Calibration diff var and PLLCRTCGrab stored var * Repair incorrect DCCG operation at end of PLLSet git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42149 a95241bf-73f2-0310-859d-f6bbb57e9c96 --- src/add-ons/accelerants/radeon_hd/pll.cpp | 14 ++++++-------- 1 file changed, 6 insertions(+), 8 deletions(-) diff --git a/src/add-ons/accelerants/radeon_hd/pll.cpp b/src/add-ons/accelerants/radeon_hd/pll.cpp index 85cdc67a30..0d52a9da14 100644 --- a/src/add-ons/accelerants/radeon_hd/pll.cpp +++ b/src/add-ons/accelerants/radeon_hd/pll.cpp @@ -89,8 +89,6 @@ PLLCalculate(uint32 pixelClock, uint16 *reference, uint16 *feedback, for (referenceDiv = 1; referenceDiv <= REF_DIV_LIMIT; referenceDiv++) { - uint32 diff; - feedbackDiv = (uint32)((ratio * postDiv * referenceDiv) + 0.5); if (feedbackDiv >= FB_DIV_LIMIT) @@ -98,7 +96,7 @@ PLLCalculate(uint32 pixelClock, uint16 *reference, uint16 *feedback, if (feedbackDiv > (500 + (13 * referenceDiv))) // rv6x0 limit break; - diff = abs(pixelClock - (feedbackDiv + uint32 diff = abs(pixelClock - (feedbackDiv * gInfo->shared_info->pll_info.reference_frequency) / (postDiv * referenceDiv)); @@ -323,7 +321,7 @@ PLLSet(uint8 pllIndex, uint32 pixelClock) PLLCRTCGrab(pllIndex, false); if (hasDccg) - DCCGCLKSet(pllIndex, RV620_DCCGCLK_RELEASE); + DCCGCLKSet(pllIndex, RV620_DCCGCLK_GRAB); TRACE("%s: PLLSet exit\n", __func__); return B_OK; @@ -365,8 +363,6 @@ PLLCalibrate(uint8 pllIndex) void PLLCRTCGrab(uint8 pllIndex, bool crt2) { - - uint32 stored; bool pll2IsCurrent; if (!crt2) { @@ -384,7 +380,7 @@ PLLCRTCGrab(uint8 pllIndex, bool crt2) /* if the current pll is not active, then poke it just enough to flip * owners */ if (!pll2IsCurrent) { - stored = read32PLL(P1PLL_CNTL); + uint32 stored = read32PLL(P1PLL_CNTL); if (stored & 0x03) { write32PLLAtMask(P1PLL_CNTL, 0, 0x03); @@ -393,7 +389,7 @@ PLLCRTCGrab(uint8 pllIndex, bool crt2) } } else { - stored = read32PLL(P2PLL_CNTL); + uint32 stored = read32PLL(P2PLL_CNTL); if (stored & 0x03) { write32PLLAtMask(P2PLL_CNTL, 0, 0x03); @@ -404,6 +400,8 @@ PLLCRTCGrab(uint8 pllIndex, bool crt2) } +// See if card has a DCCG available that we need to lock to +// the PLL clock. No one seems really sure what DCCG is. bool DCCGCLKAvailable(uint8 pllIndex) {