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intel_extreme: IronLake reference clock activation

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This commit is contained in:
Alexander von Gluck IV
2016-07-17 15:25:08 -05:00
parent 00a3a794e0
commit a933bb4cbc
4 changed files with 130 additions and 1 deletions
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headers/private/graphics/intel_extreme/intel_extreme.h
+24
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@@ -711,6 +711,30 @@ struct intel_free_graphics_memory {
#define INTEL_DISPLAY_B_PLL (0x6018 | REGS_SOUTH_SHARED)
#define CHV_DISPLAY_C_PLL (0x6030 | REGS_SOUTH_SHARED)
// Ironlake PCH reference clk control
#define PCH_DREF_CONTROL (0x6200 | REGS_SOUTH_SHARED)
#define DREF_CONTROL_MASK 0x7fc3
#define DREF_CPU_SOURCE_OUTPUT_DISABLE (0 << 13)
#define DREF_CPU_SOURCE_OUTPUT_DOWNSPREAD (2 << 13)
#define DREF_CPU_SOURCE_OUTPUT_NONSPREAD (3 << 13)
#define DREF_CPU_SOURCE_OUTPUT_MASK (3 << 13)
#define DREF_SSC_SOURCE_DISABLE (0 << 11)
#define DREF_SSC_SOURCE_ENABLE (2 << 11)
#define DREF_SSC_SOURCE_MASK (3 << 11)
#define DREF_NONSPREAD_SOURCE_DISABLE (0 << 9)
#define DREF_NONSPREAD_CK505_ENABLE (1 << 9)
#define DREF_NONSPREAD_SOURCE_ENABLE (2 << 9)
#define DREF_NONSPREAD_SOURCE_MASK (3 << 9)
#define DREF_SUPERSPREAD_SOURCE_DISABLE (0 << 7)
#define DREF_SUPERSPREAD_SOURCE_ENABLE (2 << 7)
#define DREF_SUPERSPREAD_SOURCE_MASK (3 << 7)
#define DREF_SSC4_DOWNSPREAD (0 << 6)
#define DREF_SSC4_CENTERSPREAD (1 << 6)
#define DREF_SSC1_DISABLE (0 << 1)
#define DREF_SSC1_ENABLE (1 << 1)
#define DREF_SSC4_DISABLE (0 << 0)
#define DREF_SSC4_ENABLE (1 << 0)
// Multiplier Divisor
#define INTEL_DISPLAY_A_PLL_MD (0x601C | REGS_SOUTH_SHARED)
#define INTEL_DISPLAY_B_PLL_MD (0x6020 | REGS_SOUTH_SHARED)