From ab26d7f83768b1a9c8adc54fe9ac73d66c4b7e76 Mon Sep 17 00:00:00 2001 From: Rudolf Cornelissen Date: Mon, 24 Jan 2005 20:11:59 +0000 Subject: [PATCH] finalized DMA buffer overfill checking for optimum speed. On NV11 accelerated functions are running at 130% to 200% speed in DMA mode compared to the 'old' PIO mode. Without trouble now. Still only 32bit mode, and still missing invert_rect function though. Also still not explicitly adhering the engine constraints which needs to be rechecked/retuned compared to PIO mode (hence the non working 800x600x8 mode I expect..) git-svn-id: file:///srv/svn/repos/haiku/trunk/current@11009 a95241bf-73f2-0310-859d-f6bbb57e9c96 --- src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c | 12 ++++++++---- 1 file changed, 8 insertions(+), 4 deletions(-) diff --git a/src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c b/src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c index cb4c185d81..4e6aa2e866 100644 --- a/src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c +++ b/src/add-ons/accelerants/nvidia/engine/nv_acc_dma.c @@ -825,11 +825,15 @@ static status_t nv_acc_fifofree_dma(uint16 cmd_size) while ((si->engine.dma.free < cmd_size) && (cnt < 10000) && (err < 3)) { /* see where the engine is currently fetching from the buffer */ + /* note: + * read this only once in the code as accessing registers is relatively slow */ dmaget = ((NV_REG32(NVACC_FIFO + NV_GENERAL_DMAGET + si->engine.fifo.handle[(si->engine.fifo.ch_ptr[NV_ROP5_SOLID])])) >> 2); - /* snooze a bit so I do not hammer the bus */ - snooze (100); + /* update timeout counter: on NV11 on a Pentium4 2.8Ghz max reached count + * using BeRoMeter 1.2.6 was about 600; so counting 10000 before generating + * a timeout should definately do it. Snooze()-ing cannot be done without a + * serious speed penalty, even if done for only 1 microSecond. */ cnt++; /* where's the engine fetching viewed from us issuing? */ @@ -857,7 +861,7 @@ static status_t nv_acc_fifofree_dma(uint16 cmd_size) /* note the updated current free space we have in the DMA buffer */ si->engine.dma.free = dmaget - si->engine.dma.current; - /* mind this pittfall: + /* mind this pittfall (? there might be another reason): * as the engine is DMA triggered for fetching chunks every 128 bytes, * we may not touch that much at the end of our free space! * (confirmed NV11 when it's buffer is full for a longer period of @@ -875,7 +879,7 @@ static status_t nv_acc_fifofree_dma(uint16 cmd_size) /* note the updated current free space we have in the DMA buffer */ si->engine.dma.free = dmaget - si->engine.dma.current; - /* mind this pittfall: + /* mind this pittfall (? there might be another reason): * as the engine is DMA triggered for fetching chunks every 128 bytes, * we may not touch that much at the end of our free space! * (confirmed NV11 when it's buffer is full for a longer period of