diff --git a/headers/private/kernel/arch/arm/arm_mmu.h b/headers/private/kernel/arch/arm/arm_mmu.h
index 9388c4ac98..730ebac43f 100644
--- a/headers/private/kernel/arch/arm/arm_mmu.h
+++ b/headers/private/kernel/arch/arm/arm_mmu.h
@@ -43,26 +43,26 @@
 // found it in the cortex A8 reference... so I set t to 0
 // page table must obviously be on multiple of 1KB
 
-/*
- * L2-Page descriptors... now things get really complicated...
- * there are three different types of pages large pages (64KB) and small(4KB)
- * and "small extended".
- * only small extende is used by now....
- * and there is a new and a old format of page table entries
- * I will use the old format...
- */
-
 #define ARM_MMU_L2_TYPE_LARGE			0x1
+#define ARM_MMU_L2_TYPE_SMALLNEW		0x2
 #define ARM_MMU_L2_TYPE_SMALLEXT		0x3
 
-/* for new format entries (cortex-a8) */
-#define ARM_MMU_L2_TYPE_SMALLNEW		0x2
+#define ARM_MMU_L2_FLAG_XN				0x001
+#define ARM_MMU_L2_FLAG_B				0x004
+#define ARM_MMU_L2_FLAG_C				0x008
+#define ARM_MMU_L2_FLAG_AP0				0x010
+#define ARM_MMU_L2_FLAG_AP1				0x020
+#define ARM_MMU_L2_FLAG_TEX0			0x040
+#define ARM_MMU_L2_FLAG_TEX1			0x080
+#define ARM_MMU_L2_FLAG_TEX2			0x100
+#define ARM_MMU_L2_FLAG_AP2				0x200
+#define ARM_MMU_L2_FLAG_S				0x400
+#define ARM_MMU_L2_FLAG_NG				0x800
 
-// for B C and TEX see ARM arm B4-11
-#define ARM_MMU_L2_FLAG_B				0x4
-#define ARM_MMU_L2_FLAG_C				0x8
-#define ARM_MMU_L2_FLAG_TEX				0	// use 0b000 as TEX
-#define ARM_MMU_L2_FLAG_AP_RW			0x30
+#define ARM_MMU_L2_FLAG_AP_KRW			0x010
+	// allow read and write for kernel only
+
+#define ARM_MMU_L2_FLAG_AP_RW			0x030
 	// allow read and write for user and system
 
 #define ARM_MMU_L1_TABLE_ENTRY_COUNT	4096
diff --git a/src/system/boot/platform/efi/arch/arm/arch_mmu.cpp b/src/system/boot/platform/efi/arch/arm/arch_mmu.cpp
index 430d583ce3..0ac59a4a3f 100644
--- a/src/system/boot/platform/efi/arch/arm/arch_mmu.cpp
+++ b/src/system/boot/platform/efi/arch/arm/arch_mmu.cpp
@@ -325,7 +325,7 @@ arch_mmu_generate_post_efi_page_tables(size_t memoryMapSize,
 			(efi_memory_descriptor *)(memoryMapAddr + i * descriptorSize);
 		if ((entry->Attribute & EFI_MEMORY_RUNTIME) != 0) {
 			map_range_to_new_area(entry,
-				ARM_MMU_L2_FLAG_B | ARM_MMU_L2_FLAG_C | ARM_MMU_L2_FLAG_AP_RW);
+				ARM_MMU_L2_FLAG_B | ARM_MMU_L2_FLAG_C | ARM_MMU_L2_FLAG_AP_KRW);
 		}
 	}
 
@@ -335,10 +335,11 @@ arch_mmu_generate_post_efi_page_tables(size_t memoryMapSize,
 	size_t size;
 	while (mmu_next_region(&cookie, &vaddr, &paddr, &size)) {
 		map_range(vaddr, paddr, size,
-			ARM_MMU_L2_FLAG_B | ARM_MMU_L2_FLAG_C | ARM_MMU_L2_FLAG_AP_RW);
+			ARM_MMU_L2_FLAG_B | ARM_MMU_L2_FLAG_C | ARM_MMU_L2_FLAG_AP_KRW);
 	}
 
-	map_range_to_new_area(gKernelArgs.arch_args.uart.regs, ARM_MMU_L2_FLAG_B);
+	map_range_to_new_area(gKernelArgs.arch_args.uart.regs,
+		ARM_MMU_L2_FLAG_B | ARM_MMU_L2_FLAG_AP_KRW | ARM_MMU_L2_FLAG_XN);
 
 	sort_address_ranges(gKernelArgs.virtual_allocated_range,
 		gKernelArgs.num_virtual_allocated_ranges);
diff --git a/src/system/boot/platform/efi/arch/arm/entry.S b/src/system/boot/platform/efi/arch/arm/entry.S
index 35e16d0f6d..10c5aff72d 100644
--- a/src/system/boot/platform/efi/arch/arm/entry.S
+++ b/src/system/boot/platform/efi/arch/arm/entry.S
@@ -83,11 +83,13 @@ _pl1_entry:
 	MCR p15, 0, r1, c8, c7, 0
 
 	// write DACR
-	mov r9, #0xffffffff
-	MCR p15, 0, r9, c3, c0, 0
+	mov		r9, #0x00000001
+	mcr		p15, 0, r9, c3, c0, 0
 
 	// enable MMU and caches
 	mrc		p15, 0, r9, c1, c0, 0
+	bic		r9, r9, #0x20000000		// access flag disabled
+	bic		r9, r9, #0x10000000		// TEX remap disabled
 	orr		r9, r9, #0x00001000		// i-cache enabled
 	orr		r9, r9, #0x00000004		// d-cache enabled
 	orr		r9, r9, #0x00000001		// MMU enabled
diff --git a/src/system/kernel/arch/arm/paging/32bit/ARMPagingMethod32Bit.cpp b/src/system/kernel/arch/arm/paging/32bit/ARMPagingMethod32Bit.cpp
index 45be441b27..3b288d2c43 100644
--- a/src/system/kernel/arch/arm/paging/32bit/ARMPagingMethod32Bit.cpp
+++ b/src/system/kernel/arch/arm/paging/32bit/ARMPagingMethod32Bit.cpp
@@ -182,7 +182,8 @@ ARMPagingMethod32Bit::PhysicalPageSlotPool::Map(phys_addr_t physicalAddress,
 		(virtualAddress - fVirtualBase) / B_PAGE_SIZE];
 	pte = (physicalAddress & ARM_PTE_ADDRESS_MASK)
 		| ARM_MMU_L2_TYPE_SMALLNEW
-		| ARM_MMU_L2_FLAG_B | ARM_MMU_L2_FLAG_C;
+		| ARM_MMU_L2_FLAG_B | ARM_MMU_L2_FLAG_C
+		| ARM_MMU_L2_FLAG_AP_KRW | ARM_MMU_L2_FLAG_XN;
 
 	arch_cpu_invalidate_TLB_range(virtualAddress, virtualAddress + B_PAGE_SIZE);
 //	invalidate_TLB(virtualAddress);
@@ -510,7 +511,8 @@ ARMPagingMethod32Bit::PutPageTableEntryInTable(page_table_entry* entry,
 {
 	page_table_entry page = (physicalAddress & ARM_PTE_ADDRESS_MASK)
 		| ARM_MMU_L2_TYPE_SMALLNEW
-		| ARM_MMU_L2_FLAG_B | ARM_MMU_L2_FLAG_C;
+		| ARM_MMU_L2_FLAG_B | ARM_MMU_L2_FLAG_C
+		| ARM_MMU_L2_FLAG_AP_RW;
 #if 0 //IRA
 		| X86_PTE_PRESENT | (globalPage ? X86_PTE_GLOBAL : 0)
 		| MemoryTypeToPageTableEntryFlags(memoryType);