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* improve framebuffer programming on newer cards

Browse Source 
* correct? color mode setting bug
* fix var naming to match style guidelines
* add a few missing register defines


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42879 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Alexander von Gluck IV
2011-10-18 05:54:28 +00:00
parent a4f66979fe
commit afbd52f16a
4 changed files with 81 additions and 31 deletions
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headers/private/graphics/radeon_hd/r800_reg.h
+3
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@@ -117,6 +117,8 @@
#define EVERGREEN_GRPH_Y_START 0x6830 #define EVERGREEN_GRPH_Y_START 0x6830
#define EVERGREEN_GRPH_X_END 0x6834 #define EVERGREEN_GRPH_X_END 0x6834
#define EVERGREEN_GRPH_Y_END 0x6838 #define EVERGREEN_GRPH_Y_END 0x6838
#define EVERGREEN_GRPH_FLIP_CONTROL 0x6848
# define EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN (1 << 0)
#define EVERGREEN_CUR_CONTROL 0x6998 #define EVERGREEN_CUR_CONTROL 0x6998
# define EVERGREEN_CURSOR_EN (1 << 0) # define EVERGREEN_CURSOR_EN (1 << 0)
# define EVERGREEN_CURSOR_MODE(x) (((x) & 0x3) << 8) # define EVERGREEN_CURSOR_MODE(x) (((x) & 0x3) << 8)
@@ -180,6 +182,7 @@
#define EVERGREEN_CRTC_CONTROL 0x6e70 #define EVERGREEN_CRTC_CONTROL 0x6e70
# define EVERGREEN_CRTC_MASTER_EN (1 << 0) # define EVERGREEN_CRTC_MASTER_EN (1 << 0)
#define EVERGREEN_CRTC_UPDATE_LOCK 0x6ed4 #define EVERGREEN_CRTC_UPDATE_LOCK 0x6ed4
#define EVERGREEN_MASTER_UPDATE_MODE 0x6ef8
#define EVERGREEN_DC_GPIO_HPD_MASK 0x64b0 #define EVERGREEN_DC_GPIO_HPD_MASK 0x64b0
#define EVERGREEN_DC_GPIO_HPD_A 0x64b4 #define EVERGREEN_DC_GPIO_HPD_A 0x64b4
#define EVERGREEN_DC_GPIO_HPD_EN 0x64b8 #define EVERGREEN_DC_GPIO_HPD_EN 0x64b8
src/add-ons/accelerants/radeon_hd/display.cpp
+76 -28
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@@ -846,13 +846,18 @@ display_crtc_scale(uint8 crtcID, display_mode *mode)
void void
display_crtc_fb_set_dce1(uint8 crtcID, display_mode *mode) display_crtc_fb_set(uint8 crtcID, display_mode *mode)
{ {
radeon_shared_info &info = *gInfo->shared_info; radeon_shared_info &info = *gInfo->shared_info;
register_info* regs = gDisplay[crtcID]->regs; register_info* regs = gDisplay[crtcID]->regs;
uint32 fb_swap = R600_D1GRPH_SWAP_ENDIAN_NONE; uint32 fbSwap;
uint32 fb_format; if (info.device_chipset >= RADEON_R1000)
fbSwap = EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_NONE);
else
fbSwap = R600_D1GRPH_SWAP_ENDIAN_NONE;
uint32 fbFormat;
uint32 bytesPerPixel; uint32 bytesPerPixel;
uint32 bitsPerPixel; uint32 bitsPerPixel;
@@ -861,34 +866,63 @@ display_crtc_fb_set_dce1(uint8 crtcID, display_mode *mode)
case B_CMAP8: case B_CMAP8:
bytesPerPixel = 1; bytesPerPixel = 1;
bitsPerPixel = 8; bitsPerPixel = 8;
fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_8BPP if (info.device_chipset >= RADEON_R1000) { // DCE4
| AVIVO_D1GRPH_CONTROL_8BPP_INDEXED; fbFormat = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_8BPP)
| EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_INDEXED));
} else {
fbFormat = AVIVO_D1GRPH_CONTROL_DEPTH_8BPP
| AVIVO_D1GRPH_CONTROL_8BPP_INDEXED;
}
break; break;
case B_RGB15_LITTLE: case B_RGB15_LITTLE:
bytesPerPixel = 2; bytesPerPixel = 2;
bitsPerPixel = 15; bitsPerPixel = 15;
fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP if (info.device_chipset >= RADEON_R1000) { // DCE4
| AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555; fbFormat = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP)
| EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB1555));
} else {
fbFormat = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP
| AVIVO_D1GRPH_CONTROL_16BPP_ARGB1555;
}
break; break;
case B_RGB16_LITTLE: case B_RGB16_LITTLE:
bytesPerPixel = 2; bytesPerPixel = 2;
bitsPerPixel = 16; bitsPerPixel = 16;
fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP
| AVIVO_D1GRPH_CONTROL_16BPP_RGB565; if (info.device_chipset >= RADEON_R1000) { // DCE4
#ifdef __POWERPC__ fbFormat = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_16BPP)
fb_swap = R600_D1GRPH_SWAP_ENDIAN_16BIT; | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB565));
#endif #ifdef __POWERPC__
fbSwap
= EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN16);
#endif
} else {
fbFormat = AVIVO_D1GRPH_CONTROL_DEPTH_16BPP
| AVIVO_D1GRPH_CONTROL_16BPP_RGB565;
#ifdef __POWERPC__
fbSwap = R600_D1GRPH_SWAP_ENDIAN_16BIT;
#endif
}
break; break;
case B_RGB24_LITTLE: case B_RGB24_LITTLE:
case B_RGB32_LITTLE: case B_RGB32_LITTLE:
default: default:
bytesPerPixel = 4; bytesPerPixel = 4;
bitsPerPixel = 32; bitsPerPixel = 32;
fb_format = AVIVO_D1GRPH_CONTROL_DEPTH_32BPP if (info.device_chipset >= RADEON_R1000) { // DCE4
| AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888; fbFormat = (EVERGREEN_GRPH_DEPTH(EVERGREEN_GRPH_DEPTH_32BPP)
#ifdef __POWERPC__ | EVERGREEN_GRPH_FORMAT(EVERGREEN_GRPH_FORMAT_ARGB8888));
fb_swap = R600_D1GRPH_SWAP_ENDIAN_32BIT; #ifdef __POWERPC__
#endif fbSwap
= EVERGREEN_GRPH_ENDIAN_SWAP(EVERGREEN_GRPH_ENDIAN_8IN32);
#endif
} else {
fbFormat = AVIVO_D1GRPH_CONTROL_DEPTH_32BPP
| AVIVO_D1GRPH_CONTROL_32BPP_ARGB8888;
#ifdef __POWERPC__
fbSwap = R600_D1GRPH_SWAP_ENDIAN_32BIT;
#endif
}
break; break;
} }
@@ -898,9 +932,6 @@ display_crtc_fb_set_dce1(uint8 crtcID, display_mode *mode)
uint64 fbAddressInt = gInfo->shared_info->frame_buffer_int; uint64 fbAddressInt = gInfo->shared_info->frame_buffer_int;
Write32(OUT, regs->grphPrimarySurfaceAddr, (fbAddressInt & 0xFFFFFFFF));
Write32(OUT, regs->grphSecondarySurfaceAddr, (fbAddressInt & 0xFFFFFFFF));
if (info.device_chipset >= (RADEON_R700 | 0x70)) { if (info.device_chipset >= (RADEON_R700 | 0x70)) {
Write32(OUT, regs->grphPrimarySurfaceAddrHigh, Write32(OUT, regs->grphPrimarySurfaceAddrHigh,
(fbAddressInt >> 32) & 0xf); (fbAddressInt >> 32) & 0xf);
@@ -908,8 +939,14 @@ display_crtc_fb_set_dce1(uint8 crtcID, display_mode *mode)
(fbAddressInt >> 32) & 0xf); (fbAddressInt >> 32) & 0xf);
} }
if (info.device_chipset >= RADEON_R600) Write32(OUT, regs->grphPrimarySurfaceAddr, (fbAddressInt & 0xFFFFFFFF));
Write32(CRT, regs->grphSwapControl, fb_swap); Write32(OUT, regs->grphSecondarySurfaceAddr, (fbAddressInt & 0xFFFFFFFF));
if (info.device_chipset >= RADEON_R600) {
Write32(CRT, regs->grphControl, fbFormat);
Write32(CRT, regs->grphSwapControl, fbSwap);
}
Write32(CRT, regs->grphSurfaceOffsetX, 0); Write32(CRT, regs->grphSurfaceOffsetX, 0);
Write32(CRT, regs->grphSurfaceOffsetY, 0); Write32(CRT, regs->grphSurfaceOffsetY, 0);
@@ -931,18 +968,29 @@ display_crtc_fb_set_dce1(uint8 crtcID, display_mode *mode)
Write32(CRT, regs->viewportSize, Write32(CRT, regs->viewportSize,
(viewport_w << 16) | viewport_h); (viewport_w << 16) | viewport_h);
uint32 tmp = Read32(CRT, AVIVO_D1GRPH_FLIP_CONTROL + regs->crtcOffset); // Pageflip setup
tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN; if (info.device_chipset >= RADEON_R1000) { // DCE4
Write32(OUT, AVIVO_D1GRPH_FLIP_CONTROL + regs->crtcOffset, tmp); uint32 tmp
= Read32(OUT, EVERGREEN_GRPH_FLIP_CONTROL + regs->crtcOffset);
tmp &= ~EVERGREEN_GRPH_SURFACE_UPDATE_H_RETRACE_EN;
Write32(OUT, EVERGREEN_GRPH_FLIP_CONTROL + regs->crtcOffset, tmp);
Write32(OUT, AVIVO_D1MODE_MASTER_UPDATE_MODE + regs->crtcOffset, 0); Write32(OUT, EVERGREEN_MASTER_UPDATE_MODE + regs->crtcOffset, 0);
// Pageflip to happen anywhere in vblank // Pageflip to happen anywhere in vblank
} else {
uint32 tmp = Read32(OUT, AVIVO_D1GRPH_FLIP_CONTROL + regs->crtcOffset);
tmp &= ~AVIVO_D1GRPH_SURFACE_UPDATE_H_RETRACE_EN;
Write32(OUT, AVIVO_D1GRPH_FLIP_CONTROL + regs->crtcOffset, tmp);
Write32(OUT, AVIVO_D1MODE_MASTER_UPDATE_MODE + regs->crtcOffset, 0);
// Pageflip to happen anywhere in vblank
}
// update shared info // update shared info
gInfo->shared_info->bytes_per_row = bytesPerRow; gInfo->shared_info->bytes_per_row = bytesPerRow;
gInfo->shared_info->current_mode = *mode; gInfo->shared_info->current_mode = *mode;
gInfo->shared_info->bits_per_pixel = bitsPerPixel; gInfo->shared_info->bits_per_pixel = bitsPerPixel;
} }
src/add-ons/accelerants/radeon_hd/display.h
+1 -1
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@@ -69,7 +69,7 @@ uint32 display_get_encoder_mode(uint32 connectorIndex);
void display_crtc_lock(uint8 crtcID, int command); void display_crtc_lock(uint8 crtcID, int command);
void display_crtc_blank(uint8 crtcID, int command); void display_crtc_blank(uint8 crtcID, int command);
void display_crtc_scale(uint8 crtcID, display_mode *mode); void display_crtc_scale(uint8 crtcID, display_mode *mode);
void display_crtc_fb_set_dce1(uint8 crtcID, display_mode *mode); void display_crtc_fb_set(uint8 crtcID, display_mode *mode);
void display_crtc_set(uint8 crtcID, display_mode *mode); void display_crtc_set(uint8 crtcID, display_mode *mode);
void display_crtc_set_dtd(uint8 crtcID, display_mode *mode); void display_crtc_set_dtd(uint8 crtcID, display_mode *mode);
void display_crtc_power(uint8 crtcID, int command); void display_crtc_power(uint8 crtcID, int command);
src/add-ons/accelerants/radeon_hd/mode.cpp
+1 -2
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@@ -178,8 +178,7 @@ radeon_set_display_mode(display_mode *mode)
// TODO: check if ATOM_PPLL1 is used and use ATOM_PPLL2 if so // TODO: check if ATOM_PPLL1 is used and use ATOM_PPLL2 if so
display_crtc_set_dtd(id, mode); display_crtc_set_dtd(id, mode);
// TODO: vvvv : atombios_crtc_set_base display_crtc_fb_set(id, mode);
display_crtc_fb_set_dce1(id, mode);
// atombios_overscan_setup // atombios_overscan_setup
display_crtc_scale(id, mode); display_crtc_scale(id, mode);