kernel/x86_64: Enable AVX-512 when supported

Check for AVX-512 support and enable on detected CPUs.

Additionally, reserve more bytes in the kernel thread state for the
typical case of AVX + AVX512 + PT when running under a VM.

This additional state will not be copied to the userland structures
until we can determine a more future-proof way of handling x86 extended
state.

The change also includes out the newly supported registers when entering
userland. This is done by issuing a `XRSTOR` instruction based on the
stored initial FPU state.

This change should not have any visible effects on non-AVX-512 CPUs.
It has been tested on an i7-1165g7 VM with .NET's AVX-512 test suite:
https://github.com/dotnet/runtime/blob/c0d836dbe2315b310e7e099afcb50475dce1a521/src/tests/nativeaot/SmokeTests/HardwareIntrinsics/Program.cs#L398-L424

Change-Id: Iad5123e6d13dff39c0fd3957f7e8135202236460
Reviewed-on: https://review.haiku-os.org/c/haiku/+/10853
Reviewed-by: waddlesplash <[email protected]>
Reviewed-by: Adrien Destugues <[email protected]>
Tested-by: Commit checker robot <[email protected]>

headers/private/kernel/arch/x86/arch_thread_types.h

@@ -60,10 +60,10 @@ struct arch_thread {
 	uint8			fpu_state[512] _ALIGNED(16);
 #else
 	// floating point save point - this must be 64 byte aligned for xsave and
-	// have enough space for all the registers, at least 2560 bytes according
-	// to Intel Architecture Instruction Set Extensions Programming Reference,
-	// Section 3.2.4, table 3-8
-	uint8			user_fpu_state[2560] _ALIGNED(64);
+	// have enough space for all the registers.
+	// This is sufficient for AVX, AVX-512 (which we conditionally enable)
+	// and PT (may be force-enabled by the host when we are running under VMs).
+	uint8			user_fpu_state[2688] _ALIGNED(64);
 #endif
 
 	addr_t			GetFramePointer() const;