openBeOS_Matrox_V0.14_src
git-svn-id: file:///srv/svn/repos/haiku/trunk/current@5541 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
shatty
@@ -5,7 +5,7 @@
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Other authors:
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Mark Watson;
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Apsed;
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Rudolf Cornelissen 10/2002.
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Rudolf Cornelissen 10/2002-4/2003.
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*/
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#ifndef DRIVERINTERFACE_H
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@@ -87,6 +87,7 @@ typedef struct settings { // apsed, see comments in mga.settings
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uint32 memory;
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bool usebios;
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bool hardcursor;
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bool greensync;
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} settings;
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/*shared info*/
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@@ -136,28 +137,33 @@ typedef struct {
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uint16 width; /* Width and height of the cursor shape (always 16!) */
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uint16 height;
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bool is_visible; /* Is the cursor currently displayed? */
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}cursor;
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} cursor;
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/*colour lookup table*/
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uint8 color_data[3 * 256]; /* Colour lookup table - as used by DAC */
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/*more display mode stuff*/
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display_mode dm; /* current display mode configuration */
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display_mode dm; /* current display mode configuration: head1 */
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display_mode dm2; /* current display mode configuration: head2 */
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bool switched_crtcs; /* dualhead stretch and switch mode info */
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bool acc_mode; /* signals (non)accelerated mode */
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bool interlaced_tv_mode;/* signals interlaced CRTC TV output mode */
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/*frame buffer config - for BDirectScreen*/
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frame_buffer_config fbc; /* bytes_per_row and start of frame buffer */
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frame_buffer_config fbc; /* bytes_per_row and start of frame buffer: head1 */
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frame_buffer_config fbc2; /* bytes_per_row and start of frame buffer: head2 */
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/*acceleration engine*/
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struct {
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uint32 count; /* last dwgsync slot used */
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uint32 last_idle; /* last dwgsync slot we *know* the engine was idle after */
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benaphore lock; /* for serializing access to the acceleration engine */
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} engine;
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} engine;
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/* card info - information gathered from PINS (and other sources) */
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enum
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{ // card_type in order of date of MGA chip design
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MILL=0,
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MIL1 = 0,
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MYST,
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MIL2,
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G100,
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@@ -27,7 +27,7 @@
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#define MGACFG_AGP_STS 0xf4 // >= MIL2
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#define MGACFG_AGP_CMD 0xf8 // >= MIL2
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/*VGA registers - these are byte wide*/
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/* VGA registers - these are byte wide */
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#define MGAVGA_ATTR_I 0x1FC0 // apsed as SEQ
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#define MGAVGA_ATTR_D 0x1FC1 // apsed as SEQ
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#define MGAVGA_MISCW 0x1FC2
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@@ -45,7 +45,38 @@
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#define MGAVGA_CRTCEXT_I 0x1FDE
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#define MGAVGA_CRTCEXT_D 0x1FDF
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/*DAC registers (>= g100) */
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/* TVP3026 'non-std' DAC registers (>= MIL1) */
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#define MGADAC_TVP_CUROVRWTADD 0x3c04
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#define MGADAC_TVP_CUROVRDATA 0x3c05
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#define MGADAC_TVP_CUROVRRDADD 0x3c07
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#define MGADAC_TVP_DIRCURCTRL 0x3c09
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#define MGADAC_TVP_CURRAMDATA 0x3c0b
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/* TVP3026 'non'std' (D)AC (X) (I)ndexed registers (>= MIL1) */
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#define MGADXI_TVP_SILICONREV 0x01
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#define MGADXI_TVP_LATCHCTRL 0x0f
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#define MGADXI_TVP_TCOLCTRL 0x18
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#define MGADXI_TVP_CLOCKSEL 0x1a
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#define MGADXI_TVP_PALPAGE 0x1c
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#define MGADXI_TVP_PLLADDR 0x2c
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#define MGADXI_TVP_PIXPLLDATA 0x2d
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#define MGADXI_TVP_MEMPLLDATA 0x2e
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#define MGADXI_TVP_LOOPLLDATA 0x2f
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#define MGADXI_TVP_COLKEYOL 0x30
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#define MGADXI_TVP_COLKEYOH 0x31
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#define MGADXI_TVP_COLKEYRL 0x32
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#define MGADXI_TVP_COLKEYRH 0x33
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#define MGADXI_TVP_COLKEYGL 0x34
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#define MGADXI_TVP_COLKEYGH 0x35
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#define MGADXI_TVP_COLKEYBL 0x36
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#define MGADXI_TVP_COLKEYBH 0x37
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#define MGADXI_TVP_COLKEYCTRL 0x38
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#define MGADXI_TVP_MEMCLKCTRL 0x39
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#define MGADXI_TVP_TESTMODEDATA 0x3b
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#define MGADXI_TVP_ID 0x3f
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#define MGADXI_TVP_RESET 0xff
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/* DAC registers (>= G100) */
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#define MGADAC_PALWTADD 0x3C00
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#define MGADAC_PALDATA 0x3C01
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#define MGADAC_PIXRDMSK 0x3C02
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@@ -56,7 +87,7 @@
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#define MGADAC_CURSPOSYL 0x3C0E
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#define MGADAC_CURSPOSYH 0x3C0F
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/*(D)AC (X) (I)ndexed registers (>= g100) */
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/* (D)AC (X) (I)ndexed registers (>= G100) */
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#define MGADXI_CURADDL 0x04
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#define MGADXI_CURADDH 0x05
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#define MGADXI_CURCTRL 0x06
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@@ -101,7 +132,7 @@
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#define MGADXI_PIXPLLSTAT 0x4F
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#define MGADXI_CURCOLEXT 0x60 /*sequential from CURCOL3->15, RGB*/
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/*(D)AC (X) (I)ndexed registers (>= g200) */
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/* (D)AC (X) (I)ndexed registers (>= G200) */
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#define MGADXI_KEYOPMODE 0x51
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#define MGADXI_COLMSK0RED 0x52
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#define MGADXI_COLMSK0GREEN 0x53
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@@ -110,7 +141,7 @@
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#define MGADXI_COLKEY0GREEN 0x56
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#define MGADXI_COLKEY0BLUE 0x57
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/*(D)AC (X) (I)ndexed registers (>= g450?) */
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/* (D)AC (X) (I)ndexed registers (>= G450) */
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#define MGADXI_TVO_IDX 0x87
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#define MGADXI_TVO_DATA 0x88
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#define MGADXI_OUTPUTCONN 0x8A
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@@ -122,11 +153,10 @@
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#define MGADXI_PWRCTRL 0xA0
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#define MGADXI_PANMODE 0xA2
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/*MGA 1st CRTC registers */
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/* MGA 1st CRTC registers */
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#define MGACR1_VCOUNT 0x1E20
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//end rudolf.
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/*MGA 2nd CRTC registers >= ?? TODO */
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/* MGA 2nd CRTC registers (>= G400) */
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#define MGACR2_CTL 0x3C10
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#define MGACR2_HPARAM 0x3C14
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#define MGACR2_HSYNC 0x3C18
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@@ -134,12 +164,13 @@
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#define MGACR2_VSYNC 0x3C20
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#define MGACR2_PRELOAD 0x3C24
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#define MGACR2_STARTADD0 0x3C28
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#define MGACR2_STARTADD1 0x3C2C
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#define MGACR2_OFFSET 0x3C40
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#define MGACR2_MISC 0x3C44
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#define MGACR2_VCOUNT 0x3C48
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#define MGACR2_DATACTL 0x3C4C
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/*MGA ACCeleration registers*/
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/* MGA ACCeleration registers */
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#define MGAACC_DWGCTL 0x1C00
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#define MGAACC_MACCESS 0x1C04
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#define MGAACC_MCTLWTST 0x1C08
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@@ -183,7 +214,7 @@
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#define MGAACC_SRCORG 0x2CB4 // >= G200
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#define MGAACC_DSTORG 0x2CB8 // >= G200
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/*MGA BES (Back End Scaler) registers >= TODO */
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/*MGA BES (Back End Scaler) registers (>= G200) */
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#define MGABES_A1ORG 0x3D00
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#define MGABES_A2ORG 0x3D04
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#define MGABES_B1ORG 0x3D08
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@@ -213,15 +244,34 @@
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#define MGABES_GLOBCTL 0x3DC0
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#define MGABES_STATUS 0x3DC4
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/*MAVEN registers >= TODO */
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/*MAVEN registers (<= G400) */
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#define MGAMAV_PGM 0x3E
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#define MGAMAV_PIXPLLM 0x80
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#define MGAMAV_PIXPLLN 0x81
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#define MGAMAV_PIXPLLP 0x82
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#define MGAMAV_GAMMA1 0x83
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#define MGAMAV_GAMMA2 0x84
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#define MGAMAV_GAMMA3 0x85
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#define MGAMAV_GAMMA4 0x86
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#define MGAMAV_GAMMA5 0x87
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#define MGAMAV_GAMMA6 0x88
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#define MGAMAV_GAMMA7 0x89
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#define MGAMAV_GAMMA8 0x8A
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#define MGAMAV_GAMMA9 0x8B
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#define MGAMAV_MONSET 0x8C
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#define MGAMAV_TEST 0x8D
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#define MGAMAV_WREG_0X8E_L 0x8E
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#define MGAMAV_WREG_0X8E_H 0x8F
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#define MGAMAV_HSCALETV 0x90
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#define MGAMAV_TSCALETVL 0x91
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#define MGAMAV_TSCALETVH 0x92
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#define MGAMAV_FFILTER 0x93
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#define MGAMAV_MONEN 0x94
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#define MGAMAV_RESYNC 0x95
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#define MGAMAV_LASTLINEL 0x96
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#define MGAMAV_LASTLINEH 0x97
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#define MGAMAV_WREG_0X98_L 0x98
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#define MGAMAV_WREG_0X98_H 0x99
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#define MGAMAV_HSYNCLENL 0x9A
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#define MGAMAV_HSYNCLENH 0x9B
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#define MGAMAV_HSYNCSTRL 0x9C
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@@ -242,56 +292,60 @@
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#define MGAMAV_HVIDRSTH 0xAB
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#define MGAMAV_VVIDRSTL 0xAC
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#define MGAMAV_VVIDRSTH 0xAD
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#define MGAMAV_VSOMETHINGL 0xAE
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#define MGAMAV_VSOMETHINGH 0xAF
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#define MGAMAV_OUTMODE 0xB0
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#define MGAMAV_LOCK 0xB3
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#define MGAMAV_LUMA 0xB9
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#define MGAMAV_VDISPLAYTV 0xBE
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#define MGAMAV_STABLE 0xBF
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#define MGAMAV_HDISPLAYTV 0xC2
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#define MGAMAV_BREG_0XC6 0xC6
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/*Macros for convenient accesses to the G400*/
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/* Macros for convenient accesses to the MGA chips */
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#define MGA_REG8(r_) ((vuint8 *)regs)[(r_)]
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#define MGA_REG32(r_) ((vuint32 *)regs)[(r_) >> 2]
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/*read and write to PCI config space*/
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/* read and write to PCI config space */
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#define CFGR(A) (gx00_pci_access.offset=MGACFG_##A, ioctl(fd,GX00_GET_PCI, &gx00_pci_access,sizeof(gx00_pci_access)), gx00_pci_access.value)
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#define CFGW(A,B) (gx00_pci_access.offset=MGACFG_##A, gx00_pci_access.value = B, ioctl(fd,GX00_SET_PCI,&gx00_pci_access,sizeof(gx00_pci_access)))
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/*read and write from the dac registers*/
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/* read and write from the dac registers */
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#define DACR(A) (MGA_REG8(MGADAC_##A))
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#define DACW(A,B) (MGA_REG8(MGADAC_##A)=B)
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/*read and write from the dac index register*/
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/* read and write from the dac index register */
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#define DXIR(A) (DACW(PALWTADD,MGADXI_##A),DACR(X_DATAREG))
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#define DXIW(A,B) (DACW(PALWTADD,MGADXI_##A),DACW(X_DATAREG,B))
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/*read and write from the vga registers*/
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/* read and write from the vga registers */
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#define VGAR(A) (MGA_REG8(MGAVGA_##A))
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#define VGAW(A,B) (MGA_REG8(MGAVGA_##A)=B)
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/*read and write from the indexed vga registers*/
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/* read and write from the indexed vga registers */
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#define VGAR_I(A,B) (VGAW(A##_I,B),VGAR(A##_D))
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#define VGAW_I(A,B,C) (VGAW(A##_I,B),VGAW(A##_D,C))
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/*read and write from the powergraphics registers*/
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/* read and write from the powergraphics registers */
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#define ACCR(A) (MGA_REG32(MGAACC_##A))
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#define ACCW(A,B) (MGA_REG32(MGAACC_##A)=B)
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#define ACCGO(A,B) (MGA_REG32(MGAACC_##A + 0x0100)=B)
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/*read and write from the backend scaler registers*/
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/* read and write from the backend scaler registers */
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#define BESR(A) (MGA_REG32(MGABES_##A))
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#define BESW(A,B) (MGA_REG32(MGABES_##A)=B)
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/*read and write from first CRTC*/
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/* read and write from first CRTC */
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#define CR1R(A) (MGA_REG32(MGACR1_##A))
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#define CR1W(A,B) (MGA_REG32(MGACR1_##A)=B)
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/*read and write from second CRTC*/
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/* read and write from second CRTC */
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#define CR2R(A) (MGA_REG32(MGACR2_##A))
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#define CR2W(A,B) (MGA_REG32(MGACR2_##A)=B)
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/*read and write from maven*/
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/* read and write from maven (<= G400) */
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#define MAVR(A) (i2c_maven_read (MGAMAV_##A ))
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#define MAVW(A,B) (i2c_maven_write(MGAMAV_##A ,B))
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#define MAVRW(A) (i2c_maven_read (MGAMAV_##A )|(i2c_maven_read(MGAMAV_##A +1)<<8))
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#define MAVWW(A,B) (i2c_maven_write(MGAMAV_##A ,B &0xFF),i2c_maven_write(MGAMAV_##A +1,B >>8))
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#define MAVWWP(A,B) (i2c_maven_write(A ,B &0xFF),i2c_maven_write(A +1,B >>8))
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