diff --git a/headers/private/kernel/arch/x86/arch_cpu.h b/headers/private/kernel/arch/x86/arch_cpu.h
index 800f489300..c6d4c11c5e 100644
--- a/headers/private/kernel/arch/x86/arch_cpu.h
+++ b/headers/private/kernel/arch/x86/arch_cpu.h
@@ -243,6 +243,14 @@
 	| X86_EFLAGS_AUXILIARY_CARRY | X86_EFLAGS_ZERO | X86_EFLAGS_SIGN \
 	| X86_EFLAGS_DIRECTION | X86_EFLAGS_OVERFLOW)
 
+#define CR0_CACHE_DISABLE		(1UL << 30)
+#define CR0_NOT_WRITE_THROUGH	(1UL << 29)
+#define CR0_FPU_EMULATION		(1UL << 2)
+#define CR0_MONITOR_FPU			(1UL << 1)
+
+#define CR4_OS_FXSR				(1UL << 9)
+#define CR4_OS_XMM_EXCEPTION	(1UL << 10)
+
 
 // iframe types
 #define IFRAME_TYPE_SYSCALL				0x1
diff --git a/src/system/boot/platform/bios_ia32/long.cpp b/src/system/boot/platform/bios_ia32/long.cpp
index 8531716198..e558bae6f8 100644
--- a/src/system/boot/platform/bios_ia32/long.cpp
+++ b/src/system/boot/platform/bios_ia32/long.cpp
@@ -278,6 +278,14 @@ convert_kernel_args()
 }
 
 
+static void
+enable_sse()
+{
+	x86_write_cr4(x86_read_cr4() | CR4_OS_FXSR | CR4_OS_XMM_EXCEPTION);
+	x86_write_cr0(x86_read_cr0() & ~(CR0_FPU_EMULATION | CR0_MONITOR_FPU));
+}
+
+
 static void
 long_smp_start_kernel(void)
 {
@@ -287,6 +295,7 @@ long_smp_start_kernel(void)
 	asm("movl %%eax, %%cr0" : : "a" ((1 << 31) | (1 << 16) | (1 << 5) | 1));
 	asm("cld");
 	asm("fninit");
+	enable_sse();
 
 	// Fix our kernel stack address.
 	gKernelArgs.cpu_kstack[cpu].start
@@ -308,6 +317,8 @@ long_start_kernel()
 	if ((info.regs.edx & (1 << 29)) == 0)
 		panic("64-bit kernel requires a 64-bit CPU");
 
+	enable_sse();
+
 	preloaded_elf64_image *image = static_cast<preloaded_elf64_image *>(
 		gKernelArgs.kernel_image.Pointer());
 
diff --git a/src/system/kernel/arch/x86/arch_cpu.cpp b/src/system/kernel/arch/x86/arch_cpu.cpp
index 8a2f7832d1..6cd2628ab5 100644
--- a/src/system/kernel/arch/x86/arch_cpu.cpp
+++ b/src/system/kernel/arch/x86/arch_cpu.cpp
@@ -59,14 +59,6 @@ static const struct cpu_vendor_info vendor_info[VENDOR_NUM] = {
 	{ "NSC", { "Geode by NSC" } },
 };
 
-#define CR0_CACHE_DISABLE		(1UL << 30)
-#define CR0_NOT_WRITE_THROUGH	(1UL << 29)
-#define CR0_FPU_EMULATION		(1UL << 2)
-#define CR0_MONITOR_FPU			(1UL << 1)
-
-#define CR4_OS_FXSR				(1UL << 9)
-#define CR4_OS_XMM_EXCEPTION	(1UL << 10)
-
 #define K8_SMIONCMPHALT			(1ULL << 27)
 #define K8_C1EONCMPHALT			(1ULL << 28)