diff --git a/src/add-ons/accelerants/nvidia/engine/nv_crtc.c b/src/add-ons/accelerants/nvidia/engine/nv_crtc.c
index b6c0d8e2c1..569d614ff4 100644
--- a/src/add-ons/accelerants/nvidia/engine/nv_crtc.c
+++ b/src/add-ons/accelerants/nvidia/engine/nv_crtc.c
@@ -373,7 +373,7 @@ status_t nv_crtc_set_display_pitch()
 	/* enable access to CRTC1 on dualhead cards */
 	if (si->ps.secondary_head) CRTCW(OWNER, 0x00);
 
-	/*program the card!*/
+	/* program the card */
 	CRTCW(PITCHL, (offset & 0x00ff));
 	CRTCW(REPAINT0, ((CRTCR(REPAINT0) & 0x1f) | ((offset & 0x0700) >> 3)));
 
diff --git a/src/add-ons/accelerants/nvidia/engine/nv_crtc2.c b/src/add-ons/accelerants/nvidia/engine/nv_crtc2.c
index 93a61963c1..e5c882461a 100644
--- a/src/add-ons/accelerants/nvidia/engine/nv_crtc2.c
+++ b/src/add-ons/accelerants/nvidia/engine/nv_crtc2.c
@@ -355,7 +355,7 @@ status_t nv_crtc2_set_display_pitch()
 	/* enable access to CRTC2 */
 	CRTC2W(OWNER, 0x03);
 
-	/*program the card!*/
+	/* program the card */
 	CRTC2W(PITCHL, (offset & 0x00ff));
 	CRTC2W(REPAINT0, ((CRTC2R(REPAINT0) & 0x1f) | ((offset & 0x0700) >> 3)));