diff --git a/headers/private/graphics/nvidia/nv_macros.h b/headers/private/graphics/nvidia/nv_macros.h index 36c460d4b6..a69c261b47 100644 --- a/headers/private/graphics/nvidia/nv_macros.h +++ b/headers/private/graphics/nvidia/nv_macros.h @@ -33,9 +33,9 @@ #define NVCFG_CFG_15 0x70 //unknown if used #define NVCFG_CFG_16 0x74 //unknown if used #define NVCFG_CFG_17 0x78 //unknown if used -#define NVCFG_GF2IGPU 0x7c +#define NVCFG_GF2IGPU 0x7c //wrong... #define NVCFG_CFG_19 0x80 //unknown if used -#define NVCFG_GF4MXIGPU 0x84 +#define NVCFG_GF4MXIGPU 0x84 //wrong... #define NVCFG_CFG_21 0x88 //unknown if used #define NVCFG_CFG_22 0x8c //unknown if used #define NVCFG_CFG_23 0x90 //unknown if used @@ -78,12 +78,8 @@ pNv->riva.PRAMDAC = pNv->riva.PRAMDAC0; pNv->riva.PDIO = pNv->riva.PDIO0; } -*/ - /* - * These registers are read/write as 8 bit values. Probably have to map - * sparse on alpha. - */ -/* pNv->riva.PCIO0 = (U008 *)xf86MapPciMem(pScrn->scrnIndex, mmioFlags, + + pNv->riva.PCIO0 = (U008 *)xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag, regBase+0x00601000, 0x00003000); pNv->riva.PDIO0 = (U008 *)xf86MapPciMem(pScrn->scrnIndex, mmioFlags, @@ -97,10 +93,370 @@ pNv->riva.PCRTC0 = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag, regBase+0x00600000, 0x00003000); -Set interrupt enable. -chip->PMC[0x00000140/4] = chip->EnableIRQ & 0x01; + pNv->riva.FIFO = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag, + regBase+0x00800000, 0x00010000); + + pNv->riva.PFIFO = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag, + regBase+0x00002000, 0x00002000); + + pNv->riva.PFB = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag, + regBase+0x00100000, 0x00001000); + + pNv->riva.PMC = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag, + regBase+0x00000000, 0x00009000); + + pNv->riva.PTIMER = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag, + regBase+0x00009000, 0x00001000); + + pNv->riva.PRAMIN = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag, + regBase+0x00710000, 0x00010000); + + pNv->riva.PGRAPH = xf86MapPciMem(pScrn->scrnIndex, mmioFlags, pNv->PciTag, + regBase+0x00400000, 0x00002000); */ +/* used NV INT registers for vblank */ +#define NV32_MAIN_INTE 0x00000140 +#define NV32_CRTC_INTS 0x00600100 +#define NV32_CRTC_INTE 0x00600140 + +/* NV ACCeleration registers */ +/* engine initialisation registers */ +#define NVACC_FORMATS 0x00400618 +#define NVACC_OFFSET0 0x00400640 +#define NVACC_OFFSET1 0x00400644 +#define NVACC_OFFSET2 0x00400648 +#define NVACC_OFFSET3 0x0040064c +#define NVACC_OFFSET4 0x00400650 +#define NVACC_OFFSET5 0x00400654 +#define NVACC_BBASE0 0x00400658 +#define NVACC_BBASE1 0x0040065c +#define NVACC_BBASE2 0x00400660 +#define NVACC_BBASE3 0x00400664 +#define NVACC_NV10_BBASE4 0x00400668 +#define NVACC_NV10_BBASE5 0x0040066c +#define NVACC_PITCH0 0x00400670 +#define NVACC_PITCH1 0x00400674 +#define NVACC_PITCH2 0x00400678 +#define NVACC_PITCH3 0x0040067c +#define NVACC_PITCH4 0x00400680 +#define NVACC_BLIMIT0 0x00400684 +#define NVACC_BLIMIT1 0x00400688 +#define NVACC_BLIMIT2 0x0040068c +#define NVACC_BLIMIT3 0x00400690 +#define NVACC_NV10_BLIMIT4 0x00400694 +#define NVACC_NV10_BLIMIT5 0x00400698 +#define NVACC_BPIXEL 0x00400724 +#define NVACC_NV20_OFFSET0 0x00400820 +#define NVACC_NV20_OFFSET1 0x00400824 +#define NVACC_NV20_OFFSET2 0x00400828 +#define NVACC_NV20_OFFSET3 0x0040082c +#define NVACC_STRD_FMT 0x00400830 +#define NVACC_NV20_PITCH0 0x00400850 +#define NVACC_NV20_PITCH1 0x00400854 +#define NVACC_NV20_PITCH2 0x00400858 +#define NVACC_NV20_PITCH3 0x0040085c +#define NVACC_NV20_BLIMIT6 0x00400864 +#define NVACC_NV20_BLIMIT7 0x00400868 +#define NVACC_NV20_BLIMIT8 0x0040086c +#define NVACC_NV20_BLIMIT9 0x00400870 +#define NVACC_NV30_WHAT 0x00400890 + +/* specials */ +#define NVACC_DEBUG0 0x00400080 +#define NVACC_DEBUG1 0x00400084 +#define NVACC_DEBUG2 0x00400088 +#define NVACC_DEBUG3 0x0040008c +#define NVACC_NV10_DEBUG4 0x00400090 +#define NVACC_ACC_INTS 0x00400100 +#define NVACC_ACC_INTE 0x00400140 +#define NVACC_NV10_CTX_CTRL 0x00400144 +#define NVACC_STATUS 0x00400700 +#define NVACC_NV04_SURF_TYP 0x0040070c +#define NVACC_NV10_SURF_TYP 0x00400710 +#define NVACC_NV04_ACC_STAT 0x00400710 +#define NVACC_NV10_ACC_STAT 0x00400714 +#define NVACC_FIFO_EN 0x00400720 +#define NVACC_PAT_SHP 0x00400810 +#define NVACC_NV10_XFMOD0 0x00400f40 +#define NVACC_NV10_XFMOD1 0x00400f44 +#define NVACC_NV10_PIPEADR 0x00400f50 +#define NVACC_NV10_PIPEDAT 0x00400f54 +/* PGRAPH cache registers */ +#define NVACC_CACHE1_1 0x00400160 +#define NVACC_CACHE1_2 0x00400180 +#define NVACC_CACHE1_3 0x004001a0 +#define NVACC_CACHE1_4 0x004001c0 +#define NVACC_CACHE1_5 0x004001e0 +#define NVACC_CACHE2_1 0x00400164 +#define NVACC_CACHE2_2 0x00400184 +#define NVACC_CACHE2_3 0x004001a4 +#define NVACC_CACHE2_4 0x004001c4 +#define NVACC_CACHE2_5 0x004001e4 +#define NVACC_CACHE3_1 0x00400168 +#define NVACC_CACHE3_2 0x00400188 +#define NVACC_CACHE3_3 0x004001a8 +#define NVACC_CACHE3_4 0x004001c8 +#define NVACC_CACHE3_5 0x004001e8 +#define NVACC_CACHE4_1 0x0040016c +#define NVACC_CACHE4_2 0x0040018c +#define NVACC_CACHE4_3 0x004001ac +#define NVACC_CACHE4_4 0x004001cc +#define NVACC_CACHE4_5 0x004001ec +#define NVACC_NV10_CACHE5_1 0x00400170 +#define NVACC_NV04_CTX_CTRL 0x00400170 +#define NVACC_CACHE5_2 0x00400190 +#define NVACC_CACHE5_3 0x004001b0 +#define NVACC_CACHE5_4 0x004001d0 +#define NVACC_CACHE5_5 0x004001f0 +#define NVACC_NV10_CACHE6_1 0x00400174 +#define NVACC_CACHE6_2 0x00400194 +#define NVACC_CACHE6_3 0x004001b4 +#define NVACC_CACHE6_4 0x004001d4 +#define NVACC_CACHE6_5 0x004001f4 +#define NVACC_NV10_CACHE7_1 0x00400178 +#define NVACC_CACHE7_2 0x00400198 +#define NVACC_CACHE7_3 0x004001b8 +#define NVACC_CACHE7_4 0x004001d8 +#define NVACC_CACHE7_5 0x004001f8 +#define NVACC_NV10_CACHE8_1 0x0040017c +#define NVACC_CACHE8_2 0x0040019c +#define NVACC_CACHE8_3 0x004001bc +#define NVACC_CACHE8_4 0x004001dc +#define NVACC_CACHE8_5 0x004001fc +#define NVACC_NV10_CTX_SW1 0x0040014c +#define NVACC_NV10_CTX_SW2 0x00400150 +#define NVACC_NV10_CTX_SW3 0x00400154 +#define NVACC_NV10_CTX_SW4 0x00400158 +#define NVACC_NV10_CTX_SW5 0x0040015c +/* engine tile registers src */ +#define NVACC_NV20_FBWHAT0 0x00100200 +#define NVACC_NV20_FBWHAT1 0x00100204 +#define NVACC_NV10_FBTIL0AD 0x00100240 +#define NVACC_NV10_FBTIL0ED 0x00100244 +#define NVACC_NV10_FBTIL0PT 0x00100248 +#define NVACC_NV10_FBTIL0ST 0x0010024c +#define NVACC_NV10_FBTIL1AD 0x00100250 +#define NVACC_NV10_FBTIL1ED 0x00100254 +#define NVACC_NV10_FBTIL1PT 0x00100258 +#define NVACC_NV10_FBTIL1ST 0x0010025c +#define NVACC_NV10_FBTIL2AD 0x00100260 +#define NVACC_NV10_FBTIL2ED 0x00100264 +#define NVACC_NV10_FBTIL2PT 0x00100268 +#define NVACC_NV10_FBTIL2ST 0x0010026c +#define NVACC_NV10_FBTIL3AD 0x00100270 +#define NVACC_NV10_FBTIL3ED 0x00100274 +#define NVACC_NV10_FBTIL3PT 0x00100278 +#define NVACC_NV10_FBTIL3ST 0x0010027c +#define NVACC_NV10_FBTIL4AD 0x00100280 +#define NVACC_NV10_FBTIL4ED 0x00100284 +#define NVACC_NV10_FBTIL4PT 0x00100288 +#define NVACC_NV10_FBTIL4ST 0x0010028c +#define NVACC_NV10_FBTIL5AD 0x00100290 +#define NVACC_NV10_FBTIL5ED 0x00100294 +#define NVACC_NV10_FBTIL5PT 0x00100298 +#define NVACC_NV10_FBTIL5ST 0x0010029c +#define NVACC_NV10_FBTIL6AD 0x001002a0 +#define NVACC_NV10_FBTIL6ED 0x001002a4 +#define NVACC_NV10_FBTIL6PT 0x001002a8 +#define NVACC_NV10_FBTIL6ST 0x001002ac +#define NVACC_NV10_FBTIL7AD 0x001002b0 +#define NVACC_NV10_FBTIL7ED 0x001002b4 +#define NVACC_NV10_FBTIL7PT 0x001002b8 +#define NVACC_NV10_FBTIL7ST 0x001002bc +/* engine tile registers dst */ +#define NVACC_NV20_WHAT0 0x004009a4 +#define NVACC_NV20_WHAT1 0x004009a8 +#define NVACC_NV10_TIL0AD 0x00400b00 +#define NVACC_NV10_TIL0ED 0x00400b04 +#define NVACC_NV10_TIL0PT 0x00400b08 +#define NVACC_NV10_TIL0ST 0x00400b0c +#define NVACC_NV10_TIL1AD 0x00400b10 +#define NVACC_NV10_TIL1ED 0x00400b14 +#define NVACC_NV10_TIL1PT 0x00400b18 +#define NVACC_NV10_TIL1ST 0x00400b1c +#define NVACC_NV10_TIL2AD 0x00400b20 +#define NVACC_NV10_TIL2ED 0x00400b24 +#define NVACC_NV10_TIL2PT 0x00400b28 +#define NVACC_NV10_TIL2ST 0x00400b2c +#define NVACC_NV10_TIL3AD 0x00400b30 +#define NVACC_NV10_TIL3ED 0x00400b34 +#define NVACC_NV10_TIL3PT 0x00400b38 +#define NVACC_NV10_TIL3ST 0x00400b3c +#define NVACC_NV10_TIL4AD 0x00400b40 +#define NVACC_NV10_TIL4ED 0x00400b44 +#define NVACC_NV10_TIL4PT 0x00400b48 +#define NVACC_NV10_TIL4ST 0x00400b4c +#define NVACC_NV10_TIL5AD 0x00400b50 +#define NVACC_NV10_TIL5ED 0x00400b54 +#define NVACC_NV10_TIL5PT 0x00400b58 +#define NVACC_NV10_TIL5ST 0x00400b5c +#define NVACC_NV10_TIL6AD 0x00400b60 +#define NVACC_NV10_TIL6ED 0x00400b64 +#define NVACC_NV10_TIL6PT 0x00400b68 +#define NVACC_NV10_TIL6ST 0x00400b6c +#define NVACC_NV10_TIL7AD 0x00400b70 +#define NVACC_NV10_TIL7ED 0x00400b74 +#define NVACC_NV10_TIL7PT 0x00400b78 +#define NVACC_NV10_TIL7ST 0x00400b7c +/* cache setup registers */ +#define NVACC_PF_INTSTAT 0x00002100 +#define NVACC_PF_INTEN 0x00002140 +#define NVACC_PF_RAMHT 0x00002210 +#define NVACC_PF_RAMFC 0x00002214 +#define NVACC_PF_RAMRO 0x00002218 +#define NVACC_PF_CACHES 0x00002500 +#define NVACC_PF_SIZE 0x0000250c +#define NVACC_PF_CACH0_PSH0 0x00003000 +#define NVACC_PF_CACH0_PUL0 0x00003050 +#define NVACC_PF_CACH0_PUL1 0x00003054 +#define NVACC_PF_CACH1_PSH0 0x00003200 +#define NVACC_PF_CACH1_PSH1 0x00003204 +#define NVACC_PF_CACH1_DMAI 0x0000322c +#define NVACC_PF_CACH1_PUL0 0x00003250 +#define NVACC_PF_CACH1_PUL1 0x00003254 +#define NVACC_PF_CACH1_HASH 0x00003258 +/* Ptimer registers */ +#define NVACC_PT_INTSTAT 0x00009100 +#define NVACC_PT_INTEN 0x00009140 +#define NVACC_PT_NUMERATOR 0x00009200 +#define NVACC_PT_DENOMINATR 0x00009210 +/* used PRAMIN registers */ +#define NVACC_PR_CTX0_R 0x00711400 +#define NVACC_PR_CTX1_R 0x00711404 +#define NVACC_PR_CTX2_R 0x00711408 +#define NVACC_PR_CTX3_R 0x0071140c +#define NVACC_PR_CTX0_0 0x00711420 +#define NVACC_PR_CTX1_0 0x00711424 +#define NVACC_PR_CTX2_0 0x00711428 +#define NVACC_PR_CTX3_0 0x0071142c +#define NVACC_PR_CTX0_1 0x00711430 +#define NVACC_PR_CTX1_1 0x00711434 +#define NVACC_PR_CTX2_1 0x00711438 +#define NVACC_PR_CTX3_1 0x0071143c +#define NVACC_PR_CTX0_2 0x00711440 +#define NVACC_PR_CTX1_2 0x00711444 +#define NVACC_PR_CTX2_2 0x00711448 +#define NVACC_PR_CTX3_2 0x0071144c +#define NVACC_PR_CTX0_3 0x00711450 +#define NVACC_PR_CTX1_3 0x00711454 +#define NVACC_PR_CTX2_3 0x00711458 +#define NVACC_PR_CTX3_3 0x0071145c +#define NVACC_PR_CTX0_4 0x00711460 +#define NVACC_PR_CTX1_4 0x00711464 +#define NVACC_PR_CTX2_4 0x00711468 +#define NVACC_PR_CTX3_4 0x0071146c +#define NVACC_PR_CTX0_5 0x00711470 +#define NVACC_PR_CTX1_5 0x00711474 +#define NVACC_PR_CTX2_5 0x00711478 +#define NVACC_PR_CTX3_5 0x0071147c +#define NVACC_PR_CTX0_6 0x00711480 +#define NVACC_PR_CTX1_6 0x00711484 +#define NVACC_PR_CTX2_6 0x00711488 +#define NVACC_PR_CTX3_6 0x0071148c +#define NVACC_PR_CTX0_7 0x00711490 +#define NVACC_PR_CTX1_7 0x00711494 +#define NVACC_PR_CTX2_7 0x00711498 +#define NVACC_PR_CTX3_7 0x0071149c +#define NVACC_PR_CTX0_8 0x007114a0 +#define NVACC_PR_CTX1_8 0x007114a4 +#define NVACC_PR_CTX2_8 0x007114a8 +#define NVACC_PR_CTX3_8 0x007114ac +#define NVACC_PR_CTX0_9 0x007114b0 +#define NVACC_PR_CTX1_9 0x007114b4 +#define NVACC_PR_CTX2_9 0x007114b8 +#define NVACC_PR_CTX3_9 0x007114bc +#define NVACC_PR_CTX0_A 0x007114c0 +#define NVACC_PR_CTX1_A 0x007114c4 /* not used */ +#define NVACC_PR_CTX2_A 0x007114c8 +#define NVACC_PR_CTX3_A 0x007114cc +#define NVACC_PR_CTX0_B 0x007114d0 +#define NVACC_PR_CTX1_B 0x007114d4 +#define NVACC_PR_CTX2_B 0x007114d8 +#define NVACC_PR_CTX3_B 0x007114dc +#define NVACC_PR_CTX0_C 0x007114e0 +#define NVACC_PR_CTX1_C 0x007114e4 +#define NVACC_PR_CTX2_C 0x007114e8 +#define NVACC_PR_CTX3_C 0x007114ec +#define NVACC_PR_CTX0_D 0x007114f0 +#define NVACC_PR_CTX1_D 0x007114f4 +#define NVACC_PR_CTX2_D 0x007114f8 +#define NVACC_PR_CTX3_D 0x007114fc +#define NVACC_PR_CTX0_E 0x00711500 +#define NVACC_PR_CTX1_E 0x00711504 +#define NVACC_PR_CTX2_E 0x00711508 +#define NVACC_PR_CTX3_E 0x0071150c +/* used RAMHT registers (hash-table(?)) */ +#define NVACC_HT_HANDL_00 0x00710000 +#define NVACC_HT_VALUE_00 0x00710004 +#define NVACC_HT_HANDL_01 0x00710008 +#define NVACC_HT_VALUE_01 0x0071000c +#define NVACC_HT_HANDL_02 0x00710010 +#define NVACC_HT_VALUE_02 0x00710014 +#define NVACC_HT_HANDL_03 0x00710018 +#define NVACC_HT_VALUE_03 0x0071001c +#define NVACC_HT_HANDL_04 0x00710020 +#define NVACC_HT_VALUE_04 0x00710024 +#define NVACC_HT_HANDL_05 0x00710028 +#define NVACC_HT_VALUE_05 0x0071002c +#define NVACC_HT_HANDL_06 0x00710030 +#define NVACC_HT_VALUE_06 0x00710034 +#define NVACC_HT_HANDL_10 0x00710080 +#define NVACC_HT_VALUE_10 0x00710084 +#define NVACC_HT_HANDL_11 0x00710088 +#define NVACC_HT_VALUE_11 0x0071008c +#define NVACC_HT_HANDL_12 0x00710090 +#define NVACC_HT_VALUE_12 0x00710094 +#define NVACC_HT_HANDL_13 0x00710098 +#define NVACC_HT_VALUE_13 0x0071009c +#define NVACC_HT_HANDL_14 0x007100a0 +#define NVACC_HT_VALUE_14 0x007100a4 +#define NVACC_HT_HANDL_15 0x007100a8 +#define NVACC_HT_VALUE_15 0x007100ac +#define NVACC_HT_HANDL_16 0x007100b0 +#define NVACC_HT_VALUE_16 0x007100b4 +#define NVACC_HT_HANDL_17 0x007100b8 +#define NVACC_HT_VALUE_17 0x007100bc + +/* acc engine fifo setup registers (for function_register 'mappings') */ +#define NVACC_FIFO_00800000 0x00800000 +#define NVACC_FIFO_00802000 0x00802000 +#define NVACC_FIFO_00804000 0x00804000 +#define NVACC_FIFO_00806000 0x00806000 +#define NVACC_FIFO_00808000 0x00808000 +#define NVACC_FIFO_0080a000 0x0080a000 +#define NVACC_FIFO_0080c000 0x0080c000 +#define NVACC_FIFO_0080e000 0x0080e000 + +/* ROP3 registers (Raster OPeration) */ +#define NV16_ROP_FIFOFREE 0x00800010 /* little endian */ +#define NVACC_ROP_ROP3 0x00800300 /* 'mapped' from 0x00420300 */ + +/* clip registers */ +#define NV16_CLP_FIFOFREE 0x00802010 /* little endian */ +#define NVACC_CLP_TOPLEFT 0x00802300 /* 'mapped' from 0x00450300 */ +#define NVACC_CLP_WIDHEIGHT 0x00802304 /* 'mapped' from 0x00450304 */ + +/* pattern registers */ +#define NV16_PAT_FIFOFREE 0x00804010 /* little endian */ +#define NVACC_PAT_SHAPE 0x00804308 /* 'mapped' from 0x00460308 */ +#define NVACC_PAT_COLOR0 0x00804310 /* 'mapped' from 0x00460310 */ +#define NVACC_PAT_COLOR1 0x00804314 /* 'mapped' from 0x00460314 */ +#define NVACC_PAT_MONO1 0x00804318 /* 'mapped' from 0x00460318 */ +#define NVACC_PAT_MONO2 0x0080431c /* 'mapped' from 0x0046031c */ + +/* blit registers */ +#define NV16_BLT_FIFOFREE 0x00808010 /* little endian */ +#define NVACC_BLT_TOPLFTSRC 0x00808300 /* 'mapped' from 0x00500300 */ +#define NVACC_BLT_TOPLFTDST 0x00808304 /* 'mapped' from 0x00500304 */ +#define NVACC_BLT_SIZE 0x00808308 /* 'mapped' from 0x00500308 */ + +/* used bitmap registers */ +#define NV16_BMP_FIFOFREE 0x0080a010 /* little endian */ +#define NVACC_BMP_COLOR1A 0x0080a3fc /* 'mapped' from 0x006b03fc */ +#define NVACC_BMP_UCRECTL_0 0x0080a400 /* 'mapped' from 0x006b0400 */ +#define NVACC_BMP_UCRECSZ_0 0x0080a404 /* 'mapped' from 0x006b0404 */ + /* Nvidia PCI direct registers */ #define NV32_PWRUPCTRL 0x00000200 #define NV8_MISCW 0x000c03c2 @@ -114,6 +470,7 @@ chip->PMC[0x00000140/4] = chip->EnableIRQ & 0x01; /* bootstrap info registers */ #define NV32_NV4STRAPINFO 0x00100000 +#define NV32_PFB_CONFIG_0 0x00100200 #define NV32_NV10STRAPINFO 0x0010020c #define NV32_NVSTRAPINFO2 0x00101000 @@ -203,6 +560,8 @@ chip->PMC[0x00000140/4] = chip->EnableIRQ & 0x01; #define NVCRTCX_CURCTL2 0x2f #define NVCRTCX_CURCTL1 0x30 #define NVCRTCX_CURCTL0 0x31 +#define NVCRTCX_INTERLACE 0x39 +#define NVCRTCX_EXTRA 0x41 /* Nvidia ATTRIBUTE indexed registers */ /* VGA standard registers: */ @@ -228,6 +587,7 @@ chip->PMC[0x00000140/4] = chip->EnableIRQ & 0x01; #define NVGRPHX_BITMASK 0x08 /* Nvidia BES (Back End Scaler) registers (>= NV10) */ +#define NVBES_NV10_INTE 0x00008140 #define NVBES_NV10_BUFSEL 0x00008700 #define NVBES_NV10_GENCTRL 0x00008704 #define NVBES_NV10_COLKEY 0x00008b00 @@ -260,11 +620,6 @@ chip->PMC[0x00000140/4] = chip->EnableIRQ & 0x01; /* Nvidia MPEG2 hardware decoder (GeForce4MX only) */ #define NVBES_DEC_GENCTRL 0x00001588 -/* - chip->PMC[0x00008140/4] = 0; -*/ -//end new. - /* NV 2nd CRTC registers (>= G400) */ #define NVCR2_CTL 0x3C10 #define NVCR2_HPARAM 0x3C14 @@ -279,50 +634,6 @@ chip->PMC[0x00000140/4] = chip->EnableIRQ & 0x01; #define NVCR2_VCOUNT 0x3C48 #define NVCR2_DATACTL 0x3C4C -/* NV ACCeleration registers */ -#define NVACC_DWGCTL 0x1C00 -#define NVACC_MACCESS 0x1C04 -#define NVACC_MCTLWTST 0x1C08 -#define NVACC_ZORG 0x1C0C -#define NVACC_PLNWT 0x1C1C -#define NVACC_BCOL 0x1C20 -#define NVACC_FCOL 0x1C24 -#define NVACC_XYSTRT 0x1C40 -#define NVACC_XYEND 0x1C44 -#define NVACC_SGN 0x1C58 -#define NVACC_LEN 0x1C5C -#define NVACC_AR0 0x1C60 -#define NVACC_AR3 0x1C6C -#define NVACC_AR5 0x1C74 -#define NVACC_CXBNDRY 0x1C80 -#define NVACC_FXBNDRY 0x1C84 -#define NVACC_YDSTLEN 0x1C88 -#define NVACC_PITCH 0x1C8C -#define NVACC_YDST 0x1C90 -#define NVACC_YDSTORG 0x1C94 -#define NVACC_YTOP 0x1C98 -#define NVACC_YBOT 0x1C9C -#define NVACC_CXLEFT 0x1CA0 -#define NVACC_CXRIGHT 0x1CA4 -#define NVACC_FXLEFT 0x1CA8 -#define NVACC_FXRIGHT 0x1CAC -#define NVACC_STATUS 0x1E14 -#define NVACC_ICLEAR 0x1E18 /* required for interrupt stuff */ -#define NVACC_IEN 0x1E1C /* required for interrupt stuff */ -#define NVACC_RST 0x1E40 -#define NVACC_MEMRDBK 0x1E44 -#define NVACC_OPMODE 0x1E54 -#define NVACC_PRIMADDRESS 0x1E58 -#define NVACC_PRIMEND 0x1E5C -#define NVACC_TEXORG 0x2C24 // >= G100 -#define NVACC_DWGSYNC 0x2C4C // >= G200 -#define NVACC_TEXORG1 0x2CA4 // >= G200 -#define NVACC_TEXORG2 0x2CA8 // >= G200 -#define NVACC_TEXORG3 0x2CAC // >= G200 -#define NVACC_TEXORG4 0x2CB0 // >= G200 -#define NVACC_SRCORG 0x2CB4 // >= G200 -#define NVACC_DSTORG 0x2CB8 // >= G200 - /*MAVEN registers (<= G400) */ #define NVMAV_PGM 0x3E #define NVMAV_PIXPLLM 0x80 @@ -416,6 +727,10 @@ chip->PMC[0x00000140/4] = chip->EnableIRQ & 0x01; /* read and write from PCI GRAPHICS indexed registers */ #define GRPHW(A,B)(NV_REG16(NV16_GRPHIND) = ((NVGRPHX_##A) | ((B) << 8))) #define GRPHR(A) (NV_REG8(NV8_GRPHIND) = (NVGRPHX_##A), NV_REG8(NV8_GRPHDAT)) + +/* read and write from the acceleration engine registers */ +#define ACCR(A) (NV_REG32(NVACC_##A)) +#define ACCW(A,B) (NV_REG32(NVACC_##A)=B) //end new. /* read and write from maven (<= G400) */ @@ -424,11 +739,6 @@ chip->PMC[0x00000140/4] = chip->EnableIRQ & 0x01; #define MAVRW(A) (i2c_maven_read (NVMAV_##A )|(i2c_maven_read(NVMAV_##A +1)<<8)) #define MAVWW(A,B) (i2c_maven_write(NVMAV_##A ,B &0xFF),i2c_maven_write(NVMAV_##A +1,B >>8)) -/* read and write from the powergraphics registers */ -#define ACCR(A) (NV_REG32(NVACC_##A)) -#define ACCW(A,B) (NV_REG32(NVACC_##A)=B) -#define ACCGO(A,B) (NV_REG32(NVACC_##A + 0x0100)=B) - /* read and write from second CRTC */ #define CR2R(A) (NV_REG32(NVCR2_##A)) #define CR2W(A,B) (NV_REG32(NVCR2_##A)=B) diff --git a/src/add-ons/accelerants/nvidia/Acceleration.c b/src/add-ons/accelerants/nvidia/Acceleration.c index 027a33086d..c5c91390bf 100644 --- a/src/add-ons/accelerants/nvidia/Acceleration.c +++ b/src/add-ons/accelerants/nvidia/Acceleration.c @@ -3,21 +3,20 @@ This file may be used under the terms of the Be Sample Code License. Other authors: - Mark Watson, - Apsed, - Rudolf Cornelissen 2/2003. + Rudolf Cornelissen 9/2003. */ #define MODULE_BIT 0x40000000 -// apsed, TODO ?? change interface of nv_acc_* and use NV pseudo DMA - #include "acc_std.h" void SCREEN_TO_SCREEN_BLIT(engine_token *et, blit_params *list, uint32 count) { int i; - /*do each blit*/ + /* init acc engine for blit function */ + nv_acc_setup_blit(); + + /* do each blit */ i=0; while (count--) { @@ -37,7 +36,7 @@ void SCREEN_TO_SCREEN_BLIT(engine_token *et, blit_params *list, uint32 count) { void SCREEN_TO_SCREEN_SCALED_FILTERED_BLIT(engine_token *et, scaled_blit_params *list, uint32 count) { int i; - /*do each blit*/ + /* do each blit */ i=0; while (count--) { @@ -59,7 +58,7 @@ void SCREEN_TO_SCREEN_SCALED_FILTERED_BLIT(engine_token *et, scaled_blit_params void SCREEN_TO_SCREEN_TRANSPARENT_BLIT(engine_token *et, uint32 transparent_colour, blit_params *list, uint32 count) { int i; - /*do each blit*/ + /* do each blit */ i=0; while (count--) { @@ -80,7 +79,10 @@ void SCREEN_TO_SCREEN_TRANSPARENT_BLIT(engine_token *et, uint32 transparent_colo void FILL_RECTANGLE(engine_token *et, uint32 colorIndex, fill_rect_params *list, uint32 count) { int i; - /*draw each rectangle*/ + /* init acc engine for fill function */ + nv_acc_setup_rectangle(colorIndex); + + /* draw each rectangle */ i=0; while (count--) { @@ -89,8 +91,7 @@ void FILL_RECTANGLE(engine_token *et, uint32 colorIndex, fill_rect_params *list, list[i].left, (list[i].right)+1, list[i].top, - (list[i].bottom-list[i].top)+1, - colorIndex + (list[i].bottom-list[i].top)+1 ); i++; } @@ -99,7 +100,10 @@ void FILL_RECTANGLE(engine_token *et, uint32 colorIndex, fill_rect_params *list, void INVERT_RECTANGLE(engine_token *et, fill_rect_params *list, uint32 count) { int i; - /*draw each rectangle*/ + /* init acc engine for invert function */ + nv_acc_setup_rect_invert(); + + /* invert each rectangle */ i=0; while (count--) { @@ -108,8 +112,7 @@ void INVERT_RECTANGLE(engine_token *et, fill_rect_params *list, uint32 count) { list[i].left, (list[i].right)+1, list[i].top, - (list[i].bottom-list[i].top)+1, - 0 + (list[i].bottom-list[i].top)+1 ); i++; } @@ -118,7 +121,10 @@ void INVERT_RECTANGLE(engine_token *et, fill_rect_params *list, uint32 count) { void FILL_SPAN(engine_token *et, uint32 colorIndex, uint16 *list, uint32 count) { int i; - /*draw each span*/ + /* init acc engine for fill function */ + nv_acc_setup_rectangle(colorIndex); + + /* draw each span */ i=0; while (count--) { @@ -127,8 +133,7 @@ void FILL_SPAN(engine_token *et, uint32 colorIndex, uint16 *list, uint32 count) list[i+1], list[i+2]+1, list[i], - 1, - colorIndex + 1 ); i+=3; } diff --git a/src/add-ons/accelerants/nvidia/GetAccelerantHook.c b/src/add-ons/accelerants/nvidia/GetAccelerantHook.c index 238b9f42ae..decd7fbc03 100644 --- a/src/add-ons/accelerants/nvidia/GetAccelerantHook.c +++ b/src/add-ons/accelerants/nvidia/GetAccelerantHook.c @@ -4,7 +4,7 @@ Other authors: Mark Watson, - Rudolf Cornelissen 10/2002-8/2003 + Rudolf Cornelissen 10/2002-9/2003 */ #define MODULE_BIT 0x08000000 @@ -118,8 +118,8 @@ void * get_accelerant_hook(uint32 feature, void *data) CHKA(FILL_SPAN); /* not (yet) used by the app_server: * so just for application use (BWindowScreen) */ - CHKA(SCREEN_TO_SCREEN_TRANSPARENT_BLIT); - //CHKA(SCREEN_TO_SCREEN_SCALED_FILTERED_BLIT; +// CHKA(SCREEN_TO_SCREEN_TRANSPARENT_BLIT); +// CHKA(SCREEN_TO_SCREEN_SCALED_FILTERED_BLIT; } /* Return a null pointer for any feature we don't understand. */ @@ -185,7 +185,6 @@ status_t check_overlay_capability(uint32 feature) status_t check_acc_capability(uint32 feature) { - bool fill = false; char *msg = ""; /* setup logmessage text */ @@ -196,15 +195,12 @@ status_t check_acc_capability(uint32 feature) break; case B_FILL_RECTANGLE: msg = "B_FILL_RECTANGLE"; - fill = true; break; case B_INVERT_RECTANGLE: msg = "B_INVERT_RECTANGLE"; - fill = true; break; case B_FILL_SPAN: msg = "B_FILL_SPAN"; - fill = true; break; case B_SCREEN_TO_SCREEN_TRANSPARENT_BLIT: msg = "B_SCREEN_TO_SCREEN_TRANSPARENT_BLIT"; @@ -221,15 +217,6 @@ status_t check_acc_capability(uint32 feature) * memory pitch.. */ if (si->acc_mode) { - /* see if we support hardware rectangle fills in the current mode: - * the Matrox card's acc engine can adress upto 16Mbyte memory for this cmd! */ - if (fill && - ((si->fbc.bytes_per_row * si->dm.virtual_height) > (16 * 1024 * 1024))) - { - LOG(4, ("Acc: Not exporting hook %s.\n", msg)); - return B_ERROR; - } - LOG(4, ("Acc: Exporting hook %s.\n", msg)); return B_OK; } diff --git a/src/add-ons/accelerants/nvidia/GetModeInfo.c b/src/add-ons/accelerants/nvidia/GetModeInfo.c index 2819c55312..1ea7098fcc 100644 --- a/src/add-ons/accelerants/nvidia/GetModeInfo.c +++ b/src/add-ons/accelerants/nvidia/GetModeInfo.c @@ -130,7 +130,5 @@ status_t GET_PIXEL_CLOCK_LIMITS(display_mode *dm, uint32 *low, uint32 *high) /* Return the semaphore id that will be used to signal a vertical sync occured. */ sem_id ACCELERANT_RETRACE_SEMAPHORE(void) { -// return si->vblank; -//temp: - return B_ERROR; + return si->vblank; } diff --git a/src/add-ons/accelerants/nvidia/Overlay.c b/src/add-ons/accelerants/nvidia/Overlay.c index 715e4da75c..c06b99ca21 100644 --- a/src/add-ons/accelerants/nvidia/Overlay.c +++ b/src/add-ons/accelerants/nvidia/Overlay.c @@ -1,4 +1,4 @@ -/* Written by Rudolf Cornelissen 05-2002/08-2003 */ +/* Written by Rudolf Cornelissen 05-2002/09-2003 */ /* Note on 'missing features' in BeOS 5.0.3 and DANO: * BeOS needs to define more colorspaces! It would be nice if BeOS would support the FourCC 'definitions' @@ -441,8 +441,9 @@ status_t GET_OVERLAY_CONSTRAINTS oc->v_scale.min = 0.125; break; } - oc->h_scale.max = 16384/(float)(ob->width - si->overlay.myBufInfo[offset].slopspace); - oc->v_scale.max = 16384/(float)ob->height; + /* found spec on the net for GF256-GF4. Still needs confirmation... */ + oc->h_scale.max = 8.0; + oc->v_scale.max = 8.0; return B_OK; } diff --git a/src/add-ons/accelerants/nvidia/SetDisplayMode.c b/src/add-ons/accelerants/nvidia/SetDisplayMode.c index 65e71e2b72..2b146585ae 100644 --- a/src/add-ons/accelerants/nvidia/SetDisplayMode.c +++ b/src/add-ons/accelerants/nvidia/SetDisplayMode.c @@ -6,7 +6,7 @@ Other authors: Mark Watson, Apsed, - Rudolf Cornelissen 11/2002-7/2003 + Rudolf Cornelissen 11/2002-10/2003 */ #define MODULE_BIT 0x00200000 @@ -386,12 +386,9 @@ status_t SET_DISPLAY_MODE(display_mode *mode_to_set) // if (target.flags & DUALHEAD_BITS) g400_crtc2_dpms(display,h,v); /* set up acceleration for this mode */ - si->dm.virtual_height += 1;//for clipping! -// nv_acc_init(); - si->dm.virtual_height -= 1; - - /* clear line at bottom of screen (for maven) if dualhead mode */ -// nv_acc_rectangle(0,si->dm.virtual_width+1,si->dm.virtual_height,1,0); + nv_acc_init(); + /* set up overlay unit for this mode */ + if (si->ps.card_arch > NV04A) nv_bes_init(); MSG(("SETMODE: booted since %f mS\n", system_time()/1000.0)); diff --git a/src/add-ons/accelerants/nvidia/engine/nv_acc.c b/src/add-ons/accelerants/nvidia/engine/nv_acc.c index 661d6f2aad..ce4012e14c 100644 --- a/src/add-ons/accelerants/nvidia/engine/nv_acc.c +++ b/src/add-ons/accelerants/nvidia/engine/nv_acc.c @@ -1,7 +1,8 @@ /* NV Acceleration functions */ -/* Authors: - Mark Watson 2/2000, - Rudolf Cornelissen 10/2002-4/2003. +/* Author: + Rudolf Cornelissen 8/2003-10/2003. + + This code was possible thanks to the Linux NV driver. */ #define MODULE_BIT 0x00080000 @@ -17,27 +18,15 @@ invert rectangle blit */ -/* G100 pre SRCORG/DSTORG registers */ -static uint32 src_dst; -/* MIL1/2 adress linearisation does not always work */ -static uint8 y_lin; -static uint8 depth; - -/* needed by MIL 1/2 because of adress linearisation constraints */ -#define ACCW_YDSTLEN(dst, len) do { \ - if (y_lin) { \ - ACCW(YDST,((dst)* (si->fbc.bytes_per_row / (depth >> 3))) >> 5); \ - ACCW(LEN,len); \ - } else ACCW(YDSTLEN,((dst)<<16)|(len)); \ -} while (0) - status_t nv_acc_wait_idle() { -// volatile int i; -// while (ACCR(STATUS)&(1<<16)) -// { -// for (i=0;i<10000;i++); /*spin in place so I do not hammer the bus*/ -// }; + /* wait until engine completely idle */ + while (ACCR(STATUS)) + { + /* snooze a bit so I do not hammer the bus */ + snooze (100); + } + return B_OK; } @@ -45,394 +34,852 @@ status_t nv_acc_wait_idle() * Engine required init. */ status_t nv_acc_init() { - /* used for convenience: MACCESS is a write only register! */ - uint32 maccess = 0x00000000; - /* if we were unable to read PINS, we have to assume something (keeping bit6 zero) */ -// if ((si->ps.card_type >= G450) && (si->ps.pins_status = B_OK)) -// { - /* b7 v5_mem_type = done by Mark Watson. fixme: still confirm! (unknown bits) */ -// maccess |= ((((uint32)si->ps.v5_mem_type) & 0x80) >> 1); -// } + uint16 cnt; - /* preset using hardware adress linearisation */ - y_lin = 0x00; - /* reset depth */ - depth = 0; + /* setup PTIMER: */ + /* set timer numerator to 8 (in b0-15) */ + ACCW(PT_NUMERATOR, 0x00000008); + /* set timer denominator to 3 (in b0-15) */ + ACCW(PT_DENOMINATR, 0x00000003); + /* disable timer-alarm INT requests (b0) */ + ACCW(PT_INTEN, 0x00000000); + /* reset timer-alarm INT status bit (b0) */ + ACCW(PT_INTSTAT, 0xffffffff); - /* cleanup bitblt */ - ACCW(OPMODE,0); + /* enable PRAMIN write access on pre NV10 before programming it! */ + if (si->ps.card_arch == NV04A) + { + /* set framebuffer config: type = notiling, PRAMIN write access enabled */ + NV_REG32(NV32_PFB_CONFIG_0) = 0x00001114; + } - /* Set the Z origin to the start of FB (otherwise lockup on blits) */ - ACCW(ZORG,0); + /*** PFIFO ***/ + /* (setup caches) */ + /* disable caches reassign */ + ACCW(PF_CACHES, 0x00000000); + /* cache1 push0 access disabled */ + ACCW(PF_CACH1_PSH0, 0x00000000); + /* cache1 pull0 access disabled */ + ACCW(PF_CACH1_PUL0, 0x00000000); + /* cache1 push1 mode = pio */ + ACCW(PF_CACH1_PSH1, 0x00000000); + /* cache1 DMA instance adress = 0 (b0-15) */ + ACCW(PF_CACH1_DMAI, 0x00000000); + /* cache0 push0 access disabled */ + ACCW(PF_CACH0_PSH0, 0x00000000); + /* cache0 pull0 access disabled */ + ACCW(PF_CACH0_PUL0, 0x00000000); + /* RAM HT (hash table(?)) baseadress = $10000 (b4-8), size = 4k, + * search = 128 (byte offset between hash 'sets'(?)) */ + /* (note: so(?) HT base is $00710000, last is $00710fff) */ + ACCW(PF_RAMHT, 0x03000100); + /* RAM FC baseadress = $11000 (b3-8) (size is fixed to 0.5k(?)) */ + /* (note: so(?) FC base is $00711000, last is $007111ff) */ + ACCW(PF_RAMFC, 0x00000110); + /* RAM RO baseadress = $11200 (b1-8), size = 0.5k */ + /* (note: so(?) RO base is $00711200, last is $007113ff) */ + /* (note also: + * This means(?) the PRAMIN CTX registers are accessible from base $00711400) */ + ACCW(PF_RAMRO, 0x00000112); + /* PFIFO size: ch0-15 = 512 bytes, ch16-31 = 124 bytes */ + ACCW(PF_SIZE, 0x0000ffff); + /* cache1 hash instance = $ffff (b0-15) */ + ACCW(PF_CACH1_HASH, 0x0000ffff); + /* disable all PFIFO INTs */ + ACCW(PF_INTEN, 0x00000000); + /* reset all PFIFO INT status bits */ + ACCW(PF_INTSTAT, 0xffffffff); + /* cache0 pull0 engine = acceleration engine (graphics) */ + ACCW(PF_CACH0_PUL1, 0x00000001); + /* cache1 push0 access enabled */ + ACCW(PF_CACH1_PSH0, 0x00000001); + /* cache1 pull0 access enabled */ + ACCW(PF_CACH1_PUL0, 0x00000001); + /* cache1 pull1 engine = acceleration engine (graphics) */ + ACCW(PF_CACH1_PUL1, 0x00000001); + /* enable PFIFO caches reassign */ + ACCW(PF_CACHES, 0x00000001); - /* Set pixel width */ + /*** PRAMIN ***/ + /* RAMHT space (hash-table(?)) */ + /* (first set) */ + ACCW(HT_HANDL_00, 0x80000010); /* 32bit handle */ + ACCW(HT_VALUE_00, 0x80011145); /* instance $1145, engine = acc engine, CHID = $00 */ + ACCW(HT_HANDL_01, 0x80000011); /* 32bit handle */ + ACCW(HT_VALUE_01, 0x80011146); /* instance $1146, engine = acc engine, CHID = $00 */ + ACCW(HT_HANDL_02, 0x80000012); /* 32bit handle */ + ACCW(HT_VALUE_02, 0x80011147); /* instance $1147, engine = acc engine, CHID = $00 */ + ACCW(HT_HANDL_03, 0x80000013); /* 32bit handle */ + ACCW(HT_VALUE_03, 0x80011148); /* instance $1148, engine = acc engine, CHID = $00 */ + ACCW(HT_HANDL_04, 0x80000014); /* 32bit handle */ + ACCW(HT_VALUE_04, 0x80011149); /* instance $1149, engine = acc engine, CHID = $00 */ + ACCW(HT_HANDL_05, 0x80000015); /* 32bit handle */ + ACCW(HT_VALUE_05, 0x8001114a); /* instance $114a, engine = acc engine, CHID = $00 */ + ACCW(HT_HANDL_06, 0x80000016); /* 32bit handle */ + if (si->ps.card_arch != NV04A) + ACCW(HT_VALUE_06, 0x80011150); /* instance $1150, engine = acc engine, CHID = $00 */ + else + ACCW(HT_VALUE_06, 0x8001114f); /* instance $114f, engine = acc engine, CHID = $00 */ + /* (second set) */ + ACCW(HT_HANDL_10, 0x80000000); /* 32bit handle */ + ACCW(HT_VALUE_10, 0x80011142); /* instance $1142, engine = acc engine, CHID = $00 */ + ACCW(HT_HANDL_11, 0x80000001); /* 32bit handle */ + ACCW(HT_VALUE_11, 0x80011143); /* instance $1143, engine = acc engine, CHID = $00 */ + ACCW(HT_HANDL_12, 0x80000002); /* 32bit handle */ + ACCW(HT_VALUE_12, 0x80011144); /* instance $1144, engine = acc engine, CHID = $00 */ + ACCW(HT_HANDL_13, 0x80000003); /* 32bit handle */ + ACCW(HT_VALUE_13, 0x8001114b); /* instance $114b, engine = acc engine, CHID = $00 */ + ACCW(HT_HANDL_14, 0x80000004); /* 32bit handle */ + ACCW(HT_VALUE_14, 0x8001114c); /* instance $114c, engine = acc engine, CHID = $00 */ + ACCW(HT_HANDL_15, 0x80000005); /* 32bit handle */ + ACCW(HT_VALUE_15, 0x8001114d); /* instance $114d, engine = acc engine, CHID = $00 */ + ACCW(HT_HANDL_16, 0x80000006); /* 32bit handle */ + ACCW(HT_VALUE_16, 0x8001114e); /* instance $114e, engine = acc engine, CHID = $00 */ + if (si->ps.card_arch != NV04A) + { + ACCW(HT_HANDL_17, 0x80000007); /* 32bit handle */ + ACCW(HT_VALUE_17, 0x8001114f); /* instance $114f, engine = acc engine, CHID = $00 */ + } + /* program CTX registers: CTX1 is mostly done later (colorspace dependant) */ + /* (setup 'root' set first) */ + ACCW(PR_CTX0_R, 0x00003000); /* NVclass = NVroot, chromakey and userclip enabled */ + /* fixme: CTX1_R should reflect RAM amount? (no influence on current used functions) */ + ACCW(PR_CTX1_R, 0x01ffffff); /* cardmemory mask(?) */ + ACCW(PR_CTX2_R, 0x00000002); /* ??? */ + ACCW(PR_CTX3_R, 0x00000002); /* ??? */ + /* (setup set '0') */ + ACCW(PR_CTX0_0, 0x01008043); /* NVclass $043, patchcfg ROP_AND, nv10+: little endian */ + ACCW(PR_CTX2_0, 0x00000000); /* DMA0 and DMA1 instance invalid */ + ACCW(PR_CTX3_0, 0x00000000); /* method traps disabled */ + /* (setup set '1') */ + ACCW(PR_CTX0_1, 0x01008019); /* NVclass $019, patchcfg ROP_AND, nv10+: little endian */ + ACCW(PR_CTX2_1, 0x00000000); /* DMA0 and DMA1 instance invalid */ + ACCW(PR_CTX3_1, 0x00000000); /* method traps disabled */ + /* (setup set '2') */ + ACCW(PR_CTX0_2, 0x01008018); /* NVclass $018, patchcfg ROP_AND, nv10+: little endian */ + ACCW(PR_CTX2_2, 0x00000000); /* DMA0 and DMA1 instance invalid */ + ACCW(PR_CTX3_2, 0x00000000); /* method traps disabled */ + /* (setup set '3') */ + ACCW(PR_CTX0_3, 0x01008021); /* NVclass $021, patchcfg ROP_AND, nv10+: little endian */ + ACCW(PR_CTX2_3, 0x00000000); /* DMA0 and DMA1 instance invalid */ + ACCW(PR_CTX3_3, 0x00000000); /* method traps disabled */ + /* (setup set '4') */ + ACCW(PR_CTX0_4, 0x0100805f); /* NVclass $05f, patchcfg ROP_AND, nv10+: little endian */ + ACCW(PR_CTX2_4, 0x00000000); /* DMA0 and DMA1 instance invalid */ + ACCW(PR_CTX3_4, 0x00000000); /* method traps disabled */ + /* (setup set '5') */ + ACCW(PR_CTX0_5, 0x0100804b); /* NVclass $04b, patchcfg ROP_AND, nv10+: little endian */ + ACCW(PR_CTX2_5, 0x00000000); /* DMA0 and DMA1 instance invalid */ + ACCW(PR_CTX3_5, 0x00000000); /* method traps disabled */ + /* (setup set '6') */ + ACCW(PR_CTX0_6, 0x0100a048); /* NVclass $048, patchcfg ROP_AND, userclip enable, + * nv10+: little endian */ + ACCW(PR_CTX1_6, 0x00000d01); /* format is A8RGB24, MSB mono */ + ACCW(PR_CTX2_6, 0x11401140); /* DMA0, DMA1 instance = $1140 */ + ACCW(PR_CTX3_6, 0x00000000); /* method traps disabled */ + /* (setup set '7') */ + if (si->ps.card_arch != NV04A) + ACCW(PR_CTX0_7, 0x0300a094); /* NVclass $094, patchcfg ROP_AND, userclip enable, + * context surface0 valid, nv10+: little endian */ + else + ACCW(PR_CTX0_7, 0x0300a054); /* NVclass $054, patchcfg ROP_AND, userclip enable, + * context surface0 valid */ + ACCW(PR_CTX1_7, 0x00000d01); /* format is A8RGB24, MSB mono */ + ACCW(PR_CTX2_7, 0x11401140); /* DMA0, DMA1 instance = $1140 */ + ACCW(PR_CTX3_7, 0x00000000); /* method traps disabled */ + /* (setup set '8') */ + if (si->ps.card_arch != NV04A) + ACCW(PR_CTX0_8, 0x0300a095); /* NVclass $095, patchcfg ROP_AND, userclip enable, + * context surface0 valid, nv10+: little endian */ + else + ACCW(PR_CTX0_8, 0x0300a055); /* NVclass $055, patchcfg ROP_AND, userclip enable, + * context surface0 valid */ + ACCW(PR_CTX1_8, 0x00000d01); /* format is A8RGB24, MSB mono */ + ACCW(PR_CTX2_8, 0x11401140); /* DMA0, DMA1 instance = $1140 */ + ACCW(PR_CTX3_8, 0x00000000); /* method traps disabled */ + /* (setup set '9') */ + ACCW(PR_CTX0_9, 0x00000058); /* NVclass $058, nv10+: little endian */ + ACCW(PR_CTX2_9, 0x11401140); /* DMA0, DMA1 instance = $1140 */ + ACCW(PR_CTX3_9, 0x00000000); /* method traps disabled */ + /* (setup set 'A') */ + ACCW(PR_CTX0_A, 0x00000059); /* NVclass $059, nv10+: little endian */ + ACCW(PR_CTX2_A, 0x11401140); /* DMA0, DMA1 instance = $1140 */ + ACCW(PR_CTX3_A, 0x00000000); /* method traps disabled */ + /* (setup set 'B') */ + ACCW(PR_CTX0_B, 0x0000005a); /* NVclass $05a, nv10+: little endian */ + ACCW(PR_CTX2_B, 0x11401140); /* DMA0, DMA1 instance = $1140 */ + ACCW(PR_CTX3_B, 0x00000000); /* method traps disabled */ + /* (setup set 'C') */ + ACCW(PR_CTX0_C, 0x0000005b); /* NVclass $05b, nv10+: little endian */ + ACCW(PR_CTX2_C, 0x11401140); /* DMA0, DMA1 instance = $1140 */ + ACCW(PR_CTX3_C, 0x00000000); /* method traps disabled */ + /* (setup set 'D') */ + if (si->ps.card_arch != NV04A) + ACCW(PR_CTX0_D, 0x00000093); /* NVclass $093, nv10+: little endian */ + else + ACCW(PR_CTX0_D, 0x0300a01c); /* NVclass $01c, patchcfg ROP_AND, userclip enable, + * context surface0 valid */ + ACCW(PR_CTX2_D, 0x11401140); /* DMA0, DMA1 instance = $1140 */ + ACCW(PR_CTX3_D, 0x00000000); /* method traps disabled */ + /* (setup set 'E' if needed) */ + if (si->ps.card_arch != NV04A) + { + ACCW(PR_CTX0_E, 0x0300a01c); /* NVclass $01c, patchcfg ROP_AND, userclip enable, + * context surface0 valid, nv10+: little endian */ + ACCW(PR_CTX2_E, 0x11401140); /* DMA0, DMA1 instance = $1140 */ + ACCW(PR_CTX3_E, 0x00000000); /* method traps disabled */ + } + + /*** PGRAPH ***/ + if (si->ps.card_arch != NV04A) + { + /* set resetstate for most function blocks */ + ACCW(DEBUG0, 0x0003ffff); + /* init some function blocks */ + ACCW(DEBUG1, 0x00118701); + ACCW(DEBUG2, 0x24f82ad9); + ACCW(DEBUG3, 0x55de0030); + /* end resetstate for the function blocks */ + ACCW(DEBUG0, 0x00000000); + /* disable specific functions */ + ACCW(NV10_DEBUG4, 0); + } + else + { + /* init some function blocks */ + ACCW(DEBUG0, 0x1231c001); + ACCW(DEBUG1, 0x72111101); + ACCW(DEBUG2, 0x11d5f071); + ACCW(DEBUG3, 0x10d4ff31); + } + + /* reset all cache sets */ + ACCW(CACHE1_1, 0); + ACCW(CACHE1_2, 0); + ACCW(CACHE1_3, 0); + ACCW(CACHE1_4, 0); + ACCW(CACHE1_5, 0); + ACCW(CACHE2_1, 0); + ACCW(CACHE2_2, 0); + ACCW(CACHE2_3, 0); + ACCW(CACHE2_4, 0); + ACCW(CACHE2_5, 0); + ACCW(CACHE3_1, 0); + ACCW(CACHE3_2, 0); + ACCW(CACHE3_3, 0); + ACCW(CACHE3_4, 0); + ACCW(CACHE3_5, 0); + ACCW(CACHE4_1, 0); + ACCW(CACHE4_2, 0); + ACCW(CACHE4_3, 0); + ACCW(CACHE4_4, 0); + ACCW(CACHE4_5, 0); + if (si->ps.card_arch != NV04A) + ACCW(NV10_CACHE5_1, 0); + ACCW(CACHE5_2, 0); + ACCW(CACHE5_3, 0); + ACCW(CACHE5_4, 0); + ACCW(CACHE5_5, 0); + if (si->ps.card_arch != NV04A) + ACCW(NV10_CACHE6_1, 0); + ACCW(CACHE6_2, 0); + ACCW(CACHE6_3, 0); + ACCW(CACHE6_4, 0); + ACCW(CACHE6_5, 0); + if (si->ps.card_arch != NV04A) + ACCW(NV10_CACHE7_1, 0); + ACCW(CACHE7_2, 0); + ACCW(CACHE7_3, 0); + ACCW(CACHE7_4, 0); + ACCW(CACHE7_5, 0); + if (si->ps.card_arch != NV04A) + ACCW(NV10_CACHE8_1, 0); + ACCW(CACHE8_2, 0); + ACCW(CACHE8_3, 0); + ACCW(CACHE8_4, 0); + ACCW(CACHE8_5, 0); + + if (si->ps.card_arch != NV04A) + { + /* reset (disable) context switch stuff */ + ACCW(NV10_CTX_SW1, 0); + ACCW(NV10_CTX_SW2, 0); + ACCW(NV10_CTX_SW3, 0); + ACCW(NV10_CTX_SW4, 0); + ACCW(NV10_CTX_SW5, 0); + } + + /* setup accesible card memory range for acc engine */ + ACCW(BBASE0, 0x00000000); + ACCW(BBASE1, 0x00000000); + ACCW(BBASE2, 0x00000000); + ACCW(BBASE3, 0x00000000); + ACCW(BLIMIT0, ((si->ps.memory_size << 20) - 1)); + ACCW(BLIMIT1, ((si->ps.memory_size << 20) - 1)); + ACCW(BLIMIT2, ((si->ps.memory_size << 20) - 1)); + ACCW(BLIMIT3, ((si->ps.memory_size << 20) - 1)); + if (si->ps.card_arch >= NV10A) + { + ACCW(NV10_BBASE4, 0x00000000); + ACCW(NV10_BBASE5, 0x00000000); + ACCW(NV10_BLIMIT4, ((si->ps.memory_size << 20) - 1)); + ACCW(NV10_BLIMIT5, ((si->ps.memory_size << 20) - 1)); + } + if (si->ps.card_arch >= NV20A) + { + /* fixme(?): assuming more BLIMIT registers here: Then how about BBASE6-9? + * (linux fixed value 'BLIMIT6-9' 0x01ffffff) */ + ACCW(NV20_BLIMIT6, ((si->ps.memory_size << 20) - 1)); + ACCW(NV20_BLIMIT7, ((si->ps.memory_size << 20) - 1)); + ACCW(NV20_BLIMIT8, ((si->ps.memory_size << 20) - 1)); + ACCW(NV20_BLIMIT9, ((si->ps.memory_size << 20) - 1)); + } + + /* disable all acceleration engine INT reguests */ + ACCW(ACC_INTE, 0x00000000); + + /* reset all acceration engine INT status bits */ + ACCW(ACC_INTS, 0xffffffff); + if (si->ps.card_arch != NV04A) + { + /* context control enabled */ + ACCW(NV10_CTX_CTRL, 0x10010100); + /* all acceleration buffers, pitches and colors are valid */ + ACCW(NV10_ACC_STAT, 0xffffffff); + } + else + { + /* context control enabled */ + ACCW(NV04_CTX_CTRL, 0x10010100); + /* all acceleration buffers, pitches and colors are valid */ + ACCW(NV04_ACC_STAT, 0xffffffff); + } + /* enable acceleration engine command FIFO */ + ACCW(FIFO_EN, 0x00000001); + /* pattern shape value = 8x8, 2 color */ + ACCW(PAT_SHP, 0x00000000); + if (si->ps.card_arch != NV04A) + { + /* surface type is non-swizzle */ + ACCW(NV10_SURF_TYP, 0x00000001); + } + else + { + /* surface type is non-swizzle */ + ACCW(NV04_SURF_TYP, 0x00000001); + } + + /*** Set pixel width and format ***/ switch(si->dm.space) { case B_CMAP8: - ACCW(MACCESS, ((maccess & 0xfffffffc) | 0x00)); - depth = 8; + /* acc engine */ + ACCW(FORMATS, 0x00001010); + if (si->ps.card_arch < NV30A) + ACCW(BPIXEL, 0x00111111); /* set depth 0-5: 4 bits per color */ + else + ACCW(BPIXEL, 0x00000021); /* set depth 0-1: 5 bits per color */ + ACCW(STRD_FMT, 0x03020202); + /* PRAMIN */ + ACCW(PR_CTX1_0, 0x00000302); /* format is X24Y8, LSB mono */ + ACCW(PR_CTX1_1, 0x00000302); /* format is X24Y8, LSB mono */ + ACCW(PR_CTX1_2, 0x00000202); /* format is X16A8Y8, LSB mono */ + ACCW(PR_CTX1_3, 0x00000302); /* format is X24Y8, LSB mono */ + ACCW(PR_CTX1_4, 0x00000302); /* format is X24Y8, LSB mono */ + ACCW(PR_CTX1_5, 0x00000302); /* format is X24Y8, LSB mono */ + ACCW(PR_CTX1_9, 0x00000302); /* format is X24Y8, LSB mono */ + ACCW(PR_CTX2_9, 0x00000302); /* dma_instance 0 valid, instance 1 invalid */ + ACCW(PR_CTX1_B, 0x00000000); /* format is invalid */ + ACCW(PR_CTX1_C, 0x00000000); /* format is invalid */ + if (si->ps.card_arch == NV04A) + { + ACCW(PR_CTX1_D, 0x00000302); /* format is X24Y8, LSB mono */ + } + else + { + ACCW(PR_CTX1_D, 0x00000000); /* format is invalid */ + ACCW(PR_CTX1_E, 0x00000302); /* format is X24Y8, LSB mono */ + } break; - case B_RGB15_LITTLE:case B_RGB16_LITTLE: - ACCW(MACCESS, ((maccess & 0xfffffffc) | 0x01)); - depth = 16; + case B_RGB15_LITTLE: + /* acc engine */ + ACCW(FORMATS, 0x00002071); + if (si->ps.card_arch < NV30A) + ACCW(BPIXEL, 0x00226222); /* set depth 0-5: 4 bits per color */ + else + ACCW(BPIXEL, 0x00000042); /* set depth 0-1: 5 bits per color */ + ACCW(STRD_FMT, 0x09080808); + /* PRAMIN */ + ACCW(PR_CTX1_0, 0x00000902); /* format is X17RGB15, LSB mono */ + ACCW(PR_CTX1_1, 0x00000902); /* format is X17RGB15, LSB mono */ + ACCW(PR_CTX1_2, 0x00000802); /* format is X16A1RGB15, LSB mono */ + ACCW(PR_CTX1_3, 0x00000902); /* format is X17RGB15, LSB mono */ + ACCW(PR_CTX1_4, 0x00000902); /* format is X17RGB15, LSB mono */ + ACCW(PR_CTX1_5, 0x00000902); /* format is X17RGB15, LSB mono */ + ACCW(PR_CTX1_9, 0x00000902); /* format is X17RGB15, LSB mono */ + ACCW(PR_CTX2_9, 0x00000902); /* dma_instance 0 valid, instance 1 invalid */ + if (si->ps.card_arch == NV04A) + { + ACCW(PR_CTX1_B, 0x00000702); /* format is X1RGB15, LSB mono */ + ACCW(PR_CTX1_C, 0x00000702); /* format is X1RGB15, LSB mono */ + } + else + { + ACCW(PR_CTX1_B, 0x00000902); /* format is X17RGB15, LSB mono */ + ACCW(PR_CTX1_C, 0x00000902); /* format is X17RGB15, LSB mono */ + ACCW(PR_CTX1_E, 0x00000902); /* format is X17RGB15, LSB mono */ + } + ACCW(PR_CTX1_D, 0x00000902); /* format is X17RGB15, LSB mono */ + break; + case B_RGB16_LITTLE: + /* acc engine */ + ACCW(FORMATS, 0x000050C2); + if (si->ps.card_arch < NV30A) + ACCW(BPIXEL, 0x00556555); /* set depth 0-5: 4 bits per color */ + else + ACCW(BPIXEL, 0x000000a5); /* set depth 0-1: 5 bits per color */ + if (si->ps.card_arch == NV04A) + ACCW(STRD_FMT, 0x0c0b0b0b); + else + ACCW(STRD_FMT, 0x000b0b0c); + /* PRAMIN */ + ACCW(PR_CTX1_0, 0x00000c02); /* format is X16RGB16, LSB mono */ + ACCW(PR_CTX1_1, 0x00000c02); /* format is X16RGB16, LSB mono */ + ACCW(PR_CTX1_2, 0x00000b02); /* format is A16RGB16, LSB mono */ + ACCW(PR_CTX1_3, 0x00000c02); /* format is X16RGB16, LSB mono */ + ACCW(PR_CTX1_4, 0x00000c02); /* format is X16RGB16, LSB mono */ + ACCW(PR_CTX1_5, 0x00000c02); /* format is X16RGB16, LSB mono */ + ACCW(PR_CTX1_9, 0x00000c02); /* format is X16RGB16, LSB mono */ + ACCW(PR_CTX2_9, 0x00000c02); /* dma_instance 0 valid, instance 1 invalid */ + if (si->ps.card_arch == NV04A) + { + ACCW(PR_CTX1_B, 0x00000702); /* format is X1RGB15, LSB mono */ + ACCW(PR_CTX1_C, 0x00000702); /* format is X1RGB15, LSB mono */ + } + else + { + ACCW(PR_CTX1_B, 0x00000c02); /* format is X16RGB16, LSB mono */ + ACCW(PR_CTX1_C, 0x00000c02); /* format is X16RGB16, LSB mono */ + ACCW(PR_CTX1_E, 0x00000c02); /* format is X16RGB16, LSB mono */ + } + ACCW(PR_CTX1_D, 0x00000c02); /* format is X16RGB16, LSB mono */ break; case B_RGB32_LITTLE:case B_RGBA32_LITTLE: - ACCW(MACCESS, ((maccess & 0xfffffffc) | 0x02)); - depth = 32; + /* acc engine */ + ACCW(FORMATS, 0x000070e5); + if (si->ps.card_arch < NV30A) + ACCW(BPIXEL, 0x0077d777); /* set depth 0-5: 4 bits per color */ + else + ACCW(BPIXEL, 0x000000e7); /* set depth 0-1: 5 bits per color */ + ACCW(STRD_FMT, 0x0e0d0d0d); + /* PRAMIN */ + ACCW(PR_CTX1_0, 0x00000e02); /* format is X8RGB24, LSB mono */ + ACCW(PR_CTX1_1, 0x00000e02); /* format is X8RGB24, LSB mono */ + ACCW(PR_CTX1_2, 0x00000d02); /* format is A8RGB24, LSB mono */ + ACCW(PR_CTX1_3, 0x00000e02); /* format is X8RGB24, LSB mono */ + ACCW(PR_CTX1_4, 0x00000e02); /* format is X8RGB24, LSB mono */ + ACCW(PR_CTX1_5, 0x00000e02); /* format is X8RGB24, LSB mono */ + ACCW(PR_CTX1_9, 0x00000e02); /* format is X8RGB24, LSB mono */ + ACCW(PR_CTX2_9, 0x00000e02); /* dma_instance 0 valid, instance 1 invalid */ + ACCW(PR_CTX1_B, 0x00000e02); /* format is X8RGB24, LSB mono */ + ACCW(PR_CTX1_C, 0x00000e02); /* format is X8RGB24, LSB mono */ + ACCW(PR_CTX1_D, 0x00000e02); /* format is X8RGB24, LSB mono */ + if (si->ps.card_arch >= NV10A) + ACCW(PR_CTX1_E, 0x00000e02); /* format is X8RGB24, LSB mono */ break; default: LOG(8,("ACC: init, invalid bit depth\n")); return B_ERROR; } - /* setup PITCH: very cardtype specific! */ -/* switch (si->ps.card_type) + /* setup some extra stuff for NV30A */ + if (si->ps.card_arch == NV30A) { - case MIL1: - switch (si->fbc.bytes_per_row / (depth >> 3)) - { - case 640: - case 768: - case 800: - case 960: - case 1024: - case 1152: - case 1280: - case 1600: - case 1920: - case 2048: -*/ /* we are using hardware adress linearisation */ -/* break; - default: -*/ /* we are using software adress linearisation */ -/* y_lin = 0x01; - LOG(8,("ACC: using software adress linearisation\n")); - break; - } - ACCW(PITCH, (y_lin << 15) | ((si->fbc.bytes_per_row / (depth >> 3)) & 0x0FFF)); - break; - case MIL2: - switch (si->fbc.bytes_per_row / (depth >> 3)) - { - case 512: - case 640: - case 768: - case 800: - case 832: - case 960: - case 1024: - case 1152: - case 1280: - case 1600: - case 1664: - case 1920: - case 2048: -*/ /* we are using hardware adress linearisation */ -/* break; - default: -*/ /* we are using software adress linearisation */ -/* y_lin = 0x01; - LOG(8,("ACC: using software adress linearisation\n")); - break; - } - ACCW(PITCH, (y_lin << 15) | ((si->fbc.bytes_per_row / (depth >> 3)) & 0x0FFF)); - break; - case G100: -*/ /* always using hardware adress linearisation, because 2D/3D - * engine works on every pitch multiple of 32 */ -/* ACCW(PITCH, ((si->fbc.bytes_per_row / (depth >> 3)) & 0x0FFF)); - break; - default: -*/ /* G200 and up are equal.. */ - /* always using hardware adress linearisation, because 2D/3D - * engine works on every pitch multiple of 32 */ -/* ACCW(PITCH, ((si->fbc.bytes_per_row / (depth >> 3)) & 0x1FFF)); - break; +/* + fixme: Does not belong here (and not needed?) + if(!chip->flatPanel) + { + chip->PRAMDAC0[0x0578/4] = state->vpllB; //0x00680578 = ??? never modified! + chip->PRAMDAC0[0x057C/4] = state->vpll2B; //0x0068057c = ??? never modified! } */ - /* disable plane write mask (needed for SDRAM): actual change needed to get it sent to RAM */ - ACCW(PLNWT,0x00000000); - ACCW(PLNWT,0xffffffff); -// if (si->ps.card_type >= G200) { - /*DSTORG - location of active screen in framebuffer*/ -// ACCW(DSTORG,(si->fbc.frame_buffer)-(si->framebuffer)); - - /*SRCORG - init source address - same as dest*/ -// ACCW(SRCORG,(si->fbc.frame_buffer)-(si->framebuffer)); -// } - - /* init YDSTORG - apsed, if not inited, BitBlts may fails on <= G200 */ - src_dst = 0; - ACCW(YDSTORG, src_dst); - - /* <= G100 uses this register as SRCORG/DSTORG replacement, but - * MIL 1/2 does not need framebuffer space for the hardcursor! */ -/* if ((si->ps.card_type == G100) && (si->settings.hardcursor)) - { - switch (si->dm.space) - { - case B_CMAP8: - src_dst = 1024 / 1; - break; - case B_RGB15_LITTLE: - case B_RGB16_LITTLE: - src_dst = 1024 / 2; - break; - case B_RGB32_LITTLE: - src_dst = 1024 / 4; - break; - default: - LOG(8,("ACC: G100 hardcursor not supported for current colorspace\n")); - return B_ERROR; - } + /* activate Zcullflush(?) */ + ACCW(DEBUG3, (ACCR(DEBUG3) | 0x00000001)); + /* unknown */ + ACCW(NV30_WHAT, (ACCR(NV30_WHAT) | 0x00040000)); } -*/ ACCW(YDSTORG,src_dst); - /* clipping */ - /* i.e. highest and lowest X pixel adresses */ - ACCW(CXBNDRY,(((si->fbc.bytes_per_row / (depth >> 3)) - 1) << 16) | (0)); + /*** setup screen location and pitch ***/ + switch (si->ps.card_arch) + { + case NV04A: + case NV10A: + /* location of active screen in framebuffer */ + ACCW(OFFSET0, (si->fbc.frame_buffer - si->framebuffer)); + ACCW(OFFSET1, (si->fbc.frame_buffer - si->framebuffer)); + ACCW(OFFSET2, (si->fbc.frame_buffer - si->framebuffer)); + ACCW(OFFSET3, (si->fbc.frame_buffer - si->framebuffer)); + ACCW(OFFSET4, (si->fbc.frame_buffer - si->framebuffer)); + ACCW(OFFSET5, (si->fbc.frame_buffer - si->framebuffer)); - /* Y pixel addresses must be linear */ - /* lowest adress */ - ACCW(YTOP, 0 + src_dst); - /* highest adress */ - ACCW(YBOT,((si->dm.virtual_height - 1) * - (si->fbc.bytes_per_row / (depth >> 3))) + src_dst); + /* setup buffer pitch */ + ACCW(PITCH0, (si->fbc.bytes_per_row & 0x0000ffff)); + ACCW(PITCH1, (si->fbc.bytes_per_row & 0x0000ffff)); + ACCW(PITCH2, (si->fbc.bytes_per_row & 0x0000ffff)); + ACCW(PITCH3, (si->fbc.bytes_per_row & 0x0000ffff)); + ACCW(PITCH4, (si->fbc.bytes_per_row & 0x0000ffff)); + break; + case NV20A: + case NV30A: + /* location of active screen in framebuffer */ + ACCW(NV20_OFFSET0, (si->fbc.frame_buffer - si->framebuffer)); + ACCW(NV20_OFFSET1, (si->fbc.frame_buffer - si->framebuffer)); + ACCW(NV20_OFFSET2, (si->fbc.frame_buffer - si->framebuffer)); + ACCW(NV20_OFFSET3, (si->fbc.frame_buffer - si->framebuffer)); + + /* setup buffer pitch */ + ACCW(NV20_PITCH0, (si->fbc.bytes_per_row & 0x0000ffff)); + ACCW(NV20_PITCH1, (si->fbc.bytes_per_row & 0x0000ffff)); + ACCW(NV20_PITCH2, (si->fbc.bytes_per_row & 0x0000ffff)); + ACCW(NV20_PITCH3, (si->fbc.bytes_per_row & 0x0000ffff)); + break; + } + + /*** setup tile and pipe stuff ***/ + if (si->ps.card_arch >= NV10A) + { +/* + fixme: setup elsewhere (does not belong here): + chip->PRAMDAC[0x00000404/4] |= (1 << 25);//0x00680404 = ??? +*/ + + /* setup acc engine tile stuff: */ + /* reset tile adresses */ + ACCW(NV10_FBTIL0AD, 0); + ACCW(NV10_FBTIL1AD, 0); + ACCW(NV10_FBTIL2AD, 0); + ACCW(NV10_FBTIL3AD, 0); + ACCW(NV10_FBTIL4AD, 0); + ACCW(NV10_FBTIL5AD, 0); + ACCW(NV10_FBTIL6AD, 0); + ACCW(NV10_FBTIL7AD, 0); + /* copy tile setup stuff from 'source' to acc engine */ + if (si->ps.card_arch >= NV20A) + { + /* unknown: */ + ACCW(NV20_WHAT0, ACCR(NV20_FBWHAT0)); + ACCW(NV20_WHAT1, ACCR(NV20_FBWHAT1)); + } + /* tile 0: */ + /* tile invalid, tile adress = $00000 (18bit) */ + ACCW(NV10_TIL0AD, ACCR(NV10_FBTIL0AD)); + /* set tile end adress (18bit) */ + ACCW(NV10_TIL0ED, ACCR(NV10_FBTIL0ED)); + /* set tile size pitch (8bit: b8-15) */ + ACCW(NV10_TIL0PT, ACCR(NV10_FBTIL0PT)); + /* set tile status */ + ACCW(NV10_TIL0ST, ACCR(NV10_FBTIL0ST)); + /* tile 1: */ + ACCW(NV10_TIL1AD, ACCR(NV10_FBTIL1AD)); + ACCW(NV10_TIL1ED, ACCR(NV10_FBTIL1ED)); + ACCW(NV10_TIL1PT, ACCR(NV10_FBTIL1PT)); + ACCW(NV10_TIL1ST, ACCR(NV10_FBTIL1ST)); + /* tile 2: */ + ACCW(NV10_TIL2AD, ACCR(NV10_FBTIL2AD)); + ACCW(NV10_TIL2ED, ACCR(NV10_FBTIL2ED)); + ACCW(NV10_TIL2PT, ACCR(NV10_FBTIL2PT)); + ACCW(NV10_TIL2ST, ACCR(NV10_FBTIL2ST)); + /* tile 3: */ + ACCW(NV10_TIL3AD, ACCR(NV10_FBTIL3AD)); + ACCW(NV10_TIL3ED, ACCR(NV10_FBTIL3ED)); + ACCW(NV10_TIL3PT, ACCR(NV10_FBTIL3PT)); + ACCW(NV10_TIL3ST, ACCR(NV10_FBTIL3ST)); + /* tile 4: */ + ACCW(NV10_TIL4AD, ACCR(NV10_FBTIL4AD)); + ACCW(NV10_TIL4ED, ACCR(NV10_FBTIL4ED)); + ACCW(NV10_TIL4PT, ACCR(NV10_FBTIL4PT)); + ACCW(NV10_TIL4ST, ACCR(NV10_FBTIL4ST)); + /* tile 5: */ + ACCW(NV10_TIL5AD, ACCR(NV10_FBTIL5AD)); + ACCW(NV10_TIL5ED, ACCR(NV10_FBTIL5ED)); + ACCW(NV10_TIL5PT, ACCR(NV10_FBTIL5PT)); + ACCW(NV10_TIL5ST, ACCR(NV10_FBTIL5ST)); + /* tile 6: */ + ACCW(NV10_TIL6AD, ACCR(NV10_FBTIL6AD)); + ACCW(NV10_TIL6ED, ACCR(NV10_FBTIL6ED)); + ACCW(NV10_TIL6PT, ACCR(NV10_FBTIL6PT)); + ACCW(NV10_TIL6ST, ACCR(NV10_FBTIL6ST)); + /* tile 7: */ + ACCW(NV10_TIL7AD, ACCR(NV10_FBTIL7AD)); + ACCW(NV10_TIL7ED, ACCR(NV10_FBTIL7ED)); + ACCW(NV10_TIL7PT, ACCR(NV10_FBTIL7PT)); + ACCW(NV10_TIL7ST, ACCR(NV10_FBTIL7ST)); + + /* setup pipe */ + /* set eyetype to local, lightning is off */ + ACCW(NV10_XFMOD0, 0x10000000); + /* disable all lights */ + ACCW(NV10_XFMOD1, 0x00000000); + + ACCW(NV10_PIPEADR, 0x00000040); + ACCW(NV10_PIPEDAT, 0x00000008); + + ACCW(NV10_PIPEADR, 0x00000200); + for (cnt = 0; cnt < (3 * 16); cnt++) ACCW(NV10_PIPEDAT, 0x00000000); + + ACCW(NV10_PIPEADR, 0x00000040); + ACCW(NV10_PIPEDAT, 0x00000000); + + ACCW(NV10_PIPEADR, 0x00000800); + for (cnt = 0; cnt < (16 * 16); cnt++) ACCW(NV10_PIPEDAT, 0x00000000); + + /* turn lightning on */ + ACCW(NV10_XFMOD0, 0x30000000); + /* set light 1 to infinite type, other lights remain off */ + ACCW(NV10_XFMOD1, 0x00000004); + + ACCW(NV10_PIPEADR, 0x00006400); + for (cnt = 0; cnt < (59 * 4); cnt++) ACCW(NV10_PIPEDAT, 0x00000000); + + ACCW(NV10_PIPEADR, 0x00006800); + for (cnt = 0; cnt < (47 * 4); cnt++) ACCW(NV10_PIPEDAT, 0x00000000); + + ACCW(NV10_PIPEADR, 0x00006c00); + for (cnt = 0; cnt < (3 * 4); cnt++) ACCW(NV10_PIPEDAT, 0x00000000); + + ACCW(NV10_PIPEADR, 0x00007000); + for (cnt = 0; cnt < (19 * 4); cnt++) ACCW(NV10_PIPEDAT, 0x00000000); + + ACCW(NV10_PIPEADR, 0x00007400); + for (cnt = 0; cnt < (12 * 4); cnt++) ACCW(NV10_PIPEDAT, 0x00000000); + + ACCW(NV10_PIPEADR, 0x00007800); + for (cnt = 0; cnt < (12 * 4); cnt++) ACCW(NV10_PIPEDAT, 0x00000000); + + ACCW(NV10_PIPEADR, 0x00004400); + for (cnt = 0; cnt < (8 * 4); cnt++) ACCW(NV10_PIPEDAT, 0x00000000); + + ACCW(NV10_PIPEADR, 0x00000000); + for (cnt = 0; cnt < 16; cnt++) ACCW(NV10_PIPEDAT, 0x00000000); + + ACCW(NV10_PIPEADR, 0x00000040); + for (cnt = 0; cnt < 4; cnt++) ACCW(NV10_PIPEDAT, 0x00000000); + } + + /*** setup acceleration engine command shortcuts (so via fifo) ***/ + /* (b31 = 1 selects 'config' function?) */ + ACCW(FIFO_00800000, 0x80000000); /* Raster OPeration */ + ACCW(FIFO_00802000, 0x80000001); /* Clip */ + ACCW(FIFO_00804000, 0x80000002); /* Pattern */ + ACCW(FIFO_00806000, 0x80000010); /* Pixmap (not used) */ + ACCW(FIFO_00808000, 0x80000011); /* Blit */ + ACCW(FIFO_0080a000, 0x80000012); /* Bitmap */ + ACCW(FIFO_0080c000, 0x80000016); /* Line (not used) */ + ACCW(FIFO_0080e000, 0x80000014); /* ??? (not used) */ + + /* do first actual acceleration engine command: + * setup clipping region (workspace size) to 32768 x 32768 pixels: + * wait for room in fifo for clipping cmd if needed. + * (fifo holds 256 32bit words: count those, not bytes) */ + while (((NV_REG16(NV16_CLP_FIFOFREE)) >> 2) < 2) + { + /* snooze a bit so I do not hammer the bus */ + snooze (10); + } + /* now setup clipping (writing 2 32bit words) */ + ACCW(CLP_TOPLEFT, 0x00000000); + ACCW(CLP_WIDHEIGHT, 0x80008000); + + return B_OK; +} + +/* screen to screen blit - i.e. move windows around and scroll within them. */ +status_t nv_acc_setup_blit() +{ + /* setup solid pattern: + * wait for room in fifo for pattern cmd if needed. + * (fifo holds 256 32bit words: count those, not bytes) */ + while (((NV_REG16(NV16_PAT_FIFOFREE)) >> 2) < 5) + { + /* snooze a bit so I do not hammer the bus */ + snooze (10); + } + /* now setup pattern (writing 5 32bit words) */ + ACCW(PAT_SHAPE, 0); /* 0 = 8x8, 1 = 64x1, 2 = 1x64 */ + ACCW(PAT_COLOR0, 0xffffffff); + ACCW(PAT_COLOR1, 0xffffffff); + ACCW(PAT_MONO1, 0xffffffff); + ACCW(PAT_MONO2, 0xffffffff); + + /* ROP3 registers (Raster OPeration): + * wait for room in fifo for ROP cmd if needed. + * (fifo holds 256 32bit words: count those, not bytes) */ + while (((NV_REG16(NV16_ROP_FIFOFREE)) >> 2) < 1) + { + /* snooze a bit so I do not hammer the bus */ + snooze (10); + } + /* now setup ROP (writing 1 32bit word) */ + ACCW(ROP_ROP3, 0xcc); return B_OK; } -/* screen to screen blit - i.e. move windows around. - * Engine function bitblit, paragraph 4.5.7.2 */ status_t nv_acc_blit(uint16 xs,uint16 ys,uint16 xd,uint16 yd,uint16 w,uint16 h) { - uint32 t_start,t_end,offset; - uint32 b_start,b_end; + /* Note: blit-copy direction is determined inside riva hardware: no setup needed */ - /*find where the top,bottom and offset are*/ - offset = (si->fbc.bytes_per_row / (depth >> 3)); - - t_end = t_start = xs + (offset*ys) + src_dst; - t_end += w; - - b_end = b_start = xs + (offset*(ys+h)) + src_dst; - b_end +=w; - - /* sgnzero bit _must_ be '0' before accessing SGN! */ - ACCW(DWGCTL,0x00000000); - - /*find which quadrant */ - switch((yd>ys)|((xd>xs)<<1)) + /* instruct engine what to blit: + * wait for room in fifo for blit cmd if needed. + * (fifo holds 256 32bit words: count those, not bytes) */ + while (((NV_REG16(NV16_BLT_FIFOFREE)) >> 2) < 3) { - case 0: /*L->R,down*/ - ACCW(SGN,0); - - ACCW(AR3,t_start); - ACCW(AR0,t_end); - ACCW(AR5,offset); - - ACCW_YDSTLEN(yd,h+1); - break; - case 1: /*L->R,up*/ - ACCW(SGN,4); - - ACCW(AR3,b_start); - ACCW(AR0,b_end); - ACCW(AR5,-offset); - - ACCW_YDSTLEN(yd+h,h+1); - break; - case 2: /*R->L,down*/ - ACCW(SGN,1); - - ACCW(AR3,t_end); - ACCW(AR0,t_start); - ACCW(AR5,offset); - - ACCW_YDSTLEN(yd,h+1); - break; - case 3: /*R->L,up*/ - ACCW(SGN,5); - - ACCW(AR3,b_end); - ACCW(AR0,b_start); - ACCW(AR5,-offset); - - ACCW_YDSTLEN(yd+h,h+1); - break; + /* snooze a bit so I do not hammer the bus */ + snooze (10); } - ACCW(FXBNDRY,((xd+w)<<16)|xd); - - /*do the blit*/ - ACCGO(DWGCTL,0x040C4018); // atype RSTR + /* now setup blit (writing 3 32bit words) */ + ACCW(BLT_TOPLFTSRC, ((ys << 16) | xs)); + ACCW(BLT_TOPLFTDST, ((yd << 16) | xd)); + ACCW(BLT_SIZE, (((h + 1) << 16) | (w + 1))); return B_OK; } -/* screen to screen tranparent blit - not sure what uses this. - * Engine function bitblit, paragraph 4.5.7.2 */ +/* rectangle fill - i.e. workspace and window background color */ +/* span fill - i.e. (selected) menuitem background color (Dano) */ +status_t nv_acc_setup_rectangle(uint32 color) +{ + /* setup solid pattern: + * wait for room in fifo for pattern cmd if needed. + * (fifo holds 256 32bit words: count those, not bytes) */ + while (((NV_REG16(NV16_PAT_FIFOFREE)) >> 2) < 5) + { + /* snooze a bit so I do not hammer the bus */ + snooze (10); + } + /* now setup pattern (writing 5 32bit words) */ + ACCW(PAT_SHAPE, 0); /* 0 = 8x8, 1 = 64x1, 2 = 1x64 */ + ACCW(PAT_COLOR0, 0xffffffff); + ACCW(PAT_COLOR1, 0xffffffff); + ACCW(PAT_MONO1, 0xffffffff); + ACCW(PAT_MONO2, 0xffffffff); + + /* ROP3 registers (Raster OPeration): + * wait for room in fifo for ROP cmd if needed. + * (fifo holds 256 32bit words: count those, not bytes) */ + while (((NV_REG16(NV16_ROP_FIFOFREE)) >> 2) < 1) + { + /* snooze a bit so I do not hammer the bus */ + snooze (10); + } + /* now setup ROP (writing 1 32bit word) for GXcopy */ + ACCW(ROP_ROP3, 0xcc); + + /* setup fill color: + * wait for room in fifo for bitmap cmd if needed. + * (fifo holds 256 32bit words: count those, not bytes) */ + while (((NV_REG16(NV16_BMP_FIFOFREE)) >> 2) < 1) + { + /* snooze a bit so I do not hammer the bus */ + snooze (10); + } + /* now setup color (writing 1 32bit word) */ + ACCW(BMP_COLOR1A, color); + + return B_OK; +} + +status_t nv_acc_rectangle(uint32 xs,uint32 xe,uint32 ys,uint32 yl) +{ + /* instruct engine what to fill: + * wait for room in fifo for bitmap cmd if needed. + * (fifo holds 256 32bit words: count those, not bytes) */ + while (((NV_REG16(NV16_BMP_FIFOFREE)) >> 2) < 2) + { + /* snooze a bit so I do not hammer the bus */ + snooze (10); + } + /* now setup fill (writing 2 32bit words) */ + ACCW(BMP_UCRECTL_0, ((xs << 16) | (ys & 0x0000ffff))); + ACCW(BMP_UCRECSZ_0, (((xe - xs) << 16) | (yl & 0x0000ffff))); + + return B_OK; +} + +/* rectangle invert - i.e. text cursor and text selection */ +status_t nv_acc_setup_rect_invert() +{ + /* setup solid pattern: + * wait for room in fifo for pattern cmd if needed. + * (fifo holds 256 32bit words: count those, not bytes) */ + while (((NV_REG16(NV16_PAT_FIFOFREE)) >> 2) < 5) + { + /* snooze a bit so I do not hammer the bus */ + snooze (10); + } + /* now setup pattern (writing 5 32bit words) */ + ACCW(PAT_SHAPE, 0); /* 0 = 8x8, 1 = 64x1, 2 = 1x64 */ + ACCW(PAT_COLOR0, 0xffffffff); + ACCW(PAT_COLOR1, 0xffffffff); + ACCW(PAT_MONO1, 0xffffffff); + ACCW(PAT_MONO2, 0xffffffff); + + /* ROP3 registers (Raster OPeration): + * wait for room in fifo for ROP cmd if needed. + * (fifo holds 256 32bit words: count those, not bytes) */ + while (((NV_REG16(NV16_ROP_FIFOFREE)) >> 2) < 1) + { + /* snooze a bit so I do not hammer the bus */ + snooze (10); + } + /* now setup ROP (writing 1 32bit word) for GXinvert */ + ACCW(ROP_ROP3, 0x55); + + /* reset fill color: + * wait for room in fifo for bitmap cmd if needed. + * (fifo holds 256 32bit words: count those, not bytes) */ + while (((NV_REG16(NV16_BMP_FIFOFREE)) >> 2) < 1) + { + /* snooze a bit so I do not hammer the bus */ + snooze (10); + } + /* now reset color (writing 1 32bit word) */ + ACCW(BMP_COLOR1A, 0); + + return B_OK; +} + +status_t nv_acc_rectangle_invert(uint32 xs,uint32 xe,uint32 ys,uint32 yl) +{ + /* instruct engine what to invert: + * wait for room in fifo for bitmap cmd if needed. + * (fifo holds 256 32bit words: count those, not bytes) */ + while (((NV_REG16(NV16_BMP_FIFOFREE)) >> 2) < 2) + { + /* snooze a bit so I do not hammer the bus */ + snooze (10); + } + /* now setup invert (writing 2 32bit words) */ + ACCW(BMP_UCRECTL_0, ((xs << 16) | (ys & 0x0000ffff))); + ACCW(BMP_UCRECSZ_0, (((xe - xs) << 16) | (yl & 0x0000ffff))); + + return B_OK; +} + +/* screen to screen tranparent blit */ status_t nv_acc_transparent_blit(uint16 xs,uint16 ys,uint16 xd,uint16 yd,uint16 w,uint16 h,uint32 colour) { - uint32 t_start,t_end,offset; - uint32 b_start,b_end; + //fixme: implement. return B_ERROR; - - /*find where the top,bottom and offset are*/ - offset = (si->fbc.bytes_per_row / (depth >> 3)); - - t_end = t_start = xs + (offset*ys) + src_dst; - t_end += w; - - b_end = b_start = xs + (offset*(ys+h)) + src_dst; - b_end +=w; - - /* sgnzero bit _must_ be '0' before accessing SGN! */ - ACCW(DWGCTL,0x00000000); - - /*find which quadrant */ - switch((yd>ys)|((xd>xs)<<1)) - { - case 0: /*L->R,down*/ - ACCW(SGN,0); - - ACCW(AR3,t_start); - ACCW(AR0,t_end); - ACCW(AR5,offset); - - ACCW_YDSTLEN(yd,h+1); - break; - case 1: /*L->R,up*/ - ACCW(SGN,4); - - ACCW(AR3,b_start); - ACCW(AR0,b_end); - ACCW(AR5,-offset); - - ACCW_YDSTLEN(yd+h,h+1); - break; - case 2: /*R->L,down*/ - ACCW(SGN,1); - - ACCW(AR3,t_end); - ACCW(AR0,t_start); - ACCW(AR5,offset); - - ACCW_YDSTLEN(yd,h+1); - break; - case 3: /*R->L,up*/ - ACCW(SGN,5); - - ACCW(AR3,b_end); - ACCW(AR0,b_start); - ACCW(AR5,-offset); - - ACCW_YDSTLEN(yd+h,h+1); - break; - } - ACCW(FXBNDRY,((xd+w)<<16)|xd); - - /*do the blit*/ - ACCW(FCOL,colour); - ACCW(BCOL,0xffffffff); - ACCGO(DWGCTL,0x440C4018); // atype RSTR - return B_OK; } -/* rectangle fill. - * Engine function rectangle_fill: paragraph 4.5.5.2 */ -/*colorIndex,fill_rect_params,count*/ -status_t nv_acc_rectangle(uint32 xs,uint32 xe,uint32 ys,uint32 yl,uint32 col) -{ -/* - FXBNDRY - left and right coordinates a - YDSTLEN - y start and no of lines a - (or YDST and LEN) - DWGCTL - atype must be RSTR or BLK a - FCOL - foreground colour a -*/ - - ACCW(FXBNDRY,(xe<<16)|xs); /*set x start and end*/ - ACCW_YDSTLEN(ys,yl); /*set y start and length*/ - ACCW(FCOL,col); /*set colour*/ - -//acc fixme: checkout blockmode constraints for G100+ (mil: nc?): also add blockmode -// for other functions, and use fastblt on MIL1/2 if possible... -//or is CMAP8 contraint a non-blockmode contraint? (linearisation problem maybe?) - if (si->dm.space==B_CMAP8 || si->ps.sdram) - { - ACCGO(DWGCTL,0x400C7814); // atype RSTR - } - else - { - ACCGO(DWGCTL,0x400C7844); // atype BLK - } - return B_OK; -} - -/* rectangle invert. - * Engine function rectangle_fill: paragraph 4.5.5.2 */ -/*colorIndex,fill_rect_params,count*/ -status_t nv_acc_rectangle_invert(uint32 xs,uint32 xe,uint32 ys,uint32 yl,uint32 col) -{ -// int i; -// uint32 * dma; -// uint32 pci; -/* - FXBNDRY - left and right coordinates a - YDSTLEN - y start and no of lines a - (or YDST and LEN) - DWGCTL - atype must be RSTR or BLK a - FCOL - foreground colour a -*/ - - ACCW(FXBNDRY,(xe<<16)|xs); /*set x start and end*/ - ACCW_YDSTLEN(ys,yl); /*set y start and length*/ - ACCW(FCOL,col); /*set colour*/ - - /*draw it! top nibble is c is clipping enabled*/ - ACCGO(DWGCTL,0x40057814); // atype RSTR - - /*pseudo_dma version!*/ -//NVACC_DWGCTL =0x1C00, -//NVACC_FCOL =0x1C24, -//NVACC_FXBNDRY =0x1C84, -//NVACC_YDSTLEN =0x1C88, -// -//40,09,21,22 (ordered as registers) - -// dma = (uint32 *)si->pseudo_dma; -// *dma++=0x40092221; -// *dma++=(xe<<16)|xs; -// *dma++=(ys<<16)|yl; -// *dma++=col; -// *dma++=0x40057814; - - /*real dma version!*/ -// dma = (vuint32 *)si->dma_buffer; -// *dma++=0x40092221;/*indices*/ -// *dma++=(xe<<16)|xs; -// *dma++=(ys<<16)|yl; -// *dma++=col; -// *dma++=0x40057814; - -// pci = si->dma_buffer_pci; -// ACCW(PRIMADDRESS,(pci)); -// ACCW(PRIMEND,(20+pci)); - -// delay(100); - - return B_OK; -} - -/* screen to screen scaled filtered blit - i.e. scale video in memory. - * Engine function texture mapping for video, paragraphs 4.5.5.5 - 4.5.5.9 */ +/* screen to screen scaled filtered blit - i.e. scale video in memory */ status_t nv_acc_video_blit(uint16 xs,uint16 ys,uint16 ws, uint16 hs, uint16 xd,uint16 yd,uint16 wd,uint16 hd) { - //fixme: implement. Used for G450/G550 Desktop TVout... - //fixme: see if MIL1 - G200 support this function as well... + //fixme: implement. - return B_OK; + return B_ERROR; } diff --git a/src/add-ons/accelerants/nvidia/engine/nv_bes.c b/src/add-ons/accelerants/nvidia/engine/nv_bes.c index 11c790fbf3..29da891b3d 100644 --- a/src/add-ons/accelerants/nvidia/engine/nv_bes.c +++ b/src/add-ons/accelerants/nvidia/engine/nv_bes.c @@ -1,5 +1,5 @@ /* Nvidia GeForce Back End Scaler functions */ -/* Written by Rudolf Cornelissen 05/2002-08/2003 */ +/* Written by Rudolf Cornelissen 05/2002-10/2003 */ #define MODULE_BIT 0x00000200 @@ -8,6 +8,24 @@ //fixme: implement: (used for virtual screens!) //void move_overlay(uint16 hdisp_start, uint16 vdisp_start); +status_t nv_bes_init() +{ + /* disable overlay ints (b0 = buffer 0, b4 = buffer 1) */ + BESW(NV10_INTE, 0x00000000); + /* shut off GeForce4MX MPEG2 decoder */ + BESW(DEC_GENCTRL, 0x00000000); + /* setup BES memory-range mask */ + BESW(NV10_0MEMMASK, ((si->ps.memory_size << 20) - 1)); + /* unknown, but needed */ + BESW(NV10_0WHAT, 0x00000000); + + /* setup brightness, contrast and saturation to be 'neutral' */ + BESW(NV10_0BRICON, ((0x1000 << 16) | 0x1000)); + BESW(NV10_0SAT, ((0x0000 << 16) | 0x1000)); + + return B_OK; +} + status_t nv_configure_bes (const overlay_buffer *ob, const overlay_window *ow, const overlay_view *ov, int offset) { @@ -441,25 +459,14 @@ status_t nv_configure_bes *** sync to BES (Back End Scaler) *** *************************************/ -//fixme if needed... (doesn't look like it) - /* Make sure reprogramming the BES completes before the next retrace occurs, - * to prevent register-update glitches (double buffer feature). */ - -// LOG(3,("Overlay: starting register programming beyond Vcount %d\n", CR1R(VCOUNT))); - /* Even at 1600x1200x90Hz, a single line still takes about 9uS to complete: - * this resolution will generate about 180Mhz pixelclock while we can do - * upto 360Mhz. So snooze about 4uS to prevent bus-congestion... - * Appr. 200 lines time will provide enough room even on a 100Mhz CPU if it's - * screen is set to the highest refreshrate/resolution possible. */ -// while (CR1R(VCOUNT) > (si->dm.timing.v_total - 200)) snooze(4); + /* Done in card hardware: + * double buffered registers + trigger if programming complete feature. */ /************************************** *** actually program the registers *** **************************************/ - /* shut off GeForce4MX MPEG2 decoder */ - BESW(DEC_GENCTRL, 0x00000000); /* We only use buffer buffer 0: select it. (0x01 = buffer 0, 0x10 = buffer 1) */ BESW(NV10_BUFSEL, 0x00000001); /* setup buffer origin: GeForce uses subpixel precise clipping on left and top! (12.4 values) */ @@ -478,10 +485,6 @@ status_t nv_configure_bes (((vcoordv & 0x0000ffff) - ((vcoordv & 0xffff0000) >> 16) + 1) << 16) | ((hcoordv & 0x0000ffff) - ((hcoordv & 0xffff0000) >> 16) + 1) )); - /* setup BES memory-range mask */ - BESW(NV10_0MEMMASK, ((si->ps.memory_size << 20) - 1)); - /* unknown, but needed */ - BESW(NV10_0WHAT, 0x00000000); /* setup horizontal scaling */ BESW(NV10_0ISCALH, (hiscalv << 4)); /* setup vertical scaling */ @@ -526,18 +529,6 @@ status_t nv_configure_bes break; } - /************************* - *** setup misc. stuff *** - *************************/ - - /* setup brightness, contrast and saturation to be 'neutral' */ - BESW(NV10_0BRICON, ((0x1000 << 16) | 0x1000)); - BESW(NV10_0SAT, ((0x0000 << 16) | 0x1000)); - - /* on a 500Mhz P3 CPU just logging a line costs 400uS (18-19 vcounts at 1024x768x60Hz)! - * programming the registers above actually costs 180uS here */ -// LOG(3,("Overlay: completed at Vcount %d\n", CR1R(VCOUNT))); - return B_OK; } diff --git a/src/add-ons/accelerants/nvidia/engine/nv_crtc.c b/src/add-ons/accelerants/nvidia/engine/nv_crtc.c index b8cec02378..6afb374c5f 100644 --- a/src/add-ons/accelerants/nvidia/engine/nv_crtc.c +++ b/src/add-ons/accelerants/nvidia/engine/nv_crtc.c @@ -1,6 +1,6 @@ /* CTRC functionality */ /* Author: - Rudolf Cornelissen 11/2002-8/2003 + Rudolf Cornelissen 11/2002-9/2003 */ #define MODULE_BIT 0x00040000 @@ -51,6 +51,7 @@ status_t nv_crtc_validate_timing( /*vertical*/ /* confine to required number of bits, taking logic into account */ + //fixme if needed: on GeForce cards there are 12 instead of 11 bits... if (*vd_e > (0x7ff - 2)) *vd_e = (0x7ff - 2); if (*vs_s > (0x7ff - 1)) *vs_s = (0x7ff - 1); if (*vs_e > 0x7ff ) *vs_e = 0x7ff ; @@ -184,6 +185,19 @@ status_t nv_crtc_set_timing(display_mode target) //| ((linecomp & 0x400) >> 3) )); + /* more vertical extended regs (on GeForce cards only) */ + if (si->ps.card_arch >= NV10A) + { + CRTCW(EXTRA, + ( + ((vtotal & 0x800) >> (11 - 0)) | + ((vdisp_e & 0x800) >> (11 - 2)) | + ((vsync_s & 0x800) >> (11 - 4)) | + ((vblnk_s & 0x800) >> (11 - 6)) + //fixme: do we miss another linecomp bit!?! + )); + } + /* setup 'large screen' mode */ if (target.timing.h_display >= 1280) CRTCW(REPAINT1, (CRTCR(REPAINT1) & 0xfb)); @@ -218,6 +232,10 @@ status_t nv_crtc_set_timing(display_mode target) LOG(2,(", MISC reg readback: $%02x\n", NV_REG8(NV8_MISCR))); } + /* always disable interlaced operation */ + /* (interlace is only supported on upto and including NV15 except for NV11) */ + CRTCW(INTERLACE, 0xff); + return B_OK; } diff --git a/src/add-ons/accelerants/nvidia/engine/nv_general.c b/src/add-ons/accelerants/nvidia/engine/nv_general.c index be004a0b49..03778b1096 100644 --- a/src/add-ons/accelerants/nvidia/engine/nv_general.c +++ b/src/add-ons/accelerants/nvidia/engine/nv_general.c @@ -1,7 +1,7 @@ /* Authors: Mark Watson 12/1999, Apsed, - Rudolf Cornelissen 10/2002-8/2003 + Rudolf Cornelissen 10/2002-10/2003 */ #define MODULE_BIT 0x00008000 @@ -81,7 +81,7 @@ status_t nv_general_powerup() { status_t status; - LOG(1,("POWERUP: nVidia (open)BeOS Accelerant 0.05 running.\n")); + LOG(1,("POWERUP: nVidia (open)BeOS Accelerant 0.06 running.\n")); /* preset no laptop */ si->ps.laptop = false; @@ -212,7 +212,13 @@ status_t nv_general_powerup() LOG(4,("POWERUP: Detected Nvidia Quadro4 500 GoGL (NV17)\n")); status = nvxx_general_powerup(); break; - //fixme: three IDs below correct?? + case 0x017d10de: /* Nvidia unknown 4 Go */ + si->ps.card_type = NV17; + si->ps.card_arch = NV10A; + si->ps.laptop = true; + LOG(4,("POWERUP: Detected Nvidia unknown 4 Go (NV17)\n")); + status = nvxx_general_powerup(); + break; case 0x018010de: /* Nvidia GeForce4 MX 440 AGP8X */ case 0x018110de: /* Nvidia GeForce4 MX 440SE AGP8X */ case 0x018210de: /* Nvidia GeForce4 MX 420 AGP8X */ @@ -221,6 +227,14 @@ status_t nv_general_powerup() LOG(4,("POWERUP: Detected Nvidia GeForce4 MX AGP8X (NV18)\n")); status = nvxx_general_powerup(); break; + case 0x018610de: /* Nvidia GeForce4 448 Go */ + case 0x018710de: /* Nvidia GeForce4 488 Go */ + si->ps.card_type = NV18; + si->ps.card_arch = NV10A; + si->ps.laptop = true; + LOG(4,("POWERUP: Detected Nvidia GeForce4 Go (NV18)\n")); + status = nvxx_general_powerup(); + break; case 0x018810de: /* Nvidia Quadro4 580 XGL */ case 0x018a10de: /* Nvidia Quadro4 280 NVS */ case 0x018b10de: /* Nvidia Quadro4 380 XGL */ @@ -298,6 +312,13 @@ status_t nv_general_powerup() LOG(4,("POWERUP: Detected Nvidia Quadro4 XGL (NV28)\n")); status = nvxx_general_powerup(); break; + case 0x028c10de: /* Nvidia unknown 4 Go */ + si->ps.card_type = NV28; + si->ps.card_arch = NV20A; + si->ps.laptop = true; + LOG(4,("POWERUP: Detected Nvidia unknown 4 Go (NV28)\n")); + status = nvxx_general_powerup(); + break; case 0x02a010de: /* Nvidia GeForce3 Integrated GPU */ si->ps.card_type = NV20; si->ps.card_arch = NV20A; @@ -325,6 +346,14 @@ status_t nv_general_powerup() LOG(4,("POWERUP: Detected Nvidia GeForce FX 5600 (NV31)\n")); status = nvxx_general_powerup(); break; + case 0x031610de: /* Nvidia unknown FX Go */ + case 0x031710de: /* Nvidia unknown FX Go */ + si->ps.card_type = NV31; + si->ps.card_arch = NV30A; + si->ps.laptop = true; + LOG(4,("POWERUP: Detected Nvidia unknown FX Go (NV31)\n")); + status = nvxx_general_powerup(); + break; case 0x031a10de: /* Nvidia GeForce FX 5600 Go */ si->ps.card_type = NV31; si->ps.card_arch = NV30A; @@ -332,6 +361,17 @@ status_t nv_general_powerup() LOG(4,("POWERUP: Detected Nvidia GeForce FX 5600 Go (NV31)\n")); status = nvxx_general_powerup(); break; + case 0x031b10de: /* Nvidia unknown FX Go */ + case 0x031c10de: /* Nvidia unknown FX Go */ + case 0x031d10de: /* Nvidia unknown FX Go */ + case 0x031e10de: /* Nvidia unknown FX Go */ + case 0x031f10de: /* Nvidia unknown FX Go */ + si->ps.card_type = NV31; + si->ps.card_arch = NV30A; + si->ps.laptop = true; + LOG(4,("POWERUP: Detected Nvidia unknown FX Go (NV31)\n")); + status = nvxx_general_powerup(); + break; case 0x032110de: /* Nvidia GeForce FX 5200 Ultra */ case 0x032210de: /* Nvidia GeForce FX 5200 */ si->ps.card_type = NV34; @@ -339,12 +379,33 @@ status_t nv_general_powerup() LOG(4,("POWERUP: Detected Nvidia GeForce FX 5200 (NV34)\n")); status = nvxx_general_powerup(); break; + case 0x032410de: /* Nvidia GeForce FX 5200 Go */ + si->ps.card_type = NV34; + si->ps.card_arch = NV30A; + si->ps.laptop = true; + LOG(4,("POWERUP: Detected Nvidia GeForce FX 5200 Go (NV34)\n")); + status = nvxx_general_powerup(); + break; + case 0x032610de: /* Nvidia unknown FX Go */ + si->ps.card_type = NV34; + si->ps.card_arch = NV30A; + si->ps.laptop = true; + LOG(4,("POWERUP: Detected Nvidia unknown FX Go (NV34)\n")); + status = nvxx_general_powerup(); + break; case 0x032b10de: /* Nvidia Quadro FX 500 */ si->ps.card_type = NV34; si->ps.card_arch = NV30A; LOG(4,("POWERUP: Detected Nvidia Quadro FX 500 (NV34)\n")); status = nvxx_general_powerup(); break; + case 0x032e10de: /* Nvidia unknown FX Go */ + si->ps.card_type = NV34; + si->ps.card_arch = NV30A; + si->ps.laptop = true; + LOG(4,("POWERUP: Detected Nvidia unknown FX Go (NV34)\n")); + status = nvxx_general_powerup(); + break; case 0x033010de: /* Nvidia GeForce FX 5900 Ultra */ case 0x033110de: /* Nvidia GeForce FX 5900 */ si->ps.card_type = NV35; @@ -718,14 +779,8 @@ status_t nv_general_dac_select(int dac) return B_OK; } -/*busy wait until retrace!*/ -status_t nv_general_wait_retrace() -{ -// while (!(ACCR(STATUS)&0x8)); - return B_OK; -} - -/* basic change of card state from VGA to powergraphics -> should work from BIOS init state*/ +/* basic change of card state from VGA to enhanced mode: + * Should work from VGA BIOS POST init state. */ static status_t nv_general_bios_to_powergraphics() { @@ -733,11 +788,16 @@ status_t nv_general_bios_to_powergraphics() /* unlock card registers for R/W access */ CRTCW(LOCK, 0x57); + CRTCW(VSYNCE ,(CRTCR(VSYNCE) & 0x7f)); /* turn off both displays and the hardcursor (also disables transfers) */ nv_crtc_dpms(false, false, false); nv_crtc_cursor_hide(); + /* let acc engine make power off/power on cycle to start 'fresh' */ + NV_REG32(NV32_PWRUPCTRL) = 0x13110011; + snooze(1000); + /* power-up all nvidia hardware function blocks */ /* bit 28: OVERLAY ENGINE (BES), * bit 25: CRTC2, (> NV04A) @@ -750,43 +810,13 @@ status_t nv_general_bios_to_powergraphics() * bit 0: TVOUT. (> NV04A) */ NV_REG32(NV32_PWRUPCTRL) = 0x13111111; - /* switch overlay engine to head 1 */ - //fixme: add other function blocks... - NV_REG32(NV32_FUNCSEL) |= 0x00001000; - NV_REG32(NV32_2FUNCSEL) &= ~0x00001000; - - /* set card to 'enhanced' mode: (only VGA standard registers used for NeoMagic cards) */ - /* (keep) card enabled, set plain normal memory usage, no old VGA 'tricks' ... */ -// CRTCW(MODECTL, 0xc3); - /* ... plain sequential memory use, more than 64Kb RAM installed, - * switch to graphics mode ... */ -// SEQW(MEMMODE, 0x0e); - /* ... disable bitplane tweaking ... */ -// GRPHW(ENSETRESET, 0x00); - /* ... no logical function tweaking with display data, no data rotation ... */ -// GRPHW(DATAROTATE, 0x00); - /* ... reset read map select to plane 0 ... */ -// GRPHW(READMAPSEL, 0x00); - /* ... set standard mode ... */ -// GRPHW(MODE, 0x00); - /* ... ISA framebuffer mapping is 64Kb window, switch to graphics mode (again), - * select standard adressing ... */ -// GRPHW(MISC, 0x05); - /* ... disable bit masking ... */ -// GRPHW(BITMASK, 0xff); - /* ... attributes are in color, switch to graphics mode (again) ... */ -// ATBW(MODECTL, 0x01); - /* ... set overscan color to black ... */ -// ATBW(OSCANCOLOR, 0x00); - /* ... enable all color planes ... */ -// ATBW(COLPLANE_EN, 0x0f); - /* ... reset horizontal pixelpanning ... */ -// ATBW(HORPIXPAN, 0x00); - /* ... and reset colorpalette groupselect bits. */ -// ATBW(COLSEL, 0x00); - - /* setup sequencer clocking mode */ -// SEQW(CLKMODE, 0x21); + if (si->ps.card_arch >= NV10A) + { + /* switch overlay engine to head 1 */ + //fixme: add other function blocks... + NV_REG32(NV32_FUNCSEL) |= 0x00001000; + NV_REG32(NV32_2FUNCSEL) &= ~0x00001000; + } /* enable 'enhanced mode', enable Vsync & Hsync, * set DAC palette to 8-bit width, disable large screen */ @@ -819,64 +849,46 @@ status_t nv_general_validate_pic_size (display_mode *target, uint32 *bytes_per_r uint8 depth = 8; /* determine pixel multiple based on 2D/3D engine constraints */ - switch (si->ps.card_type) + switch (si->ps.card_arch) { -// case MIL2: - /* see MIL1/2 specs: - * these cards always use a 64bit RAMDAC (TVP3026) and interleaved memory */ -/* switch (target->space) + case NV20A: + /* confirmed for: + * GeForce4 Ti4200 */ + switch (target->space) { - case B_CMAP8: acc_mask = 0x7f; depth = 8; break; - case B_RGB15: acc_mask = 0x3f; depth = 16; break; - case B_RGB16: acc_mask = 0x3f; depth = 16; break; - case B_RGB24: acc_mask = 0x7f; depth = 24; break; - case B_RGB32: acc_mask = 0x1f; depth = 32; break; + case B_CMAP8: acc_mask = 0x3f; depth = 8; break; + case B_RGB15: acc_mask = 0x1f; depth = 16; break; + case B_RGB16: acc_mask = 0x1f; depth = 16; break; + case B_RGB24: acc_mask = 0x3f; depth = 24; break; + case B_RGB32: acc_mask = 0x0f; depth = 32; break; default: LOG(8,("INIT: unknown color space: 0x%08x\n", target->space)); return B_ERROR; } break; -*/ default: - /* see G100 and up specs: - * these cards can do 2D as long as multiples of 32 are used. - * (Note: don't mix this up with adress linearisation!) */ + default: + /* confirmed for: + * TNT1, TNT2, TNT2-M64, GeForce2 MX400, GeForce4 MX440, GeForceFX 5200 */ switch (target->space) { - case B_CMAP8: depth = 8; break; - case B_RGB15: depth = 16; break; - case B_RGB16: depth = 16; break; - case B_RGB24: depth = 24; break; - case B_RGB32: depth = 32; break; + case B_CMAP8: acc_mask = 0x0f; depth = 8; break; + case B_RGB15: acc_mask = 0x07; depth = 16; break; + case B_RGB16: acc_mask = 0x07; depth = 16; break; + case B_RGB24: acc_mask = 0x0f; depth = 24; break; + case B_RGB32: acc_mask = 0x03; depth = 32; break; default: LOG(8,("INIT: unknown color space: 0x%08x\n", target->space)); return B_ERROR; } - acc_mask = 0x1f; break; } /* determine pixel multiple based on CRTC memory pitch constraints. * (Note: Don't mix this up with CRTC timing contraints! Those are * multiples of 8 for horizontal, 1 for vertical timing.) */ - switch (si->ps.card_type) + switch (si->ps.card_arch) { -// case MIL2: - /* see MIL1/2 specs: - * these cards always use a 64bit RAMDAC and interleaved memory */ -/* switch (target->space) - { - case B_CMAP8: crtc_mask = 0x7f; break; - case B_RGB15: crtc_mask = 0x3f; break; - case B_RGB16: crtc_mask = 0x3f; break; -*/ /* for B_RGB24 crtc_mask 0x7f is worst case scenario (MIL2 constraint) */ -/* case B_RGB24: crtc_mask = 0x7f; break; - case B_RGB32: crtc_mask = 0x1f; break; - default: - LOG(8,("INIT: unknown color space: 0x%08x\n", target->space)); - return B_ERROR; - } - break; -*/ default: + default: /* all NV cards */ switch (target->space) { @@ -889,10 +901,10 @@ status_t nv_general_validate_pic_size (display_mode *target, uint32 *bytes_per_r LOG(8,("INIT: unknown color space: 0x%08x\n", target->space)); return B_ERROR; } +//fixme for NV.. /* see G400 specs: CRTC2 has different constraints */ /* Note: * set for RGB and B_YCbCr422 modes. Other modes need larger multiples! */ -//fixme.. if (target->flags & DUALHEAD_BITS) { switch (target->space) @@ -904,6 +916,7 @@ status_t nv_general_validate_pic_size (display_mode *target, uint32 *bytes_per_r return B_ERROR; } } +//end fixme. break; } @@ -911,19 +924,73 @@ status_t nv_general_validate_pic_size (display_mode *target, uint32 *bytes_per_r * Max sizes need to adhere to both the acceleration engine _and_ the CRTC constraints! */ si->acc_mode = true; /* check virtual_width */ - switch (si->ps.card_type) + switch (si->ps.card_arch) { + case NV04A: + /* confirmed for: + * TNT1, TNT2, TNT2-M64 */ + switch(target->space) + { + case B_CMAP8: + if (target->virtual_width > 8176) si->acc_mode = false; + break; + case B_RGB15_LITTLE: + case B_RGB16_LITTLE: + if (target->virtual_width > 4088) si->acc_mode = false; + break; + case B_RGB24_LITTLE: + if (target->virtual_width > 2720) si->acc_mode = false; + break; + case B_RGB32_LITTLE: + if (target->virtual_width > 2044) si->acc_mode = false; + break; + } + break; + case NV20A: + /* confirmed for: + * GeForce4 Ti4200 */ + switch(target->space) + { + case B_CMAP8: + if (target->virtual_width > 16320) si->acc_mode = false; + break; + case B_RGB15_LITTLE: + case B_RGB16_LITTLE: + if (target->virtual_width > 8160) si->acc_mode = false; + break; + case B_RGB24_LITTLE: + if (target->virtual_width > 5440) si->acc_mode = false; + break; + case B_RGB32_LITTLE: + if (target->virtual_width > 4080) si->acc_mode = false; + break; + } + break; default: - /* G200-G550 */ - /* acc constraint: */ - if (target->virtual_width > 4096) si->acc_mode = false; - /* for 32bit mode a lower CRTC1 restriction applies! */ - if ((target->space == B_RGB32_LITTLE) && (target->virtual_width > (4092 & ~acc_mask))) - si->acc_mode = false; + /* confirmed for: + * GeForce2 MX400, GeForce4 MX440, GeForceFX 5200 */ + switch(target->space) + { + case B_CMAP8: + if (target->virtual_width > 16368) si->acc_mode = false; + break; + case B_RGB15_LITTLE: + case B_RGB16_LITTLE: + if (target->virtual_width > 8184) si->acc_mode = false; + break; + case B_RGB24_LITTLE: + if (target->virtual_width > 5456) si->acc_mode = false; + break; + case B_RGB32_LITTLE: + if (target->virtual_width > 4092) si->acc_mode = false; + break; + } break; } /* virtual_height */ - if (target->virtual_height > 2048) si->acc_mode = false; + /* (NV cards can even do more than this(?)... + * but 4096 is confirmed on all cards at max. accelerated width.) */ + if (target->virtual_height > 4096) si->acc_mode = false; /* now check NV virtual_size based on CRTC constraints */ { @@ -956,9 +1023,6 @@ status_t nv_general_validate_pic_size (display_mode *target, uint32 *bytes_per_r if (target->virtual_height > 65535) target->virtual_height = 65535; } -//temp disabled: -si->acc_mode = false; - /* OK, now we know that virtual_width is valid, and it's needing no slopspace if * it was confined above, so we can finally calculate safely if we need slopspace * for this mode... */ diff --git a/src/add-ons/accelerants/nvidia/engine/nv_proto.h b/src/add-ons/accelerants/nvidia/engine/nv_proto.h index 4f8a76e7a3..61876b84b1 100644 --- a/src/add-ons/accelerants/nvidia/engine/nv_proto.h +++ b/src/add-ons/accelerants/nvidia/engine/nv_proto.h @@ -99,9 +99,12 @@ status_t g400_crtc2_dpms_fetch(uint8 * display,uint8 * h,uint8 * v); /*acceleration functions*/ status_t check_acc_capability(uint32 feature); status_t nv_acc_init(); -status_t nv_acc_rectangle(uint32 xs,uint32 xe,uint32 ys,uint32 yl,uint32 col); -status_t nv_acc_rectangle_invert(uint32 xs,uint32 xe,uint32 ys,uint32 yl,uint32 col); +status_t nv_acc_setup_blit(); status_t nv_acc_blit(uint16,uint16,uint16, uint16,uint16,uint16 ); +status_t nv_acc_setup_rectangle(uint32 color); +status_t nv_acc_rectangle(uint32 xs,uint32 xe,uint32 ys,uint32 yl); +status_t nv_acc_setup_rect_invert(); +status_t nv_acc_rectangle_invert(uint32 xs,uint32 xe,uint32 ys,uint32 yl); status_t nv_acc_transparent_blit(uint16,uint16,uint16, uint16,uint16,uint16, uint32); status_t nv_acc_video_blit(uint16 xs,uint16 ys,uint16 ws, uint16 hs, uint16 xd,uint16 yd,uint16 wd,uint16 hd); @@ -109,6 +112,7 @@ status_t nv_acc_wait_idle(); /*backend scaler functions*/ status_t check_overlay_capability(uint32 feature); +status_t nv_bes_init(); status_t nv_configure_bes (const overlay_buffer *ob, const overlay_window *ow,const overlay_view *ov, int offset); status_t nv_release_bes(); diff --git a/src/add-ons/kernel/drivers/graphics/nvidia/driver.c b/src/add-ons/kernel/drivers/graphics/nvidia/driver.c index 5d5c77c218..1fc7904b2c 100644 --- a/src/add-ons/kernel/drivers/graphics/nvidia/driver.c +++ b/src/add-ons/kernel/drivers/graphics/nvidia/driver.c @@ -4,7 +4,7 @@ Other authors: Mark Watson; - Rudolf Cornelissen 3/2002-7/2003. + Rudolf Cornelissen 3/2002-10/2003. */ /* standard kernel driver stuff */ @@ -131,10 +131,12 @@ static uint16 nvidia_device_list[] = { 0x0178, /* Nvidia Quadro4 500 XGL/550 XGL */ 0x017a, /* Nvidia Quadro4 200 NVS/400 NVS */ 0x017c, /* Nvidia Quadro4 500 GoGL */ - //fixme: three IDs below correct?? + 0x017d, /* Nvidia unknown 4 Go */ 0x0180, /* Nvidia GeForce4 MX 440 AGP8X */ 0x0181, /* Nvidia GeForce4 MX 440SE AGP8X */ 0x0182, /* Nvidia GeForce4 MX 420 AGP8X */ + 0x0186, /* Nvidia GeForce4 448 Go */ + 0x0187, /* Nvidia GeForce4 488 Go */ 0x0188, /* Nvidia Quadro4 580 XGL */ 0x018a, /* Nvidia Quadro4 280 NVS */ 0x018b, /* Nvidia Quadro4 380 XGL */ @@ -156,6 +158,7 @@ static uint16 nvidia_device_list[] = { 0x0286, /* Nvidia GeForce4 4200 Go */ 0x0288, /* Nvidia Quadro4 980 XGL */ 0x0289, /* Nvidia Quadro4 780 XGL */ + 0x028c, /* Nvidia unknown 4 Go */ 0x02a0, /* Nvidia GeForce3 Integrated GPU */ 0x0301, /* Nvidia GeForce FX 5800 Ultra */ 0x0302, /* Nvidia GeForce FX 5800 */ @@ -163,10 +166,20 @@ static uint16 nvidia_device_list[] = { 0x0309, /* Nvidia Quadro FX 1000 */ 0x0311, /* Nvidia GeForce FX 5600 Ultra */ 0x0312, /* Nvidia GeForce FX 5600 */ + 0x0316, /* Nvidia unknown FX Go */ + 0x0317, /* Nvidia unknown FX Go */ 0x031a, /* Nvidia GeForce FX 5600 Go */ + 0x031b, /* Nvidia unknown FX Go */ + 0x031c, /* Nvidia unknown FX Go */ + 0x031d, /* Nvidia unknown FX Go */ + 0x031e, /* Nvidia unknown FX Go */ + 0x031f, /* Nvidia unknown FX Go */ 0x0321, /* Nvidia GeForce FX 5200 Ultra */ 0x0322, /* Nvidia GeForce FX 5200 */ + 0x0324, /* Nvidia GeForce FX 5200 Go */ + 0x0326, /* Nvidia unknown FX Go */ 0x032b, /* Nvidia Quadro FX 500 */ + 0x032e, /* Nvidia unknown FX Go */ 0x0330, /* Nvidia GeForce FX 5900 Ultra */ 0x0331, /* Nvidia GeForce FX 5900 */ 0x0338, /* Nvidia Quadro FX 3000 */ @@ -229,32 +242,38 @@ static void dumprom (void *rom, size_t size) close (fd); } -/*return 1, is interrupt has occured*/ +/* return 1 if vblank interrupt has occured */ int caused_vbi(vuint32 * regs) { -// return (ACCR(STATUS)&0x20); -//temp: -return 0; + return (NV_REG32(NV32_CRTC_INTS) & 0x00000001); } -/*clear the interrupt*/ +/* clear the vblank interrupt */ void clear_vbi(vuint32 * regs) { -// ACCW(ICLEAR,0x20); + NV_REG32(NV32_CRTC_INTS) = 0x00000001; } void enable_vbi(vuint32 * regs) { -// ACCW(IEN,ACCR(IEN)|0x20); + /* clear the vblank interrupt */ + NV_REG32(NV32_CRTC_INTS) = 0x00000001; + /* enable nVidia interrupt source vblank */ + NV_REG32(NV32_CRTC_INTE) |= 0x00000001; + /* enable nVidia interrupt system hardware (b0-1) */ + NV_REG32(NV32_MAIN_INTE) = 0x00000001; } void disable_vbi(vuint32 * regs) { -// ACCW(IEN,(ACCR(IEN)&~0x20)); -// ACCW(ICLEAR,0x20); + /* disable nVidia interrupt source vblank */ + NV_REG32(NV32_CRTC_INTE) &= 0xfffffffe; + /* clear the vblank interrupt */ + NV_REG32(NV32_CRTC_INTS) = 0x00000001; + /* disable nVidia interrupt system hardware (b0-1) */ + NV_REG32(NV32_MAIN_INTE) = 0x00000000; } - /* init_hardware() - Returns B_OK if one is found, otherwise returns B_ERROR so the driver will be unloaded.