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Use scsi direction mask to determine if the command to execute is a write,

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instead of checking every single command.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@25650 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Marcus Overhagen
2008-05-24 21:27:44 +00:00
parent ec5161c7b2
commit b54c709405
1 changed files with 17 additions and 12 deletions
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src/add-ons/kernel/busses/scsi/ahci/ahci_port.cpp
+17 -12
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@@ -682,7 +682,7 @@ AHCIPort::ExecuteSataRequest(sata_request *request, bool isWrite)
int prdEntrys; int prdEntrys;
if (request->ccb() && request->ccb()->sg_count) if (request->ccb() && request->ccb()->data_length)
FillPrdTable(fPRDTable, &prdEntrys, PRD_TABLE_ENTRY_COUNT, request->ccb()->sg_list, request->ccb()->sg_count, request->ccb()->data_length); FillPrdTable(fPRDTable, &prdEntrys, PRD_TABLE_ENTRY_COUNT, request->ccb()->sg_list, request->ccb()->sg_count, request->ccb()->data_length);
else if (request->data() && request->size()) else if (request->data() && request->size())
FillPrdTable(fPRDTable, &prdEntrys, PRD_TABLE_ENTRY_COUNT, request->data(), request->size()); FillPrdTable(fPRDTable, &prdEntrys, PRD_TABLE_ENTRY_COUNT, request->data(), request->size());
@@ -772,25 +772,30 @@ AHCIPort::ScsiExecuteRequest(scsi_ccb *request)
// TRACE("AHCIPort::ScsiExecuteRequest port %d, opcode 0x%02x, length %u\n", fIndex, request->cdb[0], request->cdb_length); // TRACE("AHCIPort::ScsiExecuteRequest port %d, opcode 0x%02x, length %u\n", fIndex, request->cdb[0], request->cdb_length);
if (fIsATAPI && request->cdb[0] != SCSI_OP_INQUIRY) { if (fIsATAPI && request->cdb[0] != SCSI_OP_INQUIRY) {
bool isWrite; bool isWrite = false;
switch (request->cdb[0]) { switch (request->flags & SCSI_DIR_MASK) {
case SCSI_OP_WRITE_6: case SCSI_DIR_NONE:
case SCSI_OP_WRITE_10: ASSERT(request->data_length == 0);
case SCSI_OP_WRITE_12: break;
case SCSI_DIR_IN:
ASSERT(request->data_length > 0);
break;
case SCSI_DIR_OUT:
isWrite = true; isWrite = true;
ASSERT(request->data_length > 0);
break; break;
default: default:
isWrite = false; panic("CDB has invalid direction mask");
} }
TRACE("AHCIPort::ScsiExecuteRequest ATAPI: port %d, opcode 0x%02x, length %u\n", fIndex, request->cdb[0], request->cdb_length); // TRACE("AHCIPort::ScsiExecuteRequest ATAPI: port %d, opcode 0x%02x, length %u\n", fIndex, request->cdb[0], request->cdb_length);
sata_request *sreq = new(std::nothrow) sata_request(request); sata_request *sreq = new(std::nothrow) sata_request(request);
sreq->set_atapi_cmd(); sreq->set_atapi_cmd();
uint8 *data = (uint8*) sreq->ccb()->cdb; // uint8 *data = (uint8*) sreq->ccb()->cdb;
for (int i = 0; i < 16; i += 8) { // for (int i = 0; i < 16; i += 8) {
TRACE(" %02x %02x %02x %02x %02x %02x %02x %02x\n", data[i], data[i+1], data[i+2], data[i+3], data[i+4], data[i+5], data[i+6], data[i+7]); // TRACE(" %02x %02x %02x %02x %02x %02x %02x %02x\n", data[i], data[i+1], data[i+2], data[i+3], data[i+4], data[i+5], data[i+6], data[i+7]);
} // }
ExecuteSataRequest(sreq, isWrite); ExecuteSataRequest(sreq, isWrite);
return; return;
} }