From b6994f96c0edb0d10620cf8b40a7b21888f715f6 Mon Sep 17 00:00:00 2001 From: Alexander von Gluck IV Date: Wed, 26 Feb 2014 13:17:21 -0600 Subject: [PATCH] ARM: Break apart ARMv5 and older dsb/dmb * Add isb just because. * pdziepak pointed out that ARMv5 and before had different barrier support. * pdziepak also mentioned that dsb was too strong for __sync_synchronize --- headers/private/kernel/arch/arm/arch_atomic.h | 12 ++++++++++-- src/system/libroot/os/arch/arm/thread.c | 2 +- 2 files changed, 11 insertions(+), 3 deletions(-) diff --git a/headers/private/kernel/arch/arm/arch_atomic.h b/headers/private/kernel/arch/arm/arch_atomic.h index 50b4bb791d..1c5b5e3ff3 100644 --- a/headers/private/kernel/arch/arm/arch_atomic.h +++ b/headers/private/kernel/arch/arm/arch_atomic.h @@ -9,12 +9,20 @@ #define _KERNEL_ARCH_ARM_ATOMIC_H -#if __ARM_ARCH__ <= 6 +#if __ARM_ARCH__ <= 5 +#define isb() __asm__ __volatile__("" : : : "memory") +#define dsb() __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" \ + : : "r" (0) : "memory") +#define dmb() __asm__ __volatile__("" : : : "memory") +#elif __ARM_ARCH__ == 6 +#define isb() __asm__ __volatile__("mcr p15, 0, %0, c7, c5, 4" \ + : : "r" (0) : "memory") #define dsb() __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" \ : : "r" (0) : "memory") #define dmb() __asm__ __volatile__("mcr p15, 0, %0, c7, c10, 4" \ : : "r" (0) : "memory") -#else +#else /* ARMv7+ */ +#define isb() __asm__ __volatile__("isb" : : : "memory") #define dsb() __asm__ __volatile__("dsb" : : : "memory") #define dmb() __asm__ __volatile__("dmb" : : : "memory") #endif diff --git a/src/system/libroot/os/arch/arm/thread.c b/src/system/libroot/os/arch/arm/thread.c index cb233d4147..e922970bca 100644 --- a/src/system/libroot/os/arch/arm/thread.c +++ b/src/system/libroot/os/arch/arm/thread.c @@ -27,5 +27,5 @@ find_thread(const char *name) void __sync_synchronize(void) { - dsb(); + dmb(); }