pl011 uart: Add port_init code

* Add code to initilize the uart port
* Fix uart clock
This commit is contained in:
Alexander von Gluck IV
2012-05-06 22:53:56 -05:00
parent c76127fade
commit b74906293b
4 changed files with 37 additions and 9 deletions
@@ -24,8 +24,8 @@
#define BOARD_UART_DEBUG BOARD_UART2_BASE #define BOARD_UART_DEBUG BOARD_UART2_BASE
#define BOARD_UART_CLOCK 125000000 #define BOARD_UART_CLOCK 3000000
/* 125Mhz, strange */ /* 3Mhz */
#endif /* _BOARD_RASPBERRY_PI_BOARD_CONFIG_H */ #endif /* _BOARD_RASPBERRY_PI_BOARD_CONFIG_H */
@@ -72,6 +72,17 @@
#define PL011_CR_SIREN 0x0002 // SIR enable #define PL011_CR_SIREN 0x0002 // SIR enable
#define PL011_CR_UARTEN 0x0001 // UART enable #define PL011_CR_UARTEN 0x0001 // UART enable
#define PL011_LCRH_SPS 0x80
#define PL01x_LCRH_WLEN_8 0x60
#define PL01x_LCRH_WLEN_7 0x40
#define PL01x_LCRH_WLEN_6 0x20
#define PL01x_LCRH_WLEN_5 0x00
#define PL01x_LCRH_FEN 0x10
#define PL01x_LCRH_STP2 0x08
#define PL01x_LCRH_EPS 0x04
#define PL01x_LCRH_PEN 0x02
#define PL01x_LCRH_BRK 0x01
// TODO: Other PL01x registers + values? // TODO: Other PL01x registers + values?
@@ -89,7 +89,8 @@ serial_init(void)
} }
gUARTInfo->init_early(); gUARTInfo->init_early();
gUARTInfo->init(gUARTInfo->base); gUARTInfo->init_port(gUARTInfo->base, 9600);
//gUARTInfo->init(gUARTInfo->base);
serial_enable(); serial_enable();
+22 -6
View File
@@ -31,6 +31,28 @@ read_pl011(addr_t base, uint reg)
void void
uart_pl011_init_port(addr_t base, uint baud) uart_pl011_init_port(addr_t base, uint baud)
{ {
uint16 clockDiv
= (baud > BOARD_UART_CLOCK / 16) ? 8 : 4;
uint16 baudDivisor = BOARD_UART_CLOCK * clockDiv / baud;
// TODO: Round to closest baud divisor
uint16 lcr = PL01x_LCRH_WLEN_8;
// Disable everything
unsigned char originalCR
= read_pl011(base, PL011_CR);
write_pl011(base, PL011_CR, 0);
// Set baud divisor
write_pl011(base, PL011_FBRD, baudDivisor & 0x3f);
write_pl011(base, PL011_IBRD, baudDivisor >> 6);
// Set LCR
write_pl011(base, PL011_LCRH, lcr);
// Disable auto RTS / CTS in original CR
originalCR &= ~(PL011_CR_CTSEN | PL011_CR_RTSEN);
write_pl011(base, PL011_CR, originalCR);
} }
@@ -60,12 +82,6 @@ uart_pl011_init(addr_t base)
while (read_pl011(base, PL01x_FR) & PL01x_FR_BUSY); while (read_pl011(base, PL01x_FR) & PL01x_FR_BUSY);
// Wait for xmit // Wait for xmit
// Write baud divider
#if 0
write_pl011(base, PL011_FBRD, div & 0x3F);
write_pl011(base, PL011_IBRD, div >> 6);
#endif
} }