introduce RISC-V headers
Change-Id: I9a8b6a1011cbefd4bd173852e7111e92efd0c730 Reviewed-on: https://review.haiku-os.org/c/haiku/+/4003 Reviewed-by: Alex von Gluck IV <[email protected]>
This commit is contained in:
X512
@@ -1,41 +1,330 @@
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/*
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* Copyright 2018-2019, Haiku, Inc. All rights reserved
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* Copyright 2021, Haiku, Inc.
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* Distributed under the terms of the MIT License.
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*
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* Authors:
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* Alexander von Gluck IV <[email protected]>
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*/
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#ifndef _SYSTEM_ARCH_RISCV64_DEFS_H
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#define _SYSTEM_ARCH_RISCV64_DEFS_H
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#include <SupportDefs.h>
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enum {
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modeU = 0,
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modeS = 1,
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modeM = 3,
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};
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// fs, xs
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enum {
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extStatusOff = 0,
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extStatusInitial = 1,
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extStatusClean = 2,
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extStatusDirty = 3,
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};
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struct MstatusReg {
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union {
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struct {
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uint64 ie: 4; // interrupt enable
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uint64 pie: 4; // previous interrupt enable
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uint64 spp: 1; // previous mode (supervisor)
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uint64 unused1: 2;
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uint64 mpp: 2; // previous mode (machine)
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uint64 fs: 2; // FPU status
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uint64 xs: 2; // extensions status
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uint64 mprv: 1; // modify privelege
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uint64 sum: 1; // permit supervisor user memory access
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uint64 mxr: 1; // make executable readable
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uint64 tvm: 1; // trap virtual memory
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uint64 tw: 1; // timeout wait (trap WFI)
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uint64 tsr: 1; // trap SRET
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uint64 unused2: 9;
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uint64 uxl: 2; // U-mode XLEN
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uint64 sxl: 2; // S-mode XLEN
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uint64 unused3: 27;
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uint64 sd: 1; // status dirty
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};
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uint64 val;
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};
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MstatusReg() {}
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MstatusReg(uint64 val): val(val) {}
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};
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struct SstatusReg {
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union {
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struct {
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uint64 ie: 2; // interrupt enable
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uint64 unused1: 2;
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uint64 pie: 2; // previous interrupt enable
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uint64 unused2: 2;
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uint64 spp: 1; // previous mode (supervisor)
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uint64 unused3: 4;
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uint64 fs: 2; // FPU status
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uint64 xs: 2; // extensions status
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uint64 unused4: 1;
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uint64 sum: 1; // permit supervisor user memory access
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uint64 mxr: 1; // make executable readable
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uint64 unused5: 12;
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uint64 uxl: 2; // U-mode XLEN
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uint64 unused6: 29;
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uint64 sd: 1; // status dirty
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};
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uint64 val;
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};
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SstatusReg() {}
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SstatusReg(uint64 val): val(val) {}
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};
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enum {
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softInt = 0,
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uSoftInt = softInt + modeU,
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sSoftInt = softInt + modeS,
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mSoftInt = softInt + modeM,
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timerInt = 4,
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uTimerInt = timerInt + modeU,
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sTimerInt = timerInt + modeS,
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mTimerInt = timerInt + modeM,
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externInt = 8,
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uExternInt = externInt + modeU,
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sExternInt = externInt + modeS,
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mExternInt = externInt + modeM,
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};
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enum {
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causeInterrupt = 1ULL << 63, // rest bits are interrupt number
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causeExecMisalign = 0,
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causeExecAccessFault = 1,
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causeIllegalInst = 2,
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causeBreakpoint = 3,
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causeLoadMisalign = 4,
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causeLoadAccessFault = 5,
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causeStoreMisalign = 6,
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causeStoreAccessFault = 7,
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causeECall = 8,
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causeUEcall = causeECall + modeU,
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causeSEcall = causeECall + modeS,
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causeMEcall = causeECall + modeM,
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causeExecPageFault = 12,
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causeLoadPageFault = 13,
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causeStorePageFault = 15,
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};
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enum {
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pageSize = 4096,
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pageBits = 12,
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pteCount = 512,
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pteIdxBits = 9,
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};
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enum {
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pteValid = 0,
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pteRead = 1,
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pteWrite = 2,
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pteExec = 3,
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pteUser = 4,
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pteGlobal = 5,
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pteAccessed = 6,
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pteDirty = 7,
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};
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struct Pte {
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union {
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struct {
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uint64 flags: 8;
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uint64 rsw: 2;
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uint64 ppn: 44;
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uint64 reserved: 10;
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};
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uint64 val;
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};
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Pte() {}
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Pte(uint64 val): val(val) {}
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};
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enum {
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satpModeBare = 0,
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satpModeSv39 = 8,
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satpModeSv48 = 9,
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satpModeSv57 = 10,
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satpModeSv64 = 11,
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};
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struct SatpReg {
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union {
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struct {
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uint64 ppn: 44;
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uint64 asid: 16;
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uint64 mode: 4;
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};
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uint64 val;
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};
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SatpReg() {}
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SatpReg(uint64 val): val(val) {}
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};
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static B_ALWAYS_INLINE uint64 PhysAdrPte(uint64 physAdr, uint32 level)
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{
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return (physAdr >> (pageBits + pteIdxBits*level)) % (1 << pteIdxBits);
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}
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static B_ALWAYS_INLINE uint64 PhysAdrOfs(uint64 physAdr)
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{
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return physAdr % pageSize;
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}
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// CPU core ID
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static B_ALWAYS_INLINE uint64 Mhartid() {
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uint64 x; asm volatile("csrr %0, mhartid" : "=r" (x)); return x;}
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// status register
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static B_ALWAYS_INLINE uint64 Mstatus() {
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uint64 x; asm volatile("csrr %0, mstatus" : "=r" (x)); return x;}
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static B_ALWAYS_INLINE void SetMstatus(uint64 x) {
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asm volatile("csrw mstatus, %0" : : "r" (x));}
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static B_ALWAYS_INLINE uint64 Sstatus() {
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uint64 x; asm volatile("csrr %0, sstatus" : "=r" (x)); return x;}
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static B_ALWAYS_INLINE void SetSstatus(uint64 x) {
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asm volatile("csrw sstatus, %0" : : "r" (x));}
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// exception program counter
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static B_ALWAYS_INLINE uint64 Mepc() {
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uint64 x; asm volatile("csrr %0, mepc" : "=r" (x)); return x;}
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static B_ALWAYS_INLINE void SetMepc(uint64 x) {
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asm volatile("csrw mepc, %0" : : "r" (x));}
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static B_ALWAYS_INLINE uint64 Sepc() {
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uint64 x; asm volatile("csrr %0, sepc" : "=r" (x)); return x;}
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static B_ALWAYS_INLINE void SetSepc(uint64 x) {
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asm volatile("csrw sepc, %0" : : "r" (x));}
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// interrupt pending
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static B_ALWAYS_INLINE uint64 Mip() {
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uint64 x; asm volatile("csrr %0, mip" : "=r" (x)); return x;}
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static B_ALWAYS_INLINE void SetMip(uint64 x) {
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asm volatile("csrw mip, %0" : : "r" (x));}
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static B_ALWAYS_INLINE uint64 Sip() {
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uint64 x; asm volatile("csrr %0, sip" : "=r" (x)); return x;}
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static B_ALWAYS_INLINE void SetSip(uint64 x) {
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asm volatile("csrw sip, %0" : : "r" (x));}
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// interrupt enable
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static B_ALWAYS_INLINE uint64 Sie() {
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uint64 x; asm volatile("csrr %0, sie" : "=r" (x)); return x;}
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static B_ALWAYS_INLINE void SetSie(uint64 x) {
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asm volatile("csrw sie, %0" : : "r" (x));}
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static B_ALWAYS_INLINE uint64 Mie() {
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uint64 x; asm volatile("csrr %0, mie" : "=r" (x)); return x;}
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static B_ALWAYS_INLINE void SetMie(uint64 x) {
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asm volatile("csrw mie, %0" : : "r" (x));}
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// exception delegation
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static B_ALWAYS_INLINE uint64 Medeleg() {
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uint64 x; asm volatile("csrr %0, medeleg" : "=r" (x)); return x;}
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static B_ALWAYS_INLINE void SetMedeleg(uint64 x) {
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asm volatile("csrw medeleg, %0" : : "r" (x));}
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// interrupt delegation
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static B_ALWAYS_INLINE uint64 Mideleg() {
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uint64 x; asm volatile("csrr %0, mideleg" : "=r" (x)); return x;}
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static B_ALWAYS_INLINE void SetMideleg(uint64 x) {
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asm volatile("csrw mideleg, %0" : : "r" (x));}
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// trap vector, 2 low bits: mode
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static B_ALWAYS_INLINE uint64 Mtvec() {
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uint64 x; asm volatile("csrr %0, mtvec" : "=r" (x)); return x;}
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static B_ALWAYS_INLINE void SetMtvec(uint64 x) {
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asm volatile("csrw mtvec, %0" : : "r" (x));}
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static B_ALWAYS_INLINE uint64 Stvec() {
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uint64 x; asm volatile("csrr %0, stvec" : "=r" (x)); return x;}
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static B_ALWAYS_INLINE void SetStvec(uint64 x) {
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asm volatile("csrw stvec, %0" : : "r" (x));}
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// address translation and protection (pointer to page table and flags)
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static B_ALWAYS_INLINE uint64 Satp() {
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uint64 x; asm volatile("csrr %0, satp" : "=r" (x)); return x;}
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static B_ALWAYS_INLINE void SetSatp(uint64 x) {
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asm volatile("csrw satp, %0" : : "r" (x));}
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// scratch register
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static B_ALWAYS_INLINE uint64 Mscratch() {
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uint64 x; asm volatile("csrr %0, mscratch" : "=r" (x)); return x;}
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static B_ALWAYS_INLINE void SetMscratch(uint64 x) {
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asm volatile("csrw mscratch, %0" : : "r" (x));}
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static B_ALWAYS_INLINE uint64 Sscratch() {
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uint64 x; asm volatile("csrr %0, sscratch" : "=r" (x)); return x;}
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static B_ALWAYS_INLINE void SetSscratch(uint64 x) {
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asm volatile("csrw sscratch, %0" : : "r" (x));}
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// trap cause
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static B_ALWAYS_INLINE uint64 Mcause() {
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uint64 x; asm volatile("csrr %0, mcause" : "=r" (x)); return x;}
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static B_ALWAYS_INLINE void SetMcause(uint64 x) {
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asm volatile("csrw mcause, %0" : : "r" (x));}
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static B_ALWAYS_INLINE uint64 Scause() {
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uint64 x; asm volatile("csrr %0, scause" : "=r" (x)); return x;}
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static B_ALWAYS_INLINE void SetScause(uint64 x) {
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asm volatile("csrw scause, %0" : : "r" (x));}
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// trap value
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static B_ALWAYS_INLINE uint64 Mtval() {
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uint64 x; asm volatile("csrr %0, mtval" : "=r" (x)); return x;}
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static B_ALWAYS_INLINE void SetMtval(uint64 x) {
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asm volatile("csrw mtval, %0" : : "r" (x));}
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static B_ALWAYS_INLINE uint64 Stval() {
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uint64 x; asm volatile("csrr %0, stval" : "=r" (x)); return x;}
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static B_ALWAYS_INLINE void SetStval(uint64 x) {
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asm volatile("csrw stval, %0" : : "r" (x));}
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// machine-mode counter enable
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static B_ALWAYS_INLINE uint64 Mcounteren() {
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uint64 x; asm volatile("csrr %0, mcounteren" : "=r" (x)); return x;}
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static B_ALWAYS_INLINE void SetMcounteren(uint64 x) {
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asm volatile("csrw mcounteren, %0" : : "r" (x));}
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// machine-mode cycle counter
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static B_ALWAYS_INLINE uint64 Mcycle() {
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uint64 x; asm volatile("csrr %0, mcycle" : "=r" (x)); return x;}
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// monotonic timer
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static B_ALWAYS_INLINE uint64 CpuTime() {
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uint64 x; asm volatile("csrr %0, time" : "=r" (x)); return x;}
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// flush the TLB
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static B_ALWAYS_INLINE void FlushTlbAll() {
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asm volatile("sfence.vma" : : : "memory");}
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static B_ALWAYS_INLINE void FlushTlbPage(uint64 x) {
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asm volatile("sfence.vma %0" : : "r" (x) : "memory");}
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static B_ALWAYS_INLINE uint64 Sp() {
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uint64 x; asm volatile("mv %0, sp" : "=r" (x)); return x;}
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static B_ALWAYS_INLINE void SetSp(uint64 x) {
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asm volatile("mv sp, %0" : : "r" (x));}
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static B_ALWAYS_INLINE uint64 Fp() {
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uint64 x; asm volatile("mv %0, fp" : "=r" (x)); return x;}
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static B_ALWAYS_INLINE void SetFp(uint64 x) {
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asm volatile("mv fp, %0" : : "r" (x));}
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static B_ALWAYS_INLINE uint64 Tp() {
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uint64 x; asm volatile("mv %0, tp" : "=r" (x)); return x;}
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static B_ALWAYS_INLINE void SetTp(uint64 x) {
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asm volatile("mv tp, %0" : : "r" (x));}
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static B_ALWAYS_INLINE uint64 Ra() {
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uint64 x; asm volatile("mv %0, ra" : "=r" (x)); return x;}
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static B_ALWAYS_INLINE void SetRa(uint64 x) {
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asm volatile("mv ra, %0" : : "r" (x));}
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static B_ALWAYS_INLINE void Ecall() {asm volatile("ecall");}
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// Wait for interrupts, reduce CPU load when inactive.
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static B_ALWAYS_INLINE void Wfi() {asm volatile("wfi");}
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static B_ALWAYS_INLINE void Mret() {asm volatile("mret");}
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static B_ALWAYS_INLINE void Sret() {asm volatile("sret");}
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#define SPINLOCK_PAUSE() do {} while (false)
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// Status register flags
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#define ARCH_SR_SIE 0x00000002 // Supervisor Interrupt Enable
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#define ARCH_SR_SPIE 0x00000020 // Previous Supervisor Interrupt En
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#define ARCH_SR_SPP 0x00000100 // Previously Supervisor
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#define ARCH_SR_SUM 0x00040000 // Supervisor may access user memory
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#define ARCH_SR_FS 0x00006000 // Floating Point Status
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#define ARCH_SR_FS_OFF 0x00000000
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#define ARCH_SR_FS_INITIAL 0x00002000
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#define ARCH_SR_FS_CLEAN 0x00004000
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#define ARCH_SR_FS_DIRTY 0x00006000
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#define ARCH_SR_XS 0x00018000 // Extension Status
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#define ARCH_SR_XS_OFF 0x00000000
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#define ARCH_SR_XS_INITIAL 0x00008000
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#define ARCH_SR_XS_CLEAN 0x00010000
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#define ARCH_SR_XS_DIRTY 0x00018000
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#define ARCH_SR_SD 0x8000000000000000 // FS/XS dirty
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// Interrupt Enable and Interrupt Pending
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#define ARCH_SIE_SSIE 0x00000002 // Software Interrupt Enable
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#define ARCH_SIE_STIE 0x00000020 // Timer Interrupt Enable
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#define ARCH_SIE_SEIE 0x00000200 // External Interrupt Enable
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#endif /* _SYSTEM_ARCH_RISCV64_DEFS_H */
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