From baa7999a48a2a0e147b439ef35491281cfef0613 Mon Sep 17 00:00:00 2001
From: Alexander von Gluck IV <kallisti5@unixzen.com>
Date: Tue, 14 Aug 2012 07:00:48 -0500
Subject: [PATCH] radeon_hd: slight adjustment to PLL choosing on DP

---
 src/add-ons/accelerants/radeon_hd/pll.cpp | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/src/add-ons/accelerants/radeon_hd/pll.cpp b/src/add-ons/accelerants/radeon_hd/pll.cpp
index 1bec580de5..0abaa935f7 100644
--- a/src/add-ons/accelerants/radeon_hd/pll.cpp
+++ b/src/add-ons/accelerants/radeon_hd/pll.cpp
@@ -942,15 +942,15 @@ pll_pick(uint32 connectorIndex)
 		return B_OK;
 	} else if (info.dceMajor >= 4) {
 		if (connector_is_dp(connectorIndex)) {
-			if (info.dceMajor >= 6) {
+			if (gInfo->dpExternalClock) {
+				pll->id = ATOM_PPLL_INVALID;
+				return B_OK;
+			} else if (info.dceMajor >= 6) {
 				pll->id = ATOM_PPLL1;
 				return B_OK;
 			} else if (info.dceMajor >= 5) {
 				pll->id = ATOM_DCPLL;
 				return B_OK;
-			} else if (gInfo->dpExternalClock) {
-				pll->id = ATOM_PPLL_INVALID;
-				return B_OK;
 			}
 		}
 		pll->id = ATOM_PPLL1;