diff --git a/headers/private/graphics/intel_extreme/intel_extreme.h b/headers/private/graphics/intel_extreme/intel_extreme.h
index ed7a26a8f9..acd2ce7f3d 100644
--- a/headers/private/graphics/intel_extreme/intel_extreme.h
+++ b/headers/private/graphics/intel_extreme/intel_extreme.h
@@ -470,6 +470,10 @@ struct intel_free_graphics_memory {
 #define PCH_HDMI_PORT_C					(0x1150 | REGS_SOUTH_TRANSCODER_PORT)
 #define PCH_HDMI_PORT_D					(0x1160 | REGS_SOUTH_TRANSCODER_PORT)
 
+#define GEN4_HDMI_PORT_B				(0x1140 | REGS_SOUTH_TRANSCODER_PORT)
+#define GEN4_HDMI_PORT_C				(0x1160 | REGS_SOUTH_TRANSCODER_PORT)
+#define GEN4_HDMI_PORT_D				(0x116C | REGS_SOUTH_TRANSCODER_PORT)
+
 #define INTEL_DISPLAY_PORT_A			(0x4000 | REGS_NORTH_PIPE_AND_PORT)
 #define INTEL_DISPLAY_PORT_B			(0x4100 | REGS_NORTH_PIPE_AND_PORT)
 #define INTEL_DISPLAY_PORT_C			(0x4200 | REGS_NORTH_PIPE_AND_PORT)
diff --git a/src/add-ons/accelerants/intel_extreme/Ports.cpp b/src/add-ons/accelerants/intel_extreme/Ports.cpp
index 29d5524a49..77ebd8facb 100644
--- a/src/add-ons/accelerants/intel_extreme/Ports.cpp
+++ b/src/add-ons/accelerants/intel_extreme/Ports.cpp
@@ -280,6 +280,9 @@ HDMIPort::IsConnected()
 		return false;
 
 	uint32 portRegister = _PortRegister();
+	TRACE("%s %d: PortRegister: %" B_PRIx32 "\n", PortName(), PortIndex(),
+		portRegister);
+
 	if (portRegister == 0)
 		return false;
 
@@ -298,17 +301,23 @@ HDMIPort::_PortRegister()
 {
 	// on PCH there's an additional port sandwiched in
 	bool hasPCH = gInfo->shared_info->device_type.HasPlatformControlHub();
+	bool fourthGen = gInfo->shared_info->device_type.InGroup(INTEL_TYPE_VLV);
 
 	switch (PortIndex()) {
 		case INTEL_PORT_B:
+			if (fourthGen)
+				return GEN4_HDMI_PORT_B;
 			return hasPCH ? PCH_HDMI_PORT_B : INTEL_HDMI_PORT_B;
 		case INTEL_PORT_C:
+			if (fourthGen)
+				return GEN4_HDMI_PORT_C;
 			return hasPCH ? PCH_HDMI_PORT_C : INTEL_HDMI_PORT_C;
 		case INTEL_PORT_D:
+			// TODO: Is CherryView? GEN4_HDMI_PORT_D
 			return hasPCH ? PCH_HDMI_PORT_D : 0;
 		default:
 			return 0;
-	}
+		}
 
 	return 0;
 }
diff --git a/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp b/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp
index 7637ab9da0..847fafac93 100644
--- a/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp
+++ b/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp
@@ -98,7 +98,7 @@ intel_interrupt_handler(void* data)
 
 		// Intel changed the PCH register mapping between Sandy Bridge and the
 		// later generations (Ivy Bridge and up).
-		if (info.device_type.InFamily(INTEL_TYPE_SNB)) {
+		if (info.device_type.InGroup(INTEL_TYPE_SNB)) {
 			mask = hasPCH ? PCH_INTERRUPT_VBLANK_PIPEA_SNB
 				: INTERRUPT_VBLANK_PIPEA;
 			if ((identity & mask) != 0) {
@@ -347,11 +347,12 @@ intel_extreme_init(intel_info &info)
 	}
 
 	// "I nearly got violent with the hw guys when they told me..."
-	if (info.device_type.InFamily(INTEL_TYPE_VLV)) {
+	if (info.device_type.InGroup(INTEL_TYPE_VLV)) {
 		TRACE("%s: ValleyView MMIO offset engaged\n", __func__);
 		blocks[REGISTER_BLOCK(REGS_NORTH_PLANE_CONTROL)] += VLV_DISPLAY_BASE;
 		blocks[REGISTER_BLOCK(REGS_NORTH_SHARED)] += VLV_DISPLAY_BASE;
 		blocks[REGISTER_BLOCK(REGS_SOUTH_SHARED)] += VLV_DISPLAY_BASE;
+		blocks[REGISTER_BLOCK(REGS_SOUTH_TRANSCODER_PORT)] += VLV_DISPLAY_BASE;
 	}
 
 	// make sure bus master, memory-mapped I/O, and frame buffer is enabled