diff --git a/src/add-ons/kernel/drivers/network/wlan/Jamfile b/src/add-ons/kernel/drivers/network/wlan/Jamfile index 5ccfb63538..449c287da7 100644 --- a/src/add-ons/kernel/drivers/network/wlan/Jamfile +++ b/src/add-ons/kernel/drivers/network/wlan/Jamfile @@ -9,3 +9,4 @@ SubInclude HAIKU_TOP src add-ons kernel drivers network wlan iprowifi3945 ; SubInclude HAIKU_TOP src add-ons kernel drivers network wlan iprowifi4965 ; SubInclude HAIKU_TOP src add-ons kernel drivers network wlan marvell88w8363 ; SubInclude HAIKU_TOP src add-ons kernel drivers network wlan marvell88w8335 ; +SubInclude HAIKU_TOP src add-ons kernel drivers network wlan ralinkwifi ; diff --git a/src/add-ons/kernel/drivers/network/wlan/ralinkwifi/Jamfile b/src/add-ons/kernel/drivers/network/wlan/ralinkwifi/Jamfile new file mode 100644 index 0000000000..43c689cd9c --- /dev/null +++ b/src/add-ons/kernel/drivers/network/wlan/ralinkwifi/Jamfile @@ -0,0 +1,24 @@ +SubDir HAIKU_TOP src add-ons kernel drivers network wlan ralinkwifi ; + +UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd_network compat ] : true ; +UseHeaders [ FDirName $(HAIKU_TOP) src libs compat freebsd_wlan ] : true ; +UsePrivateHeaders net system ; +UsePrivateKernelHeaders ; + +SubDirCcFlags [ FDefines _KERNEL=1 FBSD_DRIVER=1 ] + -Wno-format + -Wno-unused + -Wno-uninitialized ; + +UseHeaders [ FDirName $(SUBDIR) ] : true ; + +SEARCH_SOURCE += [ FDirName $(SUBDIR) dev ral ] ; + +KernelAddon ralinkwifi : + if_ral_pci.c + rt2560.c + rt2661.c + : + libfreebsd_wlan.a + libfreebsd_network.a + ; diff --git a/src/add-ons/kernel/drivers/network/wlan/ralinkwifi/dev/ral/if_ral_pci.c b/src/add-ons/kernel/drivers/network/wlan/ralinkwifi/dev/ral/if_ral_pci.c new file mode 100644 index 0000000000..68b662261f --- /dev/null +++ b/src/add-ons/kernel/drivers/network/wlan/ralinkwifi/dev/ral/if_ral_pci.c @@ -0,0 +1,272 @@ +/* $FreeBSD$ */ + +/*- + * Copyright (c) 2005, 2006 + * Damien Bergamini + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include +__FBSDID("$FreeBSD$"); + +/* + * PCI/Cardbus front-end for the Ralink RT2560/RT2561/RT2561S/RT2661 driver. + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include + +#include +#include + +MODULE_DEPEND(ral, pci, 1, 1, 1); +MODULE_DEPEND(ral, firmware, 1, 1, 1); +MODULE_DEPEND(ral, wlan, 1, 1, 1); +MODULE_DEPEND(ral, wlan_amrr, 1, 1, 1); + +struct ral_pci_ident { + uint16_t vendor; + uint16_t device; + const char *name; +}; + +static const struct ral_pci_ident ral_pci_ids[] = { + { 0x1814, 0x0201, "Ralink Technology RT2560" }, + { 0x1814, 0x0301, "Ralink Technology RT2561S" }, + { 0x1814, 0x0302, "Ralink Technology RT2561" }, + { 0x1814, 0x0401, "Ralink Technology RT2661" }, + + { 0, 0, NULL } +}; + +static struct ral_opns { + int (*attach)(device_t, int); + int (*detach)(void *); + void (*shutdown)(void *); + void (*suspend)(void *); + void (*resume)(void *); + void (*intr)(void *); + +} ral_rt2560_opns = { + rt2560_attach, + rt2560_detach, + rt2560_stop, + rt2560_stop, + rt2560_resume, + rt2560_intr + +}, ral_rt2661_opns = { + rt2661_attach, + rt2661_detach, + rt2661_shutdown, + rt2661_suspend, + rt2661_resume, + rt2661_intr +}; + +struct ral_pci_softc { + union { + struct rt2560_softc sc_rt2560; + struct rt2661_softc sc_rt2661; + } u; + + struct ral_opns *sc_opns; + int irq_rid; + int mem_rid; + struct resource *irq; + struct resource *mem; + void *sc_ih; +}; + +static int ral_pci_probe(device_t); +static int ral_pci_attach(device_t); +static int ral_pci_detach(device_t); +static int ral_pci_shutdown(device_t); +static int ral_pci_suspend(device_t); +static int ral_pci_resume(device_t); + +static device_method_t ral_pci_methods[] = { + /* Device interface */ + DEVMETHOD(device_probe, ral_pci_probe), + DEVMETHOD(device_attach, ral_pci_attach), + DEVMETHOD(device_detach, ral_pci_detach), + DEVMETHOD(device_shutdown, ral_pci_shutdown), + DEVMETHOD(device_suspend, ral_pci_suspend), + DEVMETHOD(device_resume, ral_pci_resume), + + { 0, 0 } +}; + +static driver_t ral_pci_driver = { + "ral", + ral_pci_methods, + sizeof (struct ral_pci_softc) +}; + +static devclass_t ral_devclass; + +DRIVER_MODULE(ral, pci, ral_pci_driver, ral_devclass, 0, 0); + +static int +ral_pci_probe(device_t dev) +{ + const struct ral_pci_ident *ident; + + for (ident = ral_pci_ids; ident->name != NULL; ident++) { + if (pci_get_vendor(dev) == ident->vendor && + pci_get_device(dev) == ident->device) { + device_set_desc(dev, ident->name); + return 0; + } + } + return ENXIO; +} + +/* Base Address Register */ +#define RAL_PCI_BAR0 0x10 + +static int +ral_pci_attach(device_t dev) +{ + struct ral_pci_softc *psc = device_get_softc(dev); + struct rt2560_softc *sc = &psc->u.sc_rt2560; + int error; + + if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { + device_printf(dev, "chip is in D%d power mode " + "-- setting to D0\n", pci_get_powerstate(dev)); + pci_set_powerstate(dev, PCI_POWERSTATE_D0); + } + + /* enable bus-mastering */ + pci_enable_busmaster(dev); + + psc->sc_opns = (pci_get_device(dev) == 0x0201) ? &ral_rt2560_opns : + &ral_rt2661_opns; + + psc->mem_rid = RAL_PCI_BAR0; + psc->mem = bus_alloc_resource_any(dev, SYS_RES_MEMORY, &psc->mem_rid, + RF_ACTIVE); + if (psc->mem == NULL) { + device_printf(dev, "could not allocate memory resource\n"); + return ENXIO; + } + + sc->sc_st = rman_get_bustag(psc->mem); + sc->sc_sh = rman_get_bushandle(psc->mem); + sc->sc_invalid = 1; + + psc->irq_rid = 0; + psc->irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &psc->irq_rid, + RF_ACTIVE | RF_SHAREABLE); + if (psc->irq == NULL) { + device_printf(dev, "could not allocate interrupt resource\n"); + return ENXIO; + } + + error = (*psc->sc_opns->attach)(dev, pci_get_device(dev)); + if (error != 0) + return error; + + /* + * Hook our interrupt after all initialization is complete. + */ + error = bus_setup_intr(dev, psc->irq, INTR_TYPE_NET | INTR_MPSAFE, + NULL, psc->sc_opns->intr, psc, &psc->sc_ih); + if (error != 0) { + device_printf(dev, "could not set up interrupt\n"); + return error; + } + sc->sc_invalid = 0; + + return 0; +} + +static int +ral_pci_detach(device_t dev) +{ + struct ral_pci_softc *psc = device_get_softc(dev); + struct rt2560_softc *sc = &psc->u.sc_rt2560; + + /* check if device was removed */ + sc->sc_invalid = !bus_child_present(dev); + + (*psc->sc_opns->detach)(psc); + + bus_generic_detach(dev); + bus_teardown_intr(dev, psc->irq, psc->sc_ih); + bus_release_resource(dev, SYS_RES_IRQ, psc->irq_rid, psc->irq); + + bus_release_resource(dev, SYS_RES_MEMORY, psc->mem_rid, psc->mem); + + return 0; +} + +static int +ral_pci_shutdown(device_t dev) +{ + struct ral_pci_softc *psc = device_get_softc(dev); + + (*psc->sc_opns->shutdown)(psc); + + return 0; +} + +static int +ral_pci_suspend(device_t dev) +{ + struct ral_pci_softc *psc = device_get_softc(dev); + + (*psc->sc_opns->suspend)(psc); + + return 0; +} + +static int +ral_pci_resume(device_t dev) +{ + struct ral_pci_softc *psc = device_get_softc(dev); + + (*psc->sc_opns->resume)(psc); + + return 0; +} diff --git a/src/add-ons/kernel/drivers/network/wlan/ralinkwifi/dev/ral/rt2560.c b/src/add-ons/kernel/drivers/network/wlan/ralinkwifi/dev/ral/rt2560.c new file mode 100644 index 0000000000..455b5ad8e7 --- /dev/null +++ b/src/add-ons/kernel/drivers/network/wlan/ralinkwifi/dev/ral/rt2560.c @@ -0,0 +1,2841 @@ +/* $FreeBSD$ */ + +/*- + * Copyright (c) 2005, 2006 + * Damien Bergamini + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include +__FBSDID("$FreeBSD$"); + +/*- + * Ralink Technology RT2560 chipset driver + * http://www.ralinktech.com/ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include + +#define RT2560_RSSI(sc, rssi) \ + ((rssi) > (RT2560_NOISE_FLOOR + (sc)->rssi_corr) ? \ + ((rssi) - RT2560_NOISE_FLOOR - (sc)->rssi_corr) : 0) + +#define RAL_DEBUG +#ifdef RAL_DEBUG +#define DPRINTF(sc, fmt, ...) do { \ + if (sc->sc_debug > 0) \ + printf(fmt, __VA_ARGS__); \ +} while (0) +#define DPRINTFN(sc, n, fmt, ...) do { \ + if (sc->sc_debug >= (n)) \ + printf(fmt, __VA_ARGS__); \ +} while (0) +#else +#define DPRINTF(sc, fmt, ...) +#define DPRINTFN(sc, n, fmt, ...) +#endif + +static struct ieee80211vap *rt2560_vap_create(struct ieee80211com *, + const char name[IFNAMSIZ], int unit, int opmode, + int flags, const uint8_t bssid[IEEE80211_ADDR_LEN], + const uint8_t mac[IEEE80211_ADDR_LEN]); +static void rt2560_vap_delete(struct ieee80211vap *); +static void rt2560_dma_map_addr(void *, bus_dma_segment_t *, int, + int); +static int rt2560_alloc_tx_ring(struct rt2560_softc *, + struct rt2560_tx_ring *, int); +static void rt2560_reset_tx_ring(struct rt2560_softc *, + struct rt2560_tx_ring *); +static void rt2560_free_tx_ring(struct rt2560_softc *, + struct rt2560_tx_ring *); +static int rt2560_alloc_rx_ring(struct rt2560_softc *, + struct rt2560_rx_ring *, int); +static void rt2560_reset_rx_ring(struct rt2560_softc *, + struct rt2560_rx_ring *); +static void rt2560_free_rx_ring(struct rt2560_softc *, + struct rt2560_rx_ring *); +static struct ieee80211_node *rt2560_node_alloc(struct ieee80211vap *, + const uint8_t [IEEE80211_ADDR_LEN]); +static void rt2560_newassoc(struct ieee80211_node *, int); +static int rt2560_newstate(struct ieee80211vap *, + enum ieee80211_state, int); +static uint16_t rt2560_eeprom_read(struct rt2560_softc *, uint8_t); +static void rt2560_encryption_intr(struct rt2560_softc *); +static void rt2560_tx_intr(struct rt2560_softc *); +static void rt2560_prio_intr(struct rt2560_softc *); +static void rt2560_decryption_intr(struct rt2560_softc *); +static void rt2560_rx_intr(struct rt2560_softc *); +static void rt2560_beacon_update(struct ieee80211vap *, int item); +static void rt2560_beacon_expire(struct rt2560_softc *); +static void rt2560_wakeup_expire(struct rt2560_softc *); +static void rt2560_scan_start(struct ieee80211com *); +static void rt2560_scan_end(struct ieee80211com *); +static void rt2560_set_channel(struct ieee80211com *); +static void rt2560_setup_tx_desc(struct rt2560_softc *, + struct rt2560_tx_desc *, uint32_t, int, int, int, + bus_addr_t); +static int rt2560_tx_bcn(struct rt2560_softc *, struct mbuf *, + struct ieee80211_node *); +static int rt2560_tx_mgt(struct rt2560_softc *, struct mbuf *, + struct ieee80211_node *); +static int rt2560_tx_data(struct rt2560_softc *, struct mbuf *, + struct ieee80211_node *); +static void rt2560_start_locked(struct ifnet *); +static void rt2560_start(struct ifnet *); +static void rt2560_watchdog(void *); +static int rt2560_ioctl(struct ifnet *, u_long, caddr_t); +static void rt2560_bbp_write(struct rt2560_softc *, uint8_t, + uint8_t); +static uint8_t rt2560_bbp_read(struct rt2560_softc *, uint8_t); +static void rt2560_rf_write(struct rt2560_softc *, uint8_t, + uint32_t); +static void rt2560_set_chan(struct rt2560_softc *, + struct ieee80211_channel *); +#if 0 +static void rt2560_disable_rf_tune(struct rt2560_softc *); +#endif +static void rt2560_enable_tsf_sync(struct rt2560_softc *); +static void rt2560_enable_tsf(struct rt2560_softc *); +static void rt2560_update_plcp(struct rt2560_softc *); +static void rt2560_update_slot(struct ifnet *); +static void rt2560_set_basicrates(struct rt2560_softc *); +static void rt2560_update_led(struct rt2560_softc *, int, int); +static void rt2560_set_bssid(struct rt2560_softc *, const uint8_t *); +static void rt2560_set_macaddr(struct rt2560_softc *, uint8_t *); +static void rt2560_get_macaddr(struct rt2560_softc *, uint8_t *); +static void rt2560_update_promisc(struct ifnet *); +static const char *rt2560_get_rf(int); +static void rt2560_read_config(struct rt2560_softc *); +static int rt2560_bbp_init(struct rt2560_softc *); +static void rt2560_set_txantenna(struct rt2560_softc *, int); +static void rt2560_set_rxantenna(struct rt2560_softc *, int); +static void rt2560_init_locked(struct rt2560_softc *); +static void rt2560_init(void *); +static void rt2560_stop_locked(struct rt2560_softc *); +static int rt2560_raw_xmit(struct ieee80211_node *, struct mbuf *, + const struct ieee80211_bpf_params *); + +static const struct { + uint32_t reg; + uint32_t val; +} rt2560_def_mac[] = { + RT2560_DEF_MAC +}; + +static const struct { + uint8_t reg; + uint8_t val; +} rt2560_def_bbp[] = { + RT2560_DEF_BBP +}; + +static const uint32_t rt2560_rf2522_r2[] = RT2560_RF2522_R2; +static const uint32_t rt2560_rf2523_r2[] = RT2560_RF2523_R2; +static const uint32_t rt2560_rf2524_r2[] = RT2560_RF2524_R2; +static const uint32_t rt2560_rf2525_r2[] = RT2560_RF2525_R2; +static const uint32_t rt2560_rf2525_hi_r2[] = RT2560_RF2525_HI_R2; +static const uint32_t rt2560_rf2525e_r2[] = RT2560_RF2525E_R2; +static const uint32_t rt2560_rf2526_r2[] = RT2560_RF2526_R2; +static const uint32_t rt2560_rf2526_hi_r2[] = RT2560_RF2526_HI_R2; + +static const struct { + uint8_t chan; + uint32_t r1, r2, r4; +} rt2560_rf5222[] = { + RT2560_RF5222 +}; + +int +rt2560_attach(device_t dev, int id) +{ + struct rt2560_softc *sc = device_get_softc(dev); + struct ieee80211com *ic; + struct ifnet *ifp; + int error; + uint8_t bands; + uint8_t macaddr[IEEE80211_ADDR_LEN]; + + sc->sc_dev = dev; + + mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, + MTX_DEF | MTX_RECURSE); + + callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0); + + /* retrieve RT2560 rev. no */ + sc->asic_rev = RAL_READ(sc, RT2560_CSR0); + + /* retrieve RF rev. no and various other things from EEPROM */ + rt2560_read_config(sc); + + device_printf(dev, "MAC/BBP RT2560 (rev 0x%02x), RF %s\n", + sc->asic_rev, rt2560_get_rf(sc->rf_rev)); + + /* + * Allocate Tx and Rx rings. + */ + error = rt2560_alloc_tx_ring(sc, &sc->txq, RT2560_TX_RING_COUNT); + if (error != 0) { + device_printf(sc->sc_dev, "could not allocate Tx ring\n"); + goto fail1; + } + + error = rt2560_alloc_tx_ring(sc, &sc->atimq, RT2560_ATIM_RING_COUNT); + if (error != 0) { + device_printf(sc->sc_dev, "could not allocate ATIM ring\n"); + goto fail2; + } + + error = rt2560_alloc_tx_ring(sc, &sc->prioq, RT2560_PRIO_RING_COUNT); + if (error != 0) { + device_printf(sc->sc_dev, "could not allocate Prio ring\n"); + goto fail3; + } + + error = rt2560_alloc_tx_ring(sc, &sc->bcnq, RT2560_BEACON_RING_COUNT); + if (error != 0) { + device_printf(sc->sc_dev, "could not allocate Beacon ring\n"); + goto fail4; + } + + error = rt2560_alloc_rx_ring(sc, &sc->rxq, RT2560_RX_RING_COUNT); + if (error != 0) { + device_printf(sc->sc_dev, "could not allocate Rx ring\n"); + goto fail5; + } + + ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); + if (ifp == NULL) { + device_printf(sc->sc_dev, "can not if_alloc()\n"); + goto fail6; + } + ic = ifp->if_l2com; + + /* retrieve MAC address */ + rt2560_get_macaddr(sc, macaddr); + + ifp->if_softc = sc; + if_initname(ifp, device_get_name(dev), device_get_unit(dev)); + ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; + ifp->if_init = rt2560_init; + ifp->if_ioctl = rt2560_ioctl; + ifp->if_start = rt2560_start; + IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); + ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; + IFQ_SET_READY(&ifp->if_snd); + + ic->ic_ifp = ifp; + ic->ic_opmode = IEEE80211_M_STA; + ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ + + /* set device capabilities */ + ic->ic_caps = + IEEE80211_C_STA /* station mode */ + | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ + | IEEE80211_C_HOSTAP /* hostap mode */ + | IEEE80211_C_MONITOR /* monitor mode */ + | IEEE80211_C_AHDEMO /* adhoc demo mode */ + | IEEE80211_C_WDS /* 4-address traffic works */ + | IEEE80211_C_MBSS /* mesh point link mode */ + | IEEE80211_C_SHPREAMBLE /* short preamble supported */ + | IEEE80211_C_SHSLOT /* short slot time supported */ + | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ + | IEEE80211_C_BGSCAN /* capable of bg scanning */ +#ifdef notyet + | IEEE80211_C_TXFRAG /* handle tx frags */ +#endif + ; + + bands = 0; + setbit(&bands, IEEE80211_MODE_11B); + setbit(&bands, IEEE80211_MODE_11G); + if (sc->rf_rev == RT2560_RF_5222) + setbit(&bands, IEEE80211_MODE_11A); + ieee80211_init_channels(ic, NULL, &bands); + + ieee80211_ifattach(ic, macaddr); + ic->ic_newassoc = rt2560_newassoc; + ic->ic_raw_xmit = rt2560_raw_xmit; + ic->ic_updateslot = rt2560_update_slot; + ic->ic_update_promisc = rt2560_update_promisc; + ic->ic_node_alloc = rt2560_node_alloc; + ic->ic_scan_start = rt2560_scan_start; + ic->ic_scan_end = rt2560_scan_end; + ic->ic_set_channel = rt2560_set_channel; + + ic->ic_vap_create = rt2560_vap_create; + ic->ic_vap_delete = rt2560_vap_delete; + + ieee80211_radiotap_attach(ic, + &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), + RT2560_TX_RADIOTAP_PRESENT, + &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), + RT2560_RX_RADIOTAP_PRESENT); + + /* + * Add a few sysctl knobs. + */ +#ifdef RAL_DEBUG + SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), + SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, + "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs"); +#endif + SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), + SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, + "txantenna", CTLFLAG_RW, &sc->tx_ant, 0, "tx antenna (0=auto)"); + + SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), + SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, + "rxantenna", CTLFLAG_RW, &sc->rx_ant, 0, "rx antenna (0=auto)"); + + if (bootverbose) + ieee80211_announce(ic); + + return 0; + +fail6: rt2560_free_rx_ring(sc, &sc->rxq); +fail5: rt2560_free_tx_ring(sc, &sc->bcnq); +fail4: rt2560_free_tx_ring(sc, &sc->prioq); +fail3: rt2560_free_tx_ring(sc, &sc->atimq); +fail2: rt2560_free_tx_ring(sc, &sc->txq); +fail1: mtx_destroy(&sc->sc_mtx); + + return ENXIO; +} + +int +rt2560_detach(void *xsc) +{ + struct rt2560_softc *sc = xsc; + struct ifnet *ifp = sc->sc_ifp; + struct ieee80211com *ic = ifp->if_l2com; + + rt2560_stop(sc); + + ieee80211_ifdetach(ic); + + rt2560_free_tx_ring(sc, &sc->txq); + rt2560_free_tx_ring(sc, &sc->atimq); + rt2560_free_tx_ring(sc, &sc->prioq); + rt2560_free_tx_ring(sc, &sc->bcnq); + rt2560_free_rx_ring(sc, &sc->rxq); + + if_free(ifp); + + mtx_destroy(&sc->sc_mtx); + + return 0; +} + +static struct ieee80211vap * +rt2560_vap_create(struct ieee80211com *ic, + const char name[IFNAMSIZ], int unit, int opmode, int flags, + const uint8_t bssid[IEEE80211_ADDR_LEN], + const uint8_t mac[IEEE80211_ADDR_LEN]) +{ + struct ifnet *ifp = ic->ic_ifp; + struct rt2560_vap *rvp; + struct ieee80211vap *vap; + + switch (opmode) { + case IEEE80211_M_STA: + case IEEE80211_M_IBSS: + case IEEE80211_M_AHDEMO: + case IEEE80211_M_MONITOR: + case IEEE80211_M_HOSTAP: + case IEEE80211_M_MBSS: + /* XXXRP: TBD */ + if (!TAILQ_EMPTY(&ic->ic_vaps)) { + if_printf(ifp, "only 1 vap supported\n"); + return NULL; + } + if (opmode == IEEE80211_M_STA) + flags |= IEEE80211_CLONE_NOBEACONS; + break; + case IEEE80211_M_WDS: + if (TAILQ_EMPTY(&ic->ic_vaps) || + ic->ic_opmode != IEEE80211_M_HOSTAP) { + if_printf(ifp, "wds only supported in ap mode\n"); + return NULL; + } + /* + * Silently remove any request for a unique + * bssid; WDS vap's always share the local + * mac address. + */ + flags &= ~IEEE80211_CLONE_BSSID; + break; + default: + if_printf(ifp, "unknown opmode %d\n", opmode); + return NULL; + } + rvp = (struct rt2560_vap *) malloc(sizeof(struct rt2560_vap), + M_80211_VAP, M_NOWAIT | M_ZERO); + if (rvp == NULL) + return NULL; + vap = &rvp->ral_vap; + ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid, mac); + + /* override state transition machine */ + rvp->ral_newstate = vap->iv_newstate; + vap->iv_newstate = rt2560_newstate; + vap->iv_update_beacon = rt2560_beacon_update; + + ieee80211_amrr_init(&rvp->amrr, vap, + IEEE80211_AMRR_MIN_SUCCESS_THRESHOLD, + IEEE80211_AMRR_MAX_SUCCESS_THRESHOLD, + 500 /* ms */); + + /* complete setup */ + ieee80211_vap_attach(vap, ieee80211_media_change, ieee80211_media_status); + if (TAILQ_FIRST(&ic->ic_vaps) == vap) + ic->ic_opmode = opmode; + return vap; +} + +static void +rt2560_vap_delete(struct ieee80211vap *vap) +{ + struct rt2560_vap *rvp = RT2560_VAP(vap); + + ieee80211_amrr_cleanup(&rvp->amrr); + ieee80211_vap_detach(vap); + free(rvp, M_80211_VAP); +} + +void +rt2560_resume(void *xsc) +{ + struct rt2560_softc *sc = xsc; + struct ifnet *ifp = sc->sc_ifp; + + if (ifp->if_flags & IFF_UP) + rt2560_init(sc); +} + +static void +rt2560_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) +{ + if (error != 0) + return; + + KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); + + *(bus_addr_t *)arg = segs[0].ds_addr; +} + +static int +rt2560_alloc_tx_ring(struct rt2560_softc *sc, struct rt2560_tx_ring *ring, + int count) +{ + int i, error; + + ring->count = count; + ring->queued = 0; + ring->cur = ring->next = 0; + ring->cur_encrypt = ring->next_encrypt = 0; + + error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0, + BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, + count * RT2560_TX_DESC_SIZE, 1, count * RT2560_TX_DESC_SIZE, + 0, NULL, NULL, &ring->desc_dmat); + if (error != 0) { + device_printf(sc->sc_dev, "could not create desc DMA tag\n"); + goto fail; + } + + error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, + BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); + if (error != 0) { + device_printf(sc->sc_dev, "could not allocate DMA memory\n"); + goto fail; + } + + error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, + count * RT2560_TX_DESC_SIZE, rt2560_dma_map_addr, &ring->physaddr, + 0); + if (error != 0) { + device_printf(sc->sc_dev, "could not load desc DMA map\n"); + goto fail; + } + + ring->data = malloc(count * sizeof (struct rt2560_tx_data), M_DEVBUF, + M_NOWAIT | M_ZERO); + if (ring->data == NULL) { + device_printf(sc->sc_dev, "could not allocate soft data\n"); + error = ENOMEM; + goto fail; + } + + error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, + BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, + MCLBYTES, RT2560_MAX_SCATTER, MCLBYTES, 0, NULL, NULL, + &ring->data_dmat); + if (error != 0) { + device_printf(sc->sc_dev, "could not create data DMA tag\n"); + goto fail; + } + + for (i = 0; i < count; i++) { + error = bus_dmamap_create(ring->data_dmat, 0, + &ring->data[i].map); + if (error != 0) { + device_printf(sc->sc_dev, "could not create DMA map\n"); + goto fail; + } + } + + return 0; + +fail: rt2560_free_tx_ring(sc, ring); + return error; +} + +static void +rt2560_reset_tx_ring(struct rt2560_softc *sc, struct rt2560_tx_ring *ring) +{ + struct rt2560_tx_desc *desc; + struct rt2560_tx_data *data; + int i; + + for (i = 0; i < ring->count; i++) { + desc = &ring->desc[i]; + data = &ring->data[i]; + + if (data->m != NULL) { + bus_dmamap_sync(ring->data_dmat, data->map, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(ring->data_dmat, data->map); + m_freem(data->m); + data->m = NULL; + } + + if (data->ni != NULL) { + ieee80211_free_node(data->ni); + data->ni = NULL; + } + + desc->flags = 0; + } + + bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); + + ring->queued = 0; + ring->cur = ring->next = 0; + ring->cur_encrypt = ring->next_encrypt = 0; +} + +static void +rt2560_free_tx_ring(struct rt2560_softc *sc, struct rt2560_tx_ring *ring) +{ + struct rt2560_tx_data *data; + int i; + + if (ring->desc != NULL) { + bus_dmamap_sync(ring->desc_dmat, ring->desc_map, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(ring->desc_dmat, ring->desc_map); + bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); + } + + if (ring->desc_dmat != NULL) + bus_dma_tag_destroy(ring->desc_dmat); + + if (ring->data != NULL) { + for (i = 0; i < ring->count; i++) { + data = &ring->data[i]; + + if (data->m != NULL) { + bus_dmamap_sync(ring->data_dmat, data->map, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(ring->data_dmat, data->map); + m_freem(data->m); + } + + if (data->ni != NULL) + ieee80211_free_node(data->ni); + + if (data->map != NULL) + bus_dmamap_destroy(ring->data_dmat, data->map); + } + + free(ring->data, M_DEVBUF); + } + + if (ring->data_dmat != NULL) + bus_dma_tag_destroy(ring->data_dmat); +} + +static int +rt2560_alloc_rx_ring(struct rt2560_softc *sc, struct rt2560_rx_ring *ring, + int count) +{ + struct rt2560_rx_desc *desc; + struct rt2560_rx_data *data; + bus_addr_t physaddr; + int i, error; + + ring->count = count; + ring->cur = ring->next = 0; + ring->cur_decrypt = 0; + + error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0, + BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, + count * RT2560_RX_DESC_SIZE, 1, count * RT2560_RX_DESC_SIZE, + 0, NULL, NULL, &ring->desc_dmat); + if (error != 0) { + device_printf(sc->sc_dev, "could not create desc DMA tag\n"); + goto fail; + } + + error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, + BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); + if (error != 0) { + device_printf(sc->sc_dev, "could not allocate DMA memory\n"); + goto fail; + } + + error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, + count * RT2560_RX_DESC_SIZE, rt2560_dma_map_addr, &ring->physaddr, + 0); + if (error != 0) { + device_printf(sc->sc_dev, "could not load desc DMA map\n"); + goto fail; + } + + ring->data = malloc(count * sizeof (struct rt2560_rx_data), M_DEVBUF, + M_NOWAIT | M_ZERO); + if (ring->data == NULL) { + device_printf(sc->sc_dev, "could not allocate soft data\n"); + error = ENOMEM; + goto fail; + } + + /* + * Pre-allocate Rx buffers and populate Rx ring. + */ + error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, + BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, + 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); + if (error != 0) { + device_printf(sc->sc_dev, "could not create data DMA tag\n"); + goto fail; + } + + for (i = 0; i < count; i++) { + desc = &sc->rxq.desc[i]; + data = &sc->rxq.data[i]; + + error = bus_dmamap_create(ring->data_dmat, 0, &data->map); + if (error != 0) { + device_printf(sc->sc_dev, "could not create DMA map\n"); + goto fail; + } + + data->m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + if (data->m == NULL) { + device_printf(sc->sc_dev, + "could not allocate rx mbuf\n"); + error = ENOMEM; + goto fail; + } + + error = bus_dmamap_load(ring->data_dmat, data->map, + mtod(data->m, void *), MCLBYTES, rt2560_dma_map_addr, + &physaddr, 0); + if (error != 0) { + device_printf(sc->sc_dev, + "could not load rx buf DMA map"); + goto fail; + } + + desc->flags = htole32(RT2560_RX_BUSY); + desc->physaddr = htole32(physaddr); + } + + bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); + + return 0; + +fail: rt2560_free_rx_ring(sc, ring); + return error; +} + +static void +rt2560_reset_rx_ring(struct rt2560_softc *sc, struct rt2560_rx_ring *ring) +{ + int i; + + for (i = 0; i < ring->count; i++) { + ring->desc[i].flags = htole32(RT2560_RX_BUSY); + ring->data[i].drop = 0; + } + + bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); + + ring->cur = ring->next = 0; + ring->cur_decrypt = 0; +} + +static void +rt2560_free_rx_ring(struct rt2560_softc *sc, struct rt2560_rx_ring *ring) +{ + struct rt2560_rx_data *data; + int i; + + if (ring->desc != NULL) { + bus_dmamap_sync(ring->desc_dmat, ring->desc_map, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(ring->desc_dmat, ring->desc_map); + bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); + } + + if (ring->desc_dmat != NULL) + bus_dma_tag_destroy(ring->desc_dmat); + + if (ring->data != NULL) { + for (i = 0; i < ring->count; i++) { + data = &ring->data[i]; + + if (data->m != NULL) { + bus_dmamap_sync(ring->data_dmat, data->map, + BUS_DMASYNC_POSTREAD); + bus_dmamap_unload(ring->data_dmat, data->map); + m_freem(data->m); + } + + if (data->map != NULL) + bus_dmamap_destroy(ring->data_dmat, data->map); + } + + free(ring->data, M_DEVBUF); + } + + if (ring->data_dmat != NULL) + bus_dma_tag_destroy(ring->data_dmat); +} + +static struct ieee80211_node * +rt2560_node_alloc(struct ieee80211vap *vap, + const uint8_t mac[IEEE80211_ADDR_LEN]) +{ + struct rt2560_node *rn; + + rn = malloc(sizeof (struct rt2560_node), M_80211_NODE, + M_NOWAIT | M_ZERO); + + return (rn != NULL) ? &rn->ni : NULL; +} + +static void +rt2560_newassoc(struct ieee80211_node *ni, int isnew) +{ + struct ieee80211vap *vap = ni->ni_vap; + + ieee80211_amrr_node_init(&RT2560_VAP(vap)->amrr, + &RT2560_NODE(ni)->amrr, ni); +} + +static int +rt2560_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) +{ + struct rt2560_vap *rvp = RT2560_VAP(vap); + struct ifnet *ifp = vap->iv_ic->ic_ifp; + struct rt2560_softc *sc = ifp->if_softc; + int error; + + if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) { + /* abort TSF synchronization */ + RAL_WRITE(sc, RT2560_CSR14, 0); + + /* turn association led off */ + rt2560_update_led(sc, 0, 0); + } + + error = rvp->ral_newstate(vap, nstate, arg); + + if (error == 0 && nstate == IEEE80211_S_RUN) { + struct ieee80211_node *ni = vap->iv_bss; + struct mbuf *m; + + if (vap->iv_opmode != IEEE80211_M_MONITOR) { + rt2560_update_plcp(sc); + rt2560_set_basicrates(sc); + rt2560_set_bssid(sc, ni->ni_bssid); + } + + if (vap->iv_opmode == IEEE80211_M_HOSTAP || + vap->iv_opmode == IEEE80211_M_IBSS || + vap->iv_opmode == IEEE80211_M_MBSS) { + m = ieee80211_beacon_alloc(ni, &rvp->ral_bo); + if (m == NULL) { + if_printf(ifp, "could not allocate beacon\n"); + return ENOBUFS; + } + ieee80211_ref_node(ni); + error = rt2560_tx_bcn(sc, m, ni); + if (error != 0) + return error; + } + + /* turn assocation led on */ + rt2560_update_led(sc, 1, 0); + + if (vap->iv_opmode != IEEE80211_M_MONITOR) + rt2560_enable_tsf_sync(sc); + else + rt2560_enable_tsf(sc); + } + return error; +} + +/* + * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or + * 93C66). + */ +static uint16_t +rt2560_eeprom_read(struct rt2560_softc *sc, uint8_t addr) +{ + uint32_t tmp; + uint16_t val; + int n; + + /* clock C once before the first command */ + RT2560_EEPROM_CTL(sc, 0); + + RT2560_EEPROM_CTL(sc, RT2560_S); + RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_C); + RT2560_EEPROM_CTL(sc, RT2560_S); + + /* write start bit (1) */ + RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_D); + RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_D | RT2560_C); + + /* write READ opcode (10) */ + RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_D); + RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_D | RT2560_C); + RT2560_EEPROM_CTL(sc, RT2560_S); + RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_C); + + /* write address (A5-A0 or A7-A0) */ + n = (RAL_READ(sc, RT2560_CSR21) & RT2560_93C46) ? 5 : 7; + for (; n >= 0; n--) { + RT2560_EEPROM_CTL(sc, RT2560_S | + (((addr >> n) & 1) << RT2560_SHIFT_D)); + RT2560_EEPROM_CTL(sc, RT2560_S | + (((addr >> n) & 1) << RT2560_SHIFT_D) | RT2560_C); + } + + RT2560_EEPROM_CTL(sc, RT2560_S); + + /* read data Q15-Q0 */ + val = 0; + for (n = 15; n >= 0; n--) { + RT2560_EEPROM_CTL(sc, RT2560_S | RT2560_C); + tmp = RAL_READ(sc, RT2560_CSR21); + val |= ((tmp & RT2560_Q) >> RT2560_SHIFT_Q) << n; + RT2560_EEPROM_CTL(sc, RT2560_S); + } + + RT2560_EEPROM_CTL(sc, 0); + + /* clear Chip Select and clock C */ + RT2560_EEPROM_CTL(sc, RT2560_S); + RT2560_EEPROM_CTL(sc, 0); + RT2560_EEPROM_CTL(sc, RT2560_C); + + return val; +} + +/* + * Some frames were processed by the hardware cipher engine and are ready for + * transmission. + */ +static void +rt2560_encryption_intr(struct rt2560_softc *sc) +{ + struct rt2560_tx_desc *desc; + int hw; + + /* retrieve last descriptor index processed by cipher engine */ + hw = RAL_READ(sc, RT2560_SECCSR1) - sc->txq.physaddr; + hw /= RT2560_TX_DESC_SIZE; + + bus_dmamap_sync(sc->txq.desc_dmat, sc->txq.desc_map, + BUS_DMASYNC_POSTREAD); + + while (sc->txq.next_encrypt != hw) { + if (sc->txq.next_encrypt == sc->txq.cur_encrypt) { + printf("hw encrypt %d, cur_encrypt %d\n", hw, + sc->txq.cur_encrypt); + break; + } + + desc = &sc->txq.desc[sc->txq.next_encrypt]; + + if ((le32toh(desc->flags) & RT2560_TX_BUSY) || + (le32toh(desc->flags) & RT2560_TX_CIPHER_BUSY)) + break; + + /* for TKIP, swap eiv field to fix a bug in ASIC */ + if ((le32toh(desc->flags) & RT2560_TX_CIPHER_MASK) == + RT2560_TX_CIPHER_TKIP) + desc->eiv = bswap32(desc->eiv); + + /* mark the frame ready for transmission */ + desc->flags |= htole32(RT2560_TX_VALID); + desc->flags |= htole32(RT2560_TX_BUSY); + + DPRINTFN(sc, 15, "encryption done idx=%u\n", + sc->txq.next_encrypt); + + sc->txq.next_encrypt = + (sc->txq.next_encrypt + 1) % RT2560_TX_RING_COUNT; + } + + bus_dmamap_sync(sc->txq.desc_dmat, sc->txq.desc_map, + BUS_DMASYNC_PREWRITE); + + /* kick Tx */ + RAL_WRITE(sc, RT2560_TXCSR0, RT2560_KICK_TX); +} + +static void +rt2560_tx_intr(struct rt2560_softc *sc) +{ + struct ifnet *ifp = sc->sc_ifp; + struct rt2560_tx_desc *desc; + struct rt2560_tx_data *data; + struct rt2560_node *rn; + struct mbuf *m; + uint32_t flags; + int retrycnt; + + bus_dmamap_sync(sc->txq.desc_dmat, sc->txq.desc_map, + BUS_DMASYNC_POSTREAD); + + for (;;) { + desc = &sc->txq.desc[sc->txq.next]; + data = &sc->txq.data[sc->txq.next]; + + flags = le32toh(desc->flags); + if ((flags & RT2560_TX_BUSY) || + (flags & RT2560_TX_CIPHER_BUSY) || + !(flags & RT2560_TX_VALID)) + break; + + rn = (struct rt2560_node *)data->ni; + m = data->m; + + switch (flags & RT2560_TX_RESULT_MASK) { + case RT2560_TX_SUCCESS: + DPRINTFN(sc, 10, "%s\n", "data frame sent successfully"); + if (data->rix != IEEE80211_FIXED_RATE_NONE) + ieee80211_amrr_tx_complete(&rn->amrr, + IEEE80211_AMRR_SUCCESS, 0); + ifp->if_opackets++; + break; + + case RT2560_TX_SUCCESS_RETRY: + retrycnt = RT2560_TX_RETRYCNT(flags); + + DPRINTFN(sc, 9, "data frame sent after %u retries\n", + retrycnt); + if (data->rix != IEEE80211_FIXED_RATE_NONE) + ieee80211_amrr_tx_complete(&rn->amrr, + IEEE80211_AMRR_SUCCESS, retrycnt); + ifp->if_opackets++; + break; + + case RT2560_TX_FAIL_RETRY: + retrycnt = RT2560_TX_RETRYCNT(flags); + + DPRINTFN(sc, 9, "data frame failed after %d retries\n", + retrycnt); + if (data->rix != IEEE80211_FIXED_RATE_NONE) + ieee80211_amrr_tx_complete(&rn->amrr, + IEEE80211_AMRR_FAILURE, retrycnt); + ifp->if_oerrors++; + break; + + case RT2560_TX_FAIL_INVALID: + case RT2560_TX_FAIL_OTHER: + default: + device_printf(sc->sc_dev, "sending data frame failed " + "0x%08x\n", flags); + ifp->if_oerrors++; + } + + bus_dmamap_sync(sc->txq.data_dmat, data->map, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(sc->txq.data_dmat, data->map); + m_freem(m); + data->m = NULL; + ieee80211_free_node(data->ni); + data->ni = NULL; + + /* descriptor is no longer valid */ + desc->flags &= ~htole32(RT2560_TX_VALID); + + DPRINTFN(sc, 15, "tx done idx=%u\n", sc->txq.next); + + sc->txq.queued--; + sc->txq.next = (sc->txq.next + 1) % RT2560_TX_RING_COUNT; + } + + bus_dmamap_sync(sc->txq.desc_dmat, sc->txq.desc_map, + BUS_DMASYNC_PREWRITE); + + if (sc->prioq.queued == 0 && sc->txq.queued == 0) + sc->sc_tx_timer = 0; + + if (sc->txq.queued < RT2560_TX_RING_COUNT - 1) { + sc->sc_flags &= ~RT2560_F_DATA_OACTIVE; + if ((sc->sc_flags & + (RT2560_F_DATA_OACTIVE | RT2560_F_PRIO_OACTIVE)) == 0) + ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; + rt2560_start_locked(ifp); + } +} + +static void +rt2560_prio_intr(struct rt2560_softc *sc) +{ + struct ifnet *ifp = sc->sc_ifp; + struct rt2560_tx_desc *desc; + struct rt2560_tx_data *data; + struct ieee80211_node *ni; + struct mbuf *m; + int flags; + + bus_dmamap_sync(sc->prioq.desc_dmat, sc->prioq.desc_map, + BUS_DMASYNC_POSTREAD); + + for (;;) { + desc = &sc->prioq.desc[sc->prioq.next]; + data = &sc->prioq.data[sc->prioq.next]; + + flags = le32toh(desc->flags); + if ((flags & RT2560_TX_BUSY) || (flags & RT2560_TX_VALID) == 0) + break; + + switch (flags & RT2560_TX_RESULT_MASK) { + case RT2560_TX_SUCCESS: + DPRINTFN(sc, 10, "%s\n", "mgt frame sent successfully"); + break; + + case RT2560_TX_SUCCESS_RETRY: + DPRINTFN(sc, 9, "mgt frame sent after %u retries\n", + (flags >> 5) & 0x7); + break; + + case RT2560_TX_FAIL_RETRY: + DPRINTFN(sc, 9, "%s\n", + "sending mgt frame failed (too much retries)"); + break; + + case RT2560_TX_FAIL_INVALID: + case RT2560_TX_FAIL_OTHER: + default: + device_printf(sc->sc_dev, "sending mgt frame failed " + "0x%08x\n", flags); + break; + } + + bus_dmamap_sync(sc->prioq.data_dmat, data->map, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(sc->prioq.data_dmat, data->map); + + m = data->m; + data->m = NULL; + ni = data->ni; + data->ni = NULL; + + /* descriptor is no longer valid */ + desc->flags &= ~htole32(RT2560_TX_VALID); + + DPRINTFN(sc, 15, "prio done idx=%u\n", sc->prioq.next); + + sc->prioq.queued--; + sc->prioq.next = (sc->prioq.next + 1) % RT2560_PRIO_RING_COUNT; + + if (m->m_flags & M_TXCB) + ieee80211_process_callback(ni, m, + (flags & RT2560_TX_RESULT_MASK) &~ + (RT2560_TX_SUCCESS | RT2560_TX_SUCCESS_RETRY)); + m_freem(m); + ieee80211_free_node(ni); + } + + bus_dmamap_sync(sc->prioq.desc_dmat, sc->prioq.desc_map, + BUS_DMASYNC_PREWRITE); + + if (sc->prioq.queued == 0 && sc->txq.queued == 0) + sc->sc_tx_timer = 0; + + if (sc->prioq.queued < RT2560_PRIO_RING_COUNT) { + sc->sc_flags &= ~RT2560_F_PRIO_OACTIVE; + if ((sc->sc_flags & + (RT2560_F_DATA_OACTIVE | RT2560_F_PRIO_OACTIVE)) == 0) + ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; + rt2560_start_locked(ifp); + } +} + +/* + * Some frames were processed by the hardware cipher engine and are ready for + * handoff to the IEEE802.11 layer. + */ +static void +rt2560_decryption_intr(struct rt2560_softc *sc) +{ + struct ifnet *ifp = sc->sc_ifp; + struct ieee80211com *ic = ifp->if_l2com; + struct rt2560_rx_desc *desc; + struct rt2560_rx_data *data; + bus_addr_t physaddr; + struct ieee80211_frame *wh; + struct ieee80211_node *ni; + struct mbuf *mnew, *m; + int hw, error; + int8_t rssi, nf; + + /* retrieve last decriptor index processed by cipher engine */ + hw = RAL_READ(sc, RT2560_SECCSR0) - sc->rxq.physaddr; + hw /= RT2560_RX_DESC_SIZE; + + bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, + BUS_DMASYNC_POSTREAD); + + for (; sc->rxq.cur_decrypt != hw;) { + desc = &sc->rxq.desc[sc->rxq.cur_decrypt]; + data = &sc->rxq.data[sc->rxq.cur_decrypt]; + + if ((le32toh(desc->flags) & RT2560_RX_BUSY) || + (le32toh(desc->flags) & RT2560_RX_CIPHER_BUSY)) + break; + + if (data->drop) { + ifp->if_ierrors++; + goto skip; + } + + if ((le32toh(desc->flags) & RT2560_RX_CIPHER_MASK) != 0 && + (le32toh(desc->flags) & RT2560_RX_ICV_ERROR)) { + ifp->if_ierrors++; + goto skip; + } + + /* + * Try to allocate a new mbuf for this ring element and load it + * before processing the current mbuf. If the ring element + * cannot be loaded, drop the received packet and reuse the old + * mbuf. In the unlikely case that the old mbuf can't be + * reloaded either, explicitly panic. + */ + mnew = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + if (mnew == NULL) { + ifp->if_ierrors++; + goto skip; + } + + bus_dmamap_sync(sc->rxq.data_dmat, data->map, + BUS_DMASYNC_POSTREAD); + bus_dmamap_unload(sc->rxq.data_dmat, data->map); + + error = bus_dmamap_load(sc->rxq.data_dmat, data->map, + mtod(mnew, void *), MCLBYTES, rt2560_dma_map_addr, + &physaddr, 0); + if (error != 0) { + m_freem(mnew); + + /* try to reload the old mbuf */ + error = bus_dmamap_load(sc->rxq.data_dmat, data->map, + mtod(data->m, void *), MCLBYTES, + rt2560_dma_map_addr, &physaddr, 0); + if (error != 0) { + /* very unlikely that it will fail... */ + panic("%s: could not load old rx mbuf", + device_get_name(sc->sc_dev)); + } + ifp->if_ierrors++; + goto skip; + } + + /* + * New mbuf successfully loaded, update Rx ring and continue + * processing. + */ + m = data->m; + data->m = mnew; + desc->physaddr = htole32(physaddr); + + /* finalize mbuf */ + m->m_pkthdr.rcvif = ifp; + m->m_pkthdr.len = m->m_len = + (le32toh(desc->flags) >> 16) & 0xfff; + + rssi = RT2560_RSSI(sc, desc->rssi); + nf = RT2560_NOISE_FLOOR; + if (ieee80211_radiotap_active(ic)) { + struct rt2560_rx_radiotap_header *tap = &sc->sc_rxtap; + uint32_t tsf_lo, tsf_hi; + + /* get timestamp (low and high 32 bits) */ + tsf_hi = RAL_READ(sc, RT2560_CSR17); + tsf_lo = RAL_READ(sc, RT2560_CSR16); + + tap->wr_tsf = + htole64(((uint64_t)tsf_hi << 32) | tsf_lo); + tap->wr_flags = 0; + tap->wr_rate = ieee80211_plcp2rate(desc->rate, + (desc->flags & htole32(RT2560_RX_OFDM)) ? + IEEE80211_T_OFDM : IEEE80211_T_CCK); + tap->wr_antenna = sc->rx_ant; + tap->wr_antsignal = nf + rssi; + tap->wr_antnoise = nf; + } + + sc->sc_flags |= RT2560_F_INPUT_RUNNING; + RAL_UNLOCK(sc); + wh = mtod(m, struct ieee80211_frame *); + ni = ieee80211_find_rxnode(ic, + (struct ieee80211_frame_min *)wh); + if (ni != NULL) { + (void) ieee80211_input(ni, m, rssi, nf); + ieee80211_free_node(ni); + } else + (void) ieee80211_input_all(ic, m, rssi, nf); + + RAL_LOCK(sc); + sc->sc_flags &= ~RT2560_F_INPUT_RUNNING; +skip: desc->flags = htole32(RT2560_RX_BUSY); + + DPRINTFN(sc, 15, "decryption done idx=%u\n", sc->rxq.cur_decrypt); + + sc->rxq.cur_decrypt = + (sc->rxq.cur_decrypt + 1) % RT2560_RX_RING_COUNT; + } + + bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, + BUS_DMASYNC_PREWRITE); +} + +/* + * Some frames were received. Pass them to the hardware cipher engine before + * sending them to the 802.11 layer. + */ +static void +rt2560_rx_intr(struct rt2560_softc *sc) +{ + struct rt2560_rx_desc *desc; + struct rt2560_rx_data *data; + + bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, + BUS_DMASYNC_POSTREAD); + + for (;;) { + desc = &sc->rxq.desc[sc->rxq.cur]; + data = &sc->rxq.data[sc->rxq.cur]; + + if ((le32toh(desc->flags) & RT2560_RX_BUSY) || + (le32toh(desc->flags) & RT2560_RX_CIPHER_BUSY)) + break; + + data->drop = 0; + + if ((le32toh(desc->flags) & RT2560_RX_PHY_ERROR) || + (le32toh(desc->flags) & RT2560_RX_CRC_ERROR)) { + /* + * This should not happen since we did not request + * to receive those frames when we filled RXCSR0. + */ + DPRINTFN(sc, 5, "PHY or CRC error flags 0x%08x\n", + le32toh(desc->flags)); + data->drop = 1; + } + + if (((le32toh(desc->flags) >> 16) & 0xfff) > MCLBYTES) { + DPRINTFN(sc, 5, "%s\n", "bad length"); + data->drop = 1; + } + + /* mark the frame for decryption */ + desc->flags |= htole32(RT2560_RX_CIPHER_BUSY); + + DPRINTFN(sc, 15, "rx done idx=%u\n", sc->rxq.cur); + + sc->rxq.cur = (sc->rxq.cur + 1) % RT2560_RX_RING_COUNT; + } + + bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, + BUS_DMASYNC_PREWRITE); + + /* kick decrypt */ + RAL_WRITE(sc, RT2560_SECCSR0, RT2560_KICK_DECRYPT); +} + +static void +rt2560_beacon_update(struct ieee80211vap *vap, int item) +{ + struct rt2560_vap *rvp = RT2560_VAP(vap); + struct ieee80211_beacon_offsets *bo = &rvp->ral_bo; + + setbit(bo->bo_flags, item); +} + +/* + * This function is called periodically in IBSS mode when a new beacon must be + * sent out. + */ +static void +rt2560_beacon_expire(struct rt2560_softc *sc) +{ + struct ifnet *ifp = sc->sc_ifp; + struct ieee80211com *ic = ifp->if_l2com; + struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); + struct rt2560_vap *rvp = RT2560_VAP(vap); + struct rt2560_tx_data *data; + + if (ic->ic_opmode != IEEE80211_M_IBSS && + ic->ic_opmode != IEEE80211_M_HOSTAP && + ic->ic_opmode != IEEE80211_M_MBSS) + return; + + data = &sc->bcnq.data[sc->bcnq.next]; + /* + * Don't send beacon if bsschan isn't set + */ + if (data->ni == NULL) + return; + + bus_dmamap_sync(sc->bcnq.data_dmat, data->map, BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(sc->bcnq.data_dmat, data->map); + + /* XXX 1 =>'s mcast frames which means all PS sta's will wakeup! */ + ieee80211_beacon_update(data->ni, &rvp->ral_bo, data->m, 1); + + rt2560_tx_bcn(sc, data->m, data->ni); + + DPRINTFN(sc, 15, "%s", "beacon expired\n"); + + sc->bcnq.next = (sc->bcnq.next + 1) % RT2560_BEACON_RING_COUNT; +} + +/* ARGSUSED */ +static void +rt2560_wakeup_expire(struct rt2560_softc *sc) +{ + DPRINTFN(sc, 2, "%s", "wakeup expired\n"); +} + +void +rt2560_intr(void *arg) +{ + struct rt2560_softc *sc = arg; + struct ifnet *ifp = sc->sc_ifp; + uint32_t r; + + RAL_LOCK(sc); + + /* disable interrupts */ + RAL_WRITE(sc, RT2560_CSR8, 0xffffffff); + + /* don't re-enable interrupts if we're shutting down */ + if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { + RAL_UNLOCK(sc); + return; + } + + r = RAL_READ(sc, RT2560_CSR7); + RAL_WRITE(sc, RT2560_CSR7, r); + + if (r & RT2560_BEACON_EXPIRE) + rt2560_beacon_expire(sc); + + if (r & RT2560_WAKEUP_EXPIRE) + rt2560_wakeup_expire(sc); + + if (r & RT2560_ENCRYPTION_DONE) + rt2560_encryption_intr(sc); + + if (r & RT2560_TX_DONE) + rt2560_tx_intr(sc); + + if (r & RT2560_PRIO_DONE) + rt2560_prio_intr(sc); + + if (r & RT2560_DECRYPTION_DONE) + rt2560_decryption_intr(sc); + + if (r & RT2560_RX_DONE) { + rt2560_rx_intr(sc); + rt2560_encryption_intr(sc); + } + + /* re-enable interrupts */ + RAL_WRITE(sc, RT2560_CSR8, RT2560_INTR_MASK); + + RAL_UNLOCK(sc); +} + +#define RAL_SIFS 10 /* us */ + +#define RT2560_TXRX_TURNAROUND 10 /* us */ + +static uint8_t +rt2560_plcp_signal(int rate) +{ + switch (rate) { + /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ + case 12: return 0xb; + case 18: return 0xf; + case 24: return 0xa; + case 36: return 0xe; + case 48: return 0x9; + case 72: return 0xd; + case 96: return 0x8; + case 108: return 0xc; + + /* CCK rates (NB: not IEEE std, device-specific) */ + case 2: return 0x0; + case 4: return 0x1; + case 11: return 0x2; + case 22: return 0x3; + } + return 0xff; /* XXX unsupported/unknown rate */ +} + +static void +rt2560_setup_tx_desc(struct rt2560_softc *sc, struct rt2560_tx_desc *desc, + uint32_t flags, int len, int rate, int encrypt, bus_addr_t physaddr) +{ + struct ifnet *ifp = sc->sc_ifp; + struct ieee80211com *ic = ifp->if_l2com; + uint16_t plcp_length; + int remainder; + + desc->flags = htole32(flags); + desc->flags |= htole32(len << 16); + + desc->physaddr = htole32(physaddr); + desc->wme = htole16( + RT2560_AIFSN(2) | + RT2560_LOGCWMIN(3) | + RT2560_LOGCWMAX(8)); + + /* setup PLCP fields */ + desc->plcp_signal = rt2560_plcp_signal(rate); + desc->plcp_service = 4; + + len += IEEE80211_CRC_LEN; + if (ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) { + desc->flags |= htole32(RT2560_TX_OFDM); + + plcp_length = len & 0xfff; + desc->plcp_length_hi = plcp_length >> 6; + desc->plcp_length_lo = plcp_length & 0x3f; + } else { + plcp_length = (16 * len + rate - 1) / rate; + if (rate == 22) { + remainder = (16 * len) % 22; + if (remainder != 0 && remainder < 7) + desc->plcp_service |= RT2560_PLCP_LENGEXT; + } + desc->plcp_length_hi = plcp_length >> 8; + desc->plcp_length_lo = plcp_length & 0xff; + + if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) + desc->plcp_signal |= 0x08; + } + + if (!encrypt) + desc->flags |= htole32(RT2560_TX_VALID); + desc->flags |= encrypt ? htole32(RT2560_TX_CIPHER_BUSY) + : htole32(RT2560_TX_BUSY); +} + +static int +rt2560_tx_bcn(struct rt2560_softc *sc, struct mbuf *m0, + struct ieee80211_node *ni) +{ + struct ieee80211vap *vap = ni->ni_vap; + struct rt2560_tx_desc *desc; + struct rt2560_tx_data *data; + bus_dma_segment_t segs[RT2560_MAX_SCATTER]; + int nsegs, rate, error; + + desc = &sc->bcnq.desc[sc->bcnq.cur]; + data = &sc->bcnq.data[sc->bcnq.cur]; + + /* XXX maybe a separate beacon rate? */ + rate = vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)].mgmtrate; + + error = bus_dmamap_load_mbuf_sg(sc->bcnq.data_dmat, data->map, m0, + segs, &nsegs, BUS_DMA_NOWAIT); + if (error != 0) { + device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", + error); + m_freem(m0); + return error; + } + + if (ieee80211_radiotap_active_vap(vap)) { + struct rt2560_tx_radiotap_header *tap = &sc->sc_txtap; + + tap->wt_flags = 0; + tap->wt_rate = rate; + tap->wt_antenna = sc->tx_ant; + + ieee80211_radiotap_tx(vap, m0); + } + + data->m = m0; + data->ni = ni; + + rt2560_setup_tx_desc(sc, desc, RT2560_TX_IFS_NEWBACKOFF | + RT2560_TX_TIMESTAMP, m0->m_pkthdr.len, rate, 0, segs->ds_addr); + + DPRINTFN(sc, 10, "sending beacon frame len=%u idx=%u rate=%u\n", + m0->m_pkthdr.len, sc->bcnq.cur, rate); + + bus_dmamap_sync(sc->bcnq.data_dmat, data->map, BUS_DMASYNC_PREWRITE); + bus_dmamap_sync(sc->bcnq.desc_dmat, sc->bcnq.desc_map, + BUS_DMASYNC_PREWRITE); + + sc->bcnq.cur = (sc->bcnq.cur + 1) % RT2560_BEACON_RING_COUNT; + + return 0; +} + +static int +rt2560_tx_mgt(struct rt2560_softc *sc, struct mbuf *m0, + struct ieee80211_node *ni) +{ + struct ieee80211vap *vap = ni->ni_vap; + struct ieee80211com *ic = ni->ni_ic; + struct rt2560_tx_desc *desc; + struct rt2560_tx_data *data; + struct ieee80211_frame *wh; + struct ieee80211_key *k; + bus_dma_segment_t segs[RT2560_MAX_SCATTER]; + uint16_t dur; + uint32_t flags = 0; + int nsegs, rate, error; + + desc = &sc->prioq.desc[sc->prioq.cur]; + data = &sc->prioq.data[sc->prioq.cur]; + + rate = vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)].mgmtrate; + + wh = mtod(m0, struct ieee80211_frame *); + + if (wh->i_fc[1] & IEEE80211_FC1_WEP) { + k = ieee80211_crypto_encap(ni, m0); + if (k == NULL) { + m_freem(m0); + return ENOBUFS; + } + } + + error = bus_dmamap_load_mbuf_sg(sc->prioq.data_dmat, data->map, m0, + segs, &nsegs, 0); + if (error != 0) { + device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", + error); + m_freem(m0); + return error; + } + + if (ieee80211_radiotap_active_vap(vap)) { + struct rt2560_tx_radiotap_header *tap = &sc->sc_txtap; + + tap->wt_flags = 0; + tap->wt_rate = rate; + tap->wt_antenna = sc->tx_ant; + + ieee80211_radiotap_tx(vap, m0); + } + + data->m = m0; + data->ni = ni; + /* management frames are not taken into account for amrr */ + data->rix = IEEE80211_FIXED_RATE_NONE; + + wh = mtod(m0, struct ieee80211_frame *); + + if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { + flags |= RT2560_TX_ACK; + + dur = ieee80211_ack_duration(ic->ic_rt, + rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE); + *(uint16_t *)wh->i_dur = htole16(dur); + + /* tell hardware to add timestamp for probe responses */ + if ((wh->i_fc[0] & IEEE80211_FC0_TYPE_MASK) == + IEEE80211_FC0_TYPE_MGT && + (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_MASK) == + IEEE80211_FC0_SUBTYPE_PROBE_RESP) + flags |= RT2560_TX_TIMESTAMP; + } + + rt2560_setup_tx_desc(sc, desc, flags, m0->m_pkthdr.len, rate, 0, + segs->ds_addr); + + bus_dmamap_sync(sc->prioq.data_dmat, data->map, BUS_DMASYNC_PREWRITE); + bus_dmamap_sync(sc->prioq.desc_dmat, sc->prioq.desc_map, + BUS_DMASYNC_PREWRITE); + + DPRINTFN(sc, 10, "sending mgt frame len=%u idx=%u rate=%u\n", + m0->m_pkthdr.len, sc->prioq.cur, rate); + + /* kick prio */ + sc->prioq.queued++; + sc->prioq.cur = (sc->prioq.cur + 1) % RT2560_PRIO_RING_COUNT; + RAL_WRITE(sc, RT2560_TXCSR0, RT2560_KICK_PRIO); + + return 0; +} + +static int +rt2560_sendprot(struct rt2560_softc *sc, + const struct mbuf *m, struct ieee80211_node *ni, int prot, int rate) +{ + struct ieee80211com *ic = ni->ni_ic; + const struct ieee80211_frame *wh; + struct rt2560_tx_desc *desc; + struct rt2560_tx_data *data; + struct mbuf *mprot; + int protrate, ackrate, pktlen, flags, isshort, error; + uint16_t dur; + bus_dma_segment_t segs[RT2560_MAX_SCATTER]; + int nsegs; + + KASSERT(prot == IEEE80211_PROT_RTSCTS || prot == IEEE80211_PROT_CTSONLY, + ("protection %d", prot)); + + wh = mtod(m, const struct ieee80211_frame *); + pktlen = m->m_pkthdr.len + IEEE80211_CRC_LEN; + + protrate = ieee80211_ctl_rate(ic->ic_rt, rate); + ackrate = ieee80211_ack_rate(ic->ic_rt, rate); + + isshort = (ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0; + dur = ieee80211_compute_duration(ic->ic_rt, pktlen, rate, isshort) + + ieee80211_ack_duration(ic->ic_rt, rate, isshort); + flags = RT2560_TX_MORE_FRAG; + if (prot == IEEE80211_PROT_RTSCTS) { + /* NB: CTS is the same size as an ACK */ + dur += ieee80211_ack_duration(ic->ic_rt, rate, isshort); + flags |= RT2560_TX_ACK; + mprot = ieee80211_alloc_rts(ic, wh->i_addr1, wh->i_addr2, dur); + } else { + mprot = ieee80211_alloc_cts(ic, ni->ni_vap->iv_myaddr, dur); + } + if (mprot == NULL) { + /* XXX stat + msg */ + return ENOBUFS; + } + + desc = &sc->txq.desc[sc->txq.cur_encrypt]; + data = &sc->txq.data[sc->txq.cur_encrypt]; + + error = bus_dmamap_load_mbuf_sg(sc->txq.data_dmat, data->map, + mprot, segs, &nsegs, 0); + if (error != 0) { + device_printf(sc->sc_dev, + "could not map mbuf (error %d)\n", error); + m_freem(mprot); + return error; + } + + data->m = mprot; + data->ni = ieee80211_ref_node(ni); + /* ctl frames are not taken into account for amrr */ + data->rix = IEEE80211_FIXED_RATE_NONE; + + rt2560_setup_tx_desc(sc, desc, flags, mprot->m_pkthdr.len, protrate, 1, + segs->ds_addr); + + bus_dmamap_sync(sc->txq.data_dmat, data->map, + BUS_DMASYNC_PREWRITE); + + sc->txq.queued++; + sc->txq.cur_encrypt = (sc->txq.cur_encrypt + 1) % RT2560_TX_RING_COUNT; + + return 0; +} + +static int +rt2560_tx_raw(struct rt2560_softc *sc, struct mbuf *m0, + struct ieee80211_node *ni, const struct ieee80211_bpf_params *params) +{ + struct ieee80211vap *vap = ni->ni_vap; + struct ieee80211com *ic = ni->ni_ic; + struct rt2560_tx_desc *desc; + struct rt2560_tx_data *data; + bus_dma_segment_t segs[RT2560_MAX_SCATTER]; + uint32_t flags; + int nsegs, rate, error; + + desc = &sc->prioq.desc[sc->prioq.cur]; + data = &sc->prioq.data[sc->prioq.cur]; + + rate = params->ibp_rate0; + if (!ieee80211_isratevalid(ic->ic_rt, rate)) { + /* XXX fall back to mcast/mgmt rate? */ + m_freem(m0); + return EINVAL; + } + + flags = 0; + if ((params->ibp_flags & IEEE80211_BPF_NOACK) == 0) + flags |= RT2560_TX_ACK; + if (params->ibp_flags & (IEEE80211_BPF_RTS|IEEE80211_BPF_CTS)) { + error = rt2560_sendprot(sc, m0, ni, + params->ibp_flags & IEEE80211_BPF_RTS ? + IEEE80211_PROT_RTSCTS : IEEE80211_PROT_CTSONLY, + rate); + if (error) { + m_freem(m0); + return error; + } + flags |= RT2560_TX_LONG_RETRY | RT2560_TX_IFS_SIFS; + } + + error = bus_dmamap_load_mbuf_sg(sc->prioq.data_dmat, data->map, m0, + segs, &nsegs, 0); + if (error != 0) { + device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", + error); + m_freem(m0); + return error; + } + + if (ieee80211_radiotap_active_vap(vap)) { + struct rt2560_tx_radiotap_header *tap = &sc->sc_txtap; + + tap->wt_flags = 0; + tap->wt_rate = rate; + tap->wt_antenna = sc->tx_ant; + + ieee80211_radiotap_tx(ni->ni_vap, m0); + } + + data->m = m0; + data->ni = ni; + + /* XXX need to setup descriptor ourself */ + rt2560_setup_tx_desc(sc, desc, flags, m0->m_pkthdr.len, + rate, (params->ibp_flags & IEEE80211_BPF_CRYPTO) != 0, + segs->ds_addr); + + bus_dmamap_sync(sc->prioq.data_dmat, data->map, BUS_DMASYNC_PREWRITE); + bus_dmamap_sync(sc->prioq.desc_dmat, sc->prioq.desc_map, + BUS_DMASYNC_PREWRITE); + + DPRINTFN(sc, 10, "sending raw frame len=%u idx=%u rate=%u\n", + m0->m_pkthdr.len, sc->prioq.cur, rate); + + /* kick prio */ + sc->prioq.queued++; + sc->prioq.cur = (sc->prioq.cur + 1) % RT2560_PRIO_RING_COUNT; + RAL_WRITE(sc, RT2560_TXCSR0, RT2560_KICK_PRIO); + + return 0; +} + +static int +rt2560_tx_data(struct rt2560_softc *sc, struct mbuf *m0, + struct ieee80211_node *ni) +{ + struct ieee80211vap *vap = ni->ni_vap; + struct ieee80211com *ic = ni->ni_ic; + struct rt2560_tx_desc *desc; + struct rt2560_tx_data *data; + struct ieee80211_frame *wh; + const struct ieee80211_txparam *tp; + struct ieee80211_key *k; + struct mbuf *mnew; + bus_dma_segment_t segs[RT2560_MAX_SCATTER]; + uint16_t dur; + uint32_t flags; + int nsegs, rate, error; + + wh = mtod(m0, struct ieee80211_frame *); + + tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; + if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { + rate = tp->mcastrate; + } else if (m0->m_flags & M_EAPOL) { + rate = tp->mgmtrate; + } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { + rate = tp->ucastrate; + } else { + (void) ieee80211_amrr_choose(ni, &RT2560_NODE(ni)->amrr); + rate = ni->ni_txrate; + } + + if (wh->i_fc[1] & IEEE80211_FC1_WEP) { + k = ieee80211_crypto_encap(ni, m0); + if (k == NULL) { + m_freem(m0); + return ENOBUFS; + } + + /* packet header may have moved, reset our local pointer */ + wh = mtod(m0, struct ieee80211_frame *); + } + + flags = 0; + if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { + int prot = IEEE80211_PROT_NONE; + if (m0->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) + prot = IEEE80211_PROT_RTSCTS; + else if ((ic->ic_flags & IEEE80211_F_USEPROT) && + ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) + prot = ic->ic_protmode; + if (prot != IEEE80211_PROT_NONE) { + error = rt2560_sendprot(sc, m0, ni, prot, rate); + if (error) { + m_freem(m0); + return error; + } + flags |= RT2560_TX_LONG_RETRY | RT2560_TX_IFS_SIFS; + } + } + + data = &sc->txq.data[sc->txq.cur_encrypt]; + desc = &sc->txq.desc[sc->txq.cur_encrypt]; + + error = bus_dmamap_load_mbuf_sg(sc->txq.data_dmat, data->map, m0, + segs, &nsegs, 0); + if (error != 0 && error != EFBIG) { + device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", + error); + m_freem(m0); + return error; + } + if (error != 0) { + mnew = m_defrag(m0, M_DONTWAIT); + if (mnew == NULL) { + device_printf(sc->sc_dev, + "could not defragment mbuf\n"); + m_freem(m0); + return ENOBUFS; + } + m0 = mnew; + + error = bus_dmamap_load_mbuf_sg(sc->txq.data_dmat, data->map, + m0, segs, &nsegs, 0); + if (error != 0) { + device_printf(sc->sc_dev, + "could not map mbuf (error %d)\n", error); + m_freem(m0); + return error; + } + + /* packet header may have moved, reset our local pointer */ + wh = mtod(m0, struct ieee80211_frame *); + } + + if (ieee80211_radiotap_active_vap(vap)) { + struct rt2560_tx_radiotap_header *tap = &sc->sc_txtap; + + tap->wt_flags = 0; + tap->wt_rate = rate; + tap->wt_antenna = sc->tx_ant; + + ieee80211_radiotap_tx(vap, m0); + } + + data->m = m0; + data->ni = ni; + + /* remember link conditions for rate adaptation algorithm */ + if (tp->ucastrate == IEEE80211_FIXED_RATE_NONE) { + data->rix = ni->ni_txrate; + /* XXX probably need last rssi value and not avg */ + data->rssi = ic->ic_node_getrssi(ni); + } else + data->rix = IEEE80211_FIXED_RATE_NONE; + + if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { + flags |= RT2560_TX_ACK; + + dur = ieee80211_ack_duration(ic->ic_rt, + rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE); + *(uint16_t *)wh->i_dur = htole16(dur); + } + + rt2560_setup_tx_desc(sc, desc, flags, m0->m_pkthdr.len, rate, 1, + segs->ds_addr); + + bus_dmamap_sync(sc->txq.data_dmat, data->map, BUS_DMASYNC_PREWRITE); + bus_dmamap_sync(sc->txq.desc_dmat, sc->txq.desc_map, + BUS_DMASYNC_PREWRITE); + + DPRINTFN(sc, 10, "sending data frame len=%u idx=%u rate=%u\n", + m0->m_pkthdr.len, sc->txq.cur_encrypt, rate); + + /* kick encrypt */ + sc->txq.queued++; + sc->txq.cur_encrypt = (sc->txq.cur_encrypt + 1) % RT2560_TX_RING_COUNT; + RAL_WRITE(sc, RT2560_SECCSR1, RT2560_KICK_ENCRYPT); + + return 0; +} + +static void +rt2560_start_locked(struct ifnet *ifp) +{ + struct rt2560_softc *sc = ifp->if_softc; + struct mbuf *m; + struct ieee80211_node *ni; + + RAL_LOCK_ASSERT(sc); + + for (;;) { + IFQ_DRV_DEQUEUE(&ifp->if_snd, m); + if (m == NULL) + break; + if (sc->txq.queued >= RT2560_TX_RING_COUNT - 1) { + IFQ_DRV_PREPEND(&ifp->if_snd, m); + ifp->if_drv_flags |= IFF_DRV_OACTIVE; + sc->sc_flags |= RT2560_F_DATA_OACTIVE; + break; + } + ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; + if (rt2560_tx_data(sc, m, ni) != 0) { + ieee80211_free_node(ni); + ifp->if_oerrors++; + break; + } + + sc->sc_tx_timer = 5; + } +} + +static void +rt2560_start(struct ifnet *ifp) +{ + struct rt2560_softc *sc = ifp->if_softc; + + RAL_LOCK(sc); + rt2560_start_locked(ifp); + RAL_UNLOCK(sc); +} + +static void +rt2560_watchdog(void *arg) +{ + struct rt2560_softc *sc = arg; + struct ifnet *ifp = sc->sc_ifp; + + RAL_LOCK_ASSERT(sc); + + KASSERT(ifp->if_drv_flags & IFF_DRV_RUNNING, ("not running")); + + if (sc->sc_invalid) /* card ejected */ + return; + + rt2560_encryption_intr(sc); + rt2560_tx_intr(sc); + + if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) { + if_printf(ifp, "device timeout\n"); + rt2560_init_locked(sc); + ifp->if_oerrors++; + /* NB: callout is reset in rt2560_init() */ + return; + } + callout_reset(&sc->watchdog_ch, hz, rt2560_watchdog, sc); +} + +static int +rt2560_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) +{ + struct rt2560_softc *sc = ifp->if_softc; + struct ieee80211com *ic = ifp->if_l2com; + struct ifreq *ifr = (struct ifreq *) data; + int error = 0, startall = 0; + + switch (cmd) { + case SIOCSIFFLAGS: + RAL_LOCK(sc); + if (ifp->if_flags & IFF_UP) { + if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { + rt2560_init_locked(sc); + startall = 1; + } else + rt2560_update_promisc(ifp); + } else { + if (ifp->if_drv_flags & IFF_DRV_RUNNING) + rt2560_stop_locked(sc); + } + RAL_UNLOCK(sc); + if (startall) + ieee80211_start_all(ic); + break; + case SIOCGIFMEDIA: + error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); + break; + case SIOCGIFADDR: + error = ether_ioctl(ifp, cmd, data); + break; + default: + error = EINVAL; + break; + } + return error; +} + +static void +rt2560_bbp_write(struct rt2560_softc *sc, uint8_t reg, uint8_t val) +{ + uint32_t tmp; + int ntries; + + for (ntries = 0; ntries < 100; ntries++) { + if (!(RAL_READ(sc, RT2560_BBPCSR) & RT2560_BBP_BUSY)) + break; + DELAY(1); + } + if (ntries == 100) { + device_printf(sc->sc_dev, "could not write to BBP\n"); + return; + } + + tmp = RT2560_BBP_WRITE | RT2560_BBP_BUSY | reg << 8 | val; + RAL_WRITE(sc, RT2560_BBPCSR, tmp); + + DPRINTFN(sc, 15, "BBP R%u <- 0x%02x\n", reg, val); +} + +static uint8_t +rt2560_bbp_read(struct rt2560_softc *sc, uint8_t reg) +{ + uint32_t val; + int ntries; + + for (ntries = 0; ntries < 100; ntries++) { + if (!(RAL_READ(sc, RT2560_BBPCSR) & RT2560_BBP_BUSY)) + break; + DELAY(1); + } + if (ntries == 100) { + device_printf(sc->sc_dev, "could not read from BBP\n"); + return 0; + } + + val = RT2560_BBP_BUSY | reg << 8; + RAL_WRITE(sc, RT2560_BBPCSR, val); + + for (ntries = 0; ntries < 100; ntries++) { + val = RAL_READ(sc, RT2560_BBPCSR); + if (!(val & RT2560_BBP_BUSY)) + return val & 0xff; + DELAY(1); + } + + device_printf(sc->sc_dev, "could not read from BBP\n"); + return 0; +} + +static void +rt2560_rf_write(struct rt2560_softc *sc, uint8_t reg, uint32_t val) +{ + uint32_t tmp; + int ntries; + + for (ntries = 0; ntries < 100; ntries++) { + if (!(RAL_READ(sc, RT2560_RFCSR) & RT2560_RF_BUSY)) + break; + DELAY(1); + } + if (ntries == 100) { + device_printf(sc->sc_dev, "could not write to RF\n"); + return; + } + + tmp = RT2560_RF_BUSY | RT2560_RF_20BIT | (val & 0xfffff) << 2 | + (reg & 0x3); + RAL_WRITE(sc, RT2560_RFCSR, tmp); + + /* remember last written value in sc */ + sc->rf_regs[reg] = val; + + DPRINTFN(sc, 15, "RF R[%u] <- 0x%05x\n", reg & 0x3, val & 0xfffff); +} + +static void +rt2560_set_chan(struct rt2560_softc *sc, struct ieee80211_channel *c) +{ + struct ifnet *ifp = sc->sc_ifp; + struct ieee80211com *ic = ifp->if_l2com; + uint8_t power, tmp; + u_int i, chan; + + chan = ieee80211_chan2ieee(ic, c); + KASSERT(chan != 0 && chan != IEEE80211_CHAN_ANY, ("chan 0x%x", chan)); + + if (IEEE80211_IS_CHAN_2GHZ(c)) + power = min(sc->txpow[chan - 1], 31); + else + power = 31; + + /* adjust txpower using ifconfig settings */ + power -= (100 - ic->ic_txpowlimit) / 8; + + DPRINTFN(sc, 2, "setting channel to %u, txpower to %u\n", chan, power); + + switch (sc->rf_rev) { + case RT2560_RF_2522: + rt2560_rf_write(sc, RAL_RF1, 0x00814); + rt2560_rf_write(sc, RAL_RF2, rt2560_rf2522_r2[chan - 1]); + rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x00040); + break; + + case RT2560_RF_2523: + rt2560_rf_write(sc, RAL_RF1, 0x08804); + rt2560_rf_write(sc, RAL_RF2, rt2560_rf2523_r2[chan - 1]); + rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x38044); + rt2560_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); + break; + + case RT2560_RF_2524: + rt2560_rf_write(sc, RAL_RF1, 0x0c808); + rt2560_rf_write(sc, RAL_RF2, rt2560_rf2524_r2[chan - 1]); + rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x00040); + rt2560_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); + break; + + case RT2560_RF_2525: + rt2560_rf_write(sc, RAL_RF1, 0x08808); + rt2560_rf_write(sc, RAL_RF2, rt2560_rf2525_hi_r2[chan - 1]); + rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x18044); + rt2560_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); + + rt2560_rf_write(sc, RAL_RF1, 0x08808); + rt2560_rf_write(sc, RAL_RF2, rt2560_rf2525_r2[chan - 1]); + rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x18044); + rt2560_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00280 : 0x00286); + break; + + case RT2560_RF_2525E: + rt2560_rf_write(sc, RAL_RF1, 0x08808); + rt2560_rf_write(sc, RAL_RF2, rt2560_rf2525e_r2[chan - 1]); + rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x18044); + rt2560_rf_write(sc, RAL_RF4, (chan == 14) ? 0x00286 : 0x00282); + break; + + case RT2560_RF_2526: + rt2560_rf_write(sc, RAL_RF2, rt2560_rf2526_hi_r2[chan - 1]); + rt2560_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); + rt2560_rf_write(sc, RAL_RF1, 0x08804); + + rt2560_rf_write(sc, RAL_RF2, rt2560_rf2526_r2[chan - 1]); + rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x18044); + rt2560_rf_write(sc, RAL_RF4, (chan & 1) ? 0x00386 : 0x00381); + break; + + /* dual-band RF */ + case RT2560_RF_5222: + for (i = 0; rt2560_rf5222[i].chan != chan; i++); + + rt2560_rf_write(sc, RAL_RF1, rt2560_rf5222[i].r1); + rt2560_rf_write(sc, RAL_RF2, rt2560_rf5222[i].r2); + rt2560_rf_write(sc, RAL_RF3, power << 7 | 0x00040); + rt2560_rf_write(sc, RAL_RF4, rt2560_rf5222[i].r4); + break; + default: + printf("unknown ral rev=%d\n", sc->rf_rev); + } + + /* XXX */ + if ((ic->ic_flags & IEEE80211_F_SCAN) == 0) { + /* set Japan filter bit for channel 14 */ + tmp = rt2560_bbp_read(sc, 70); + + tmp &= ~RT2560_JAPAN_FILTER; + if (chan == 14) + tmp |= RT2560_JAPAN_FILTER; + + rt2560_bbp_write(sc, 70, tmp); + + /* clear CRC errors */ + RAL_READ(sc, RT2560_CNT0); + } +} + +static void +rt2560_set_channel(struct ieee80211com *ic) +{ + struct ifnet *ifp = ic->ic_ifp; + struct rt2560_softc *sc = ifp->if_softc; + + RAL_LOCK(sc); + rt2560_set_chan(sc, ic->ic_curchan); + RAL_UNLOCK(sc); + +} + +#if 0 +/* + * Disable RF auto-tuning. + */ +static void +rt2560_disable_rf_tune(struct rt2560_softc *sc) +{ + uint32_t tmp; + + if (sc->rf_rev != RT2560_RF_2523) { + tmp = sc->rf_regs[RAL_RF1] & ~RAL_RF1_AUTOTUNE; + rt2560_rf_write(sc, RAL_RF1, tmp); + } + + tmp = sc->rf_regs[RAL_RF3] & ~RAL_RF3_AUTOTUNE; + rt2560_rf_write(sc, RAL_RF3, tmp); + + DPRINTFN(sc, 2, "%s", "disabling RF autotune\n"); +} +#endif + +/* + * Refer to IEEE Std 802.11-1999 pp. 123 for more information on TSF + * synchronization. + */ +static void +rt2560_enable_tsf_sync(struct rt2560_softc *sc) +{ + struct ifnet *ifp = sc->sc_ifp; + struct ieee80211com *ic = ifp->if_l2com; + struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); + uint16_t logcwmin, preload; + uint32_t tmp; + + /* first, disable TSF synchronization */ + RAL_WRITE(sc, RT2560_CSR14, 0); + + tmp = 16 * vap->iv_bss->ni_intval; + RAL_WRITE(sc, RT2560_CSR12, tmp); + + RAL_WRITE(sc, RT2560_CSR13, 0); + + logcwmin = 5; + preload = (vap->iv_opmode == IEEE80211_M_STA) ? 384 : 1024; + tmp = logcwmin << 16 | preload; + RAL_WRITE(sc, RT2560_BCNOCSR, tmp); + + /* finally, enable TSF synchronization */ + tmp = RT2560_ENABLE_TSF | RT2560_ENABLE_TBCN; + if (ic->ic_opmode == IEEE80211_M_STA) + tmp |= RT2560_ENABLE_TSF_SYNC(1); + else + tmp |= RT2560_ENABLE_TSF_SYNC(2) | + RT2560_ENABLE_BEACON_GENERATOR; + RAL_WRITE(sc, RT2560_CSR14, tmp); + + DPRINTF(sc, "%s", "enabling TSF synchronization\n"); +} + +static void +rt2560_enable_tsf(struct rt2560_softc *sc) +{ + RAL_WRITE(sc, RT2560_CSR14, 0); + RAL_WRITE(sc, RT2560_CSR14, + RT2560_ENABLE_TSF_SYNC(2) | RT2560_ENABLE_TSF); +} + +static void +rt2560_update_plcp(struct rt2560_softc *sc) +{ + struct ifnet *ifp = sc->sc_ifp; + struct ieee80211com *ic = ifp->if_l2com; + + /* no short preamble for 1Mbps */ + RAL_WRITE(sc, RT2560_PLCP1MCSR, 0x00700400); + + if (!(ic->ic_flags & IEEE80211_F_SHPREAMBLE)) { + /* values taken from the reference driver */ + RAL_WRITE(sc, RT2560_PLCP2MCSR, 0x00380401); + RAL_WRITE(sc, RT2560_PLCP5p5MCSR, 0x00150402); + RAL_WRITE(sc, RT2560_PLCP11MCSR, 0x000b8403); + } else { + /* same values as above or'ed 0x8 */ + RAL_WRITE(sc, RT2560_PLCP2MCSR, 0x00380409); + RAL_WRITE(sc, RT2560_PLCP5p5MCSR, 0x0015040a); + RAL_WRITE(sc, RT2560_PLCP11MCSR, 0x000b840b); + } + + DPRINTF(sc, "updating PLCP for %s preamble\n", + (ic->ic_flags & IEEE80211_F_SHPREAMBLE) ? "short" : "long"); +} + +/* + * This function can be called by ieee80211_set_shortslottime(). Refer to + * IEEE Std 802.11-1999 pp. 85 to know how these values are computed. + */ +static void +rt2560_update_slot(struct ifnet *ifp) +{ + struct rt2560_softc *sc = ifp->if_softc; + struct ieee80211com *ic = ifp->if_l2com; + uint8_t slottime; + uint16_t tx_sifs, tx_pifs, tx_difs, eifs; + uint32_t tmp; + +#ifndef FORCE_SLOTTIME + slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; +#else + /* + * Setting slot time according to "short slot time" capability + * in beacon/probe_resp seems to cause problem to acknowledge + * certain AP's data frames transimitted at CCK/DS rates: the + * problematic AP keeps retransmitting data frames, probably + * because MAC level acks are not received by hardware. + * So we cheat a little bit here by claiming we are capable of + * "short slot time" but setting hardware slot time to the normal + * slot time. ral(4) does not seem to have trouble to receive + * frames transmitted using short slot time even if hardware + * slot time is set to normal slot time. If we didn't use this + * trick, we would have to claim that short slot time is not + * supported; this would give relative poor RX performance + * (-1Mb~-2Mb lower) and the _whole_ BSS would stop using short + * slot time. + */ + slottime = 20; +#endif + + /* update the MAC slot boundaries */ + tx_sifs = RAL_SIFS - RT2560_TXRX_TURNAROUND; + tx_pifs = tx_sifs + slottime; + tx_difs = tx_sifs + 2 * slottime; + eifs = (ic->ic_curmode == IEEE80211_MODE_11B) ? 364 : 60; + + tmp = RAL_READ(sc, RT2560_CSR11); + tmp = (tmp & ~0x1f00) | slottime << 8; + RAL_WRITE(sc, RT2560_CSR11, tmp); + + tmp = tx_pifs << 16 | tx_sifs; + RAL_WRITE(sc, RT2560_CSR18, tmp); + + tmp = eifs << 16 | tx_difs; + RAL_WRITE(sc, RT2560_CSR19, tmp); + + DPRINTF(sc, "setting slottime to %uus\n", slottime); +} + +static void +rt2560_set_basicrates(struct rt2560_softc *sc) +{ + struct ifnet *ifp = sc->sc_ifp; + struct ieee80211com *ic = ifp->if_l2com; + + /* update basic rate set */ + if (ic->ic_curmode == IEEE80211_MODE_11B) { + /* 11b basic rates: 1, 2Mbps */ + RAL_WRITE(sc, RT2560_ARSP_PLCP_1, 0x3); + } else if (IEEE80211_IS_CHAN_5GHZ(ic->ic_curchan)) { + /* 11a basic rates: 6, 12, 24Mbps */ + RAL_WRITE(sc, RT2560_ARSP_PLCP_1, 0x150); + } else { + /* 11g basic rates: 1, 2, 5.5, 11, 6, 12, 24Mbps */ + RAL_WRITE(sc, RT2560_ARSP_PLCP_1, 0x15f); + } +} + +static void +rt2560_update_led(struct rt2560_softc *sc, int led1, int led2) +{ + uint32_t tmp; + + /* set ON period to 70ms and OFF period to 30ms */ + tmp = led1 << 16 | led2 << 17 | 70 << 8 | 30; + RAL_WRITE(sc, RT2560_LEDCSR, tmp); +} + +static void +rt2560_set_bssid(struct rt2560_softc *sc, const uint8_t *bssid) +{ + uint32_t tmp; + + tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24; + RAL_WRITE(sc, RT2560_CSR5, tmp); + + tmp = bssid[4] | bssid[5] << 8; + RAL_WRITE(sc, RT2560_CSR6, tmp); + + DPRINTF(sc, "setting BSSID to %6D\n", bssid, ":"); +} + +static void +rt2560_set_macaddr(struct rt2560_softc *sc, uint8_t *addr) +{ + uint32_t tmp; + + tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24; + RAL_WRITE(sc, RT2560_CSR3, tmp); + + tmp = addr[4] | addr[5] << 8; + RAL_WRITE(sc, RT2560_CSR4, tmp); + + DPRINTF(sc, "setting MAC address to %6D\n", addr, ":"); +} + +static void +rt2560_get_macaddr(struct rt2560_softc *sc, uint8_t *addr) +{ + uint32_t tmp; + + tmp = RAL_READ(sc, RT2560_CSR3); + addr[0] = tmp & 0xff; + addr[1] = (tmp >> 8) & 0xff; + addr[2] = (tmp >> 16) & 0xff; + addr[3] = (tmp >> 24); + + tmp = RAL_READ(sc, RT2560_CSR4); + addr[4] = tmp & 0xff; + addr[5] = (tmp >> 8) & 0xff; +} + +static void +rt2560_update_promisc(struct ifnet *ifp) +{ + struct rt2560_softc *sc = ifp->if_softc; + uint32_t tmp; + + tmp = RAL_READ(sc, RT2560_RXCSR0); + + tmp &= ~RT2560_DROP_NOT_TO_ME; + if (!(ifp->if_flags & IFF_PROMISC)) + tmp |= RT2560_DROP_NOT_TO_ME; + + RAL_WRITE(sc, RT2560_RXCSR0, tmp); + + DPRINTF(sc, "%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ? + "entering" : "leaving"); +} + +static const char * +rt2560_get_rf(int rev) +{ + switch (rev) { + case RT2560_RF_2522: return "RT2522"; + case RT2560_RF_2523: return "RT2523"; + case RT2560_RF_2524: return "RT2524"; + case RT2560_RF_2525: return "RT2525"; + case RT2560_RF_2525E: return "RT2525e"; + case RT2560_RF_2526: return "RT2526"; + case RT2560_RF_5222: return "RT5222"; + default: return "unknown"; + } +} + +static void +rt2560_read_config(struct rt2560_softc *sc) +{ + uint16_t val; + int i; + + val = rt2560_eeprom_read(sc, RT2560_EEPROM_CONFIG0); + sc->rf_rev = (val >> 11) & 0x7; + sc->hw_radio = (val >> 10) & 0x1; + sc->led_mode = (val >> 6) & 0x7; + sc->rx_ant = (val >> 4) & 0x3; + sc->tx_ant = (val >> 2) & 0x3; + sc->nb_ant = val & 0x3; + + /* read default values for BBP registers */ + for (i = 0; i < 16; i++) { + val = rt2560_eeprom_read(sc, RT2560_EEPROM_BBP_BASE + i); + if (val == 0 || val == 0xffff) + continue; + + sc->bbp_prom[i].reg = val >> 8; + sc->bbp_prom[i].val = val & 0xff; + } + + /* read Tx power for all b/g channels */ + for (i = 0; i < 14 / 2; i++) { + val = rt2560_eeprom_read(sc, RT2560_EEPROM_TXPOWER + i); + sc->txpow[i * 2] = val & 0xff; + sc->txpow[i * 2 + 1] = val >> 8; + } + for (i = 0; i < 14; ++i) { + if (sc->txpow[i] > 31) + sc->txpow[i] = 24; + } + + val = rt2560_eeprom_read(sc, RT2560_EEPROM_CALIBRATE); + if ((val & 0xff) == 0xff) + sc->rssi_corr = RT2560_DEFAULT_RSSI_CORR; + else + sc->rssi_corr = val & 0xff; + DPRINTF(sc, "rssi correction %d, calibrate 0x%02x\n", + sc->rssi_corr, val); +} + + +static void +rt2560_scan_start(struct ieee80211com *ic) +{ + struct ifnet *ifp = ic->ic_ifp; + struct rt2560_softc *sc = ifp->if_softc; + + /* abort TSF synchronization */ + RAL_WRITE(sc, RT2560_CSR14, 0); + rt2560_set_bssid(sc, ifp->if_broadcastaddr); +} + +static void +rt2560_scan_end(struct ieee80211com *ic) +{ + struct ifnet *ifp = ic->ic_ifp; + struct rt2560_softc *sc = ifp->if_softc; + struct ieee80211vap *vap = ic->ic_scan->ss_vap; + + rt2560_enable_tsf_sync(sc); + /* XXX keep local copy */ + rt2560_set_bssid(sc, vap->iv_bss->ni_bssid); +} + +static int +rt2560_bbp_init(struct rt2560_softc *sc) +{ +#define N(a) (sizeof (a) / sizeof ((a)[0])) + int i, ntries; + + /* wait for BBP to be ready */ + for (ntries = 0; ntries < 100; ntries++) { + if (rt2560_bbp_read(sc, RT2560_BBP_VERSION) != 0) + break; + DELAY(1); + } + if (ntries == 100) { + device_printf(sc->sc_dev, "timeout waiting for BBP\n"); + return EIO; + } + + /* initialize BBP registers to default values */ + for (i = 0; i < N(rt2560_def_bbp); i++) { + rt2560_bbp_write(sc, rt2560_def_bbp[i].reg, + rt2560_def_bbp[i].val); + } + + /* initialize BBP registers to values stored in EEPROM */ + for (i = 0; i < 16; i++) { + if (sc->bbp_prom[i].reg == 0 && sc->bbp_prom[i].val == 0) + break; + rt2560_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); + } + rt2560_bbp_write(sc, 17, 0x48); /* XXX restore bbp17 */ + + return 0; +#undef N +} + +static void +rt2560_set_txantenna(struct rt2560_softc *sc, int antenna) +{ + uint32_t tmp; + uint8_t tx; + + tx = rt2560_bbp_read(sc, RT2560_BBP_TX) & ~RT2560_BBP_ANTMASK; + if (antenna == 1) + tx |= RT2560_BBP_ANTA; + else if (antenna == 2) + tx |= RT2560_BBP_ANTB; + else + tx |= RT2560_BBP_DIVERSITY; + + /* need to force I/Q flip for RF 2525e, 2526 and 5222 */ + if (sc->rf_rev == RT2560_RF_2525E || sc->rf_rev == RT2560_RF_2526 || + sc->rf_rev == RT2560_RF_5222) + tx |= RT2560_BBP_FLIPIQ; + + rt2560_bbp_write(sc, RT2560_BBP_TX, tx); + + /* update values for CCK and OFDM in BBPCSR1 */ + tmp = RAL_READ(sc, RT2560_BBPCSR1) & ~0x00070007; + tmp |= (tx & 0x7) << 16 | (tx & 0x7); + RAL_WRITE(sc, RT2560_BBPCSR1, tmp); +} + +static void +rt2560_set_rxantenna(struct rt2560_softc *sc, int antenna) +{ + uint8_t rx; + + rx = rt2560_bbp_read(sc, RT2560_BBP_RX) & ~RT2560_BBP_ANTMASK; + if (antenna == 1) + rx |= RT2560_BBP_ANTA; + else if (antenna == 2) + rx |= RT2560_BBP_ANTB; + else + rx |= RT2560_BBP_DIVERSITY; + + /* need to force no I/Q flip for RF 2525e and 2526 */ + if (sc->rf_rev == RT2560_RF_2525E || sc->rf_rev == RT2560_RF_2526) + rx &= ~RT2560_BBP_FLIPIQ; + + rt2560_bbp_write(sc, RT2560_BBP_RX, rx); +} + +static void +rt2560_init_locked(struct rt2560_softc *sc) +{ +#define N(a) (sizeof (a) / sizeof ((a)[0])) + struct ifnet *ifp = sc->sc_ifp; + struct ieee80211com *ic = ifp->if_l2com; + uint32_t tmp; + int i; + + RAL_LOCK_ASSERT(sc); + + rt2560_stop_locked(sc); + + /* setup tx rings */ + tmp = RT2560_PRIO_RING_COUNT << 24 | + RT2560_ATIM_RING_COUNT << 16 | + RT2560_TX_RING_COUNT << 8 | + RT2560_TX_DESC_SIZE; + + /* rings must be initialized in this exact order */ + RAL_WRITE(sc, RT2560_TXCSR2, tmp); + RAL_WRITE(sc, RT2560_TXCSR3, sc->txq.physaddr); + RAL_WRITE(sc, RT2560_TXCSR5, sc->prioq.physaddr); + RAL_WRITE(sc, RT2560_TXCSR4, sc->atimq.physaddr); + RAL_WRITE(sc, RT2560_TXCSR6, sc->bcnq.physaddr); + + /* setup rx ring */ + tmp = RT2560_RX_RING_COUNT << 8 | RT2560_RX_DESC_SIZE; + + RAL_WRITE(sc, RT2560_RXCSR1, tmp); + RAL_WRITE(sc, RT2560_RXCSR2, sc->rxq.physaddr); + + /* initialize MAC registers to default values */ + for (i = 0; i < N(rt2560_def_mac); i++) + RAL_WRITE(sc, rt2560_def_mac[i].reg, rt2560_def_mac[i].val); + + rt2560_set_macaddr(sc, IF_LLADDR(ifp)); + + /* set basic rate set (will be updated later) */ + RAL_WRITE(sc, RT2560_ARSP_PLCP_1, 0x153); + + rt2560_update_slot(ifp); + rt2560_update_plcp(sc); + rt2560_update_led(sc, 0, 0); + + RAL_WRITE(sc, RT2560_CSR1, RT2560_RESET_ASIC); + RAL_WRITE(sc, RT2560_CSR1, RT2560_HOST_READY); + + if (rt2560_bbp_init(sc) != 0) { + rt2560_stop(sc); + RAL_UNLOCK(sc); + return; + } + + rt2560_set_txantenna(sc, sc->tx_ant); + rt2560_set_rxantenna(sc, sc->rx_ant); + + /* set default BSS channel */ + rt2560_set_chan(sc, ic->ic_curchan); + + /* kick Rx */ + tmp = RT2560_DROP_PHY_ERROR | RT2560_DROP_CRC_ERROR; + if (ic->ic_opmode != IEEE80211_M_MONITOR) { + tmp |= RT2560_DROP_CTL | RT2560_DROP_VERSION_ERROR; + if (ic->ic_opmode != IEEE80211_M_HOSTAP && + ic->ic_opmode != IEEE80211_M_MBSS) + tmp |= RT2560_DROP_TODS; + if (!(ifp->if_flags & IFF_PROMISC)) + tmp |= RT2560_DROP_NOT_TO_ME; + } + RAL_WRITE(sc, RT2560_RXCSR0, tmp); + + /* clear old FCS and Rx FIFO errors */ + RAL_READ(sc, RT2560_CNT0); + RAL_READ(sc, RT2560_CNT4); + + /* clear any pending interrupts */ + RAL_WRITE(sc, RT2560_CSR7, 0xffffffff); + + /* enable interrupts */ + RAL_WRITE(sc, RT2560_CSR8, RT2560_INTR_MASK); + + ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; + ifp->if_drv_flags |= IFF_DRV_RUNNING; + + callout_reset(&sc->watchdog_ch, hz, rt2560_watchdog, sc); +#undef N +} + +static void +rt2560_init(void *priv) +{ + struct rt2560_softc *sc = priv; + struct ifnet *ifp = sc->sc_ifp; + struct ieee80211com *ic = ifp->if_l2com; + + RAL_LOCK(sc); + rt2560_init_locked(sc); + RAL_UNLOCK(sc); + + if (ifp->if_drv_flags & IFF_DRV_RUNNING) + ieee80211_start_all(ic); /* start all vap's */ +} + +static void +rt2560_stop_locked(struct rt2560_softc *sc) +{ + struct ifnet *ifp = sc->sc_ifp; + volatile int *flags = &sc->sc_flags; + + RAL_LOCK_ASSERT(sc); + + while (*flags & RT2560_F_INPUT_RUNNING) + msleep(sc, &sc->sc_mtx, 0, "ralrunning", hz/10); + + callout_stop(&sc->watchdog_ch); + sc->sc_tx_timer = 0; + + if (ifp->if_drv_flags & IFF_DRV_RUNNING) { + ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); + + /* abort Tx */ + RAL_WRITE(sc, RT2560_TXCSR0, RT2560_ABORT_TX); + + /* disable Rx */ + RAL_WRITE(sc, RT2560_RXCSR0, RT2560_DISABLE_RX); + + /* reset ASIC (imply reset BBP) */ + RAL_WRITE(sc, RT2560_CSR1, RT2560_RESET_ASIC); + RAL_WRITE(sc, RT2560_CSR1, 0); + + /* disable interrupts */ + RAL_WRITE(sc, RT2560_CSR8, 0xffffffff); + + /* reset Tx and Rx rings */ + rt2560_reset_tx_ring(sc, &sc->txq); + rt2560_reset_tx_ring(sc, &sc->atimq); + rt2560_reset_tx_ring(sc, &sc->prioq); + rt2560_reset_tx_ring(sc, &sc->bcnq); + rt2560_reset_rx_ring(sc, &sc->rxq); + } + sc->sc_flags &= ~(RT2560_F_PRIO_OACTIVE | RT2560_F_DATA_OACTIVE); +} + +void +rt2560_stop(void *arg) +{ + struct rt2560_softc *sc = arg; + + RAL_LOCK(sc); + rt2560_stop_locked(sc); + RAL_UNLOCK(sc); +} + +static int +rt2560_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, + const struct ieee80211_bpf_params *params) +{ + struct ieee80211com *ic = ni->ni_ic; + struct ifnet *ifp = ic->ic_ifp; + struct rt2560_softc *sc = ifp->if_softc; + + RAL_LOCK(sc); + + /* prevent management frames from being sent if we're not ready */ + if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { + RAL_UNLOCK(sc); + m_freem(m); + ieee80211_free_node(ni); + return ENETDOWN; + } + if (sc->prioq.queued >= RT2560_PRIO_RING_COUNT) { + ifp->if_drv_flags |= IFF_DRV_OACTIVE; + sc->sc_flags |= RT2560_F_PRIO_OACTIVE; + RAL_UNLOCK(sc); + m_freem(m); + ieee80211_free_node(ni); + return ENOBUFS; /* XXX */ + } + + ifp->if_opackets++; + + if (params == NULL) { + /* + * Legacy path; interpret frame contents to decide + * precisely how to send the frame. + */ + if (rt2560_tx_mgt(sc, m, ni) != 0) + goto bad; + } else { + /* + * Caller supplied explicit parameters to use in + * sending the frame. + */ + if (rt2560_tx_raw(sc, m, ni, params)) + goto bad; + } + sc->sc_tx_timer = 5; + + RAL_UNLOCK(sc); + + return 0; +bad: + ifp->if_oerrors++; + ieee80211_free_node(ni); + RAL_UNLOCK(sc); + return EIO; /* XXX */ +} diff --git a/src/add-ons/kernel/drivers/network/wlan/ralinkwifi/dev/ral/rt2560reg.h b/src/add-ons/kernel/drivers/network/wlan/ralinkwifi/dev/ral/rt2560reg.h new file mode 100644 index 0000000000..8e501b4c22 --- /dev/null +++ b/src/add-ons/kernel/drivers/network/wlan/ralinkwifi/dev/ral/rt2560reg.h @@ -0,0 +1,489 @@ +/* $FreeBSD$ */ + +/*- + * Copyright (c) 2005, 2006 + * Damien Bergamini + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#define RT2560_DEFAULT_RSSI_CORR 0x79 +#define RT2560_NOISE_FLOOR -95 + +#define RT2560_TX_RING_COUNT 48 +#define RT2560_ATIM_RING_COUNT 4 +#define RT2560_PRIO_RING_COUNT 16 +#define RT2560_BEACON_RING_COUNT 1 +#define RT2560_RX_RING_COUNT 32 + +#define RT2560_TX_DESC_SIZE (sizeof (struct rt2560_tx_desc)) +#define RT2560_RX_DESC_SIZE (sizeof (struct rt2560_rx_desc)) + +#define RT2560_MAX_SCATTER 1 + +/* + * Control and status registers. + */ +#define RT2560_CSR0 0x0000 /* ASIC version number */ +#define RT2560_CSR1 0x0004 /* System control */ +#define RT2560_CSR3 0x000c /* STA MAC address 0 */ +#define RT2560_CSR4 0x0010 /* STA MAC address 1 */ +#define RT2560_CSR5 0x0014 /* BSSID 0 */ +#define RT2560_CSR6 0x0018 /* BSSID 1 */ +#define RT2560_CSR7 0x001c /* Interrupt source */ +#define RT2560_CSR8 0x0020 /* Interrupt mask */ +#define RT2560_CSR9 0x0024 /* Maximum frame length */ +#define RT2560_SECCSR0 0x0028 /* WEP control */ +#define RT2560_CSR11 0x002c /* Back-off control */ +#define RT2560_CSR12 0x0030 /* Synchronization configuration 0 */ +#define RT2560_CSR13 0x0034 /* Synchronization configuration 1 */ +#define RT2560_CSR14 0x0038 /* Synchronization control */ +#define RT2560_CSR15 0x003c /* Synchronization status */ +#define RT2560_CSR16 0x0040 /* TSF timer 0 */ +#define RT2560_CSR17 0x0044 /* TSF timer 1 */ +#define RT2560_CSR18 0x0048 /* IFS timer 0 */ +#define RT2560_CSR19 0x004c /* IFS timer 1 */ +#define RT2560_CSR20 0x0050 /* WAKEUP timer */ +#define RT2560_CSR21 0x0054 /* EEPROM control */ +#define RT2560_CSR22 0x0058 /* CFP control */ +#define RT2560_TXCSR0 0x0060 /* TX control */ +#define RT2560_TXCSR1 0x0064 /* TX configuration */ +#define RT2560_TXCSR2 0x0068 /* TX descriptor configuration */ +#define RT2560_TXCSR3 0x006c /* TX ring base address */ +#define RT2560_TXCSR4 0x0070 /* TX ATIM ring base address */ +#define RT2560_TXCSR5 0x0074 /* TX PRIO ring base address */ +#define RT2560_TXCSR6 0x0078 /* Beacon base address */ +#define RT2560_TXCSR7 0x007c /* AutoResponder control */ +#define RT2560_RXCSR0 0x0080 /* RX control */ +#define RT2560_RXCSR1 0x0084 /* RX descriptor configuration */ +#define RT2560_RXCSR2 0x0088 /* RX ring base address */ +#define RT2560_PCICSR 0x008c /* PCI control */ +#define RT2560_RXCSR3 0x0090 /* BBP ID 0 */ +#define RT2560_TXCSR9 0x0094 /* OFDM TX BBP */ +#define RT2560_ARSP_PLCP_0 0x0098 /* Auto Responder PLCP address */ +#define RT2560_ARSP_PLCP_1 0x009c /* Auto Responder Basic Rate mask */ +#define RT2560_CNT0 0x00a0 /* FCS error counter */ +#define RT2560_CNT1 0x00ac /* PLCP error counter */ +#define RT2560_CNT2 0x00b0 /* Long error counter */ +#define RT2560_CNT3 0x00b8 /* CCA false alarm counter */ +#define RT2560_CNT4 0x00bc /* RX FIFO Overflow counter */ +#define RT2560_CNT5 0x00c0 /* Tx FIFO Underrun counter */ +#define RT2560_PWRCSR0 0x00c4 /* Power mode configuration */ +#define RT2560_PSCSR0 0x00c8 /* Power state transition time */ +#define RT2560_PSCSR1 0x00cc /* Power state transition time */ +#define RT2560_PSCSR2 0x00d0 /* Power state transition time */ +#define RT2560_PSCSR3 0x00d4 /* Power state transition time */ +#define RT2560_PWRCSR1 0x00d8 /* Manual power control/status */ +#define RT2560_TIMECSR 0x00dc /* Timer control */ +#define RT2560_MACCSR0 0x00e0 /* MAC configuration */ +#define RT2560_MACCSR1 0x00e4 /* MAC configuration */ +#define RT2560_RALINKCSR 0x00e8 /* Ralink RX auto-reset BBCR */ +#define RT2560_BCNCSR 0x00ec /* Beacon interval control */ +#define RT2560_BBPCSR 0x00f0 /* BBP serial control */ +#define RT2560_RFCSR 0x00f4 /* RF serial control */ +#define RT2560_LEDCSR 0x00f8 /* LED control */ +#define RT2560_SECCSR3 0x00fc /* XXX not documented */ +#define RT2560_DMACSR0 0x0100 /* Current RX ring address */ +#define RT2560_DMACSR1 0x0104 /* Current Tx ring address */ +#define RT2560_DMACSR2 0x0104 /* Current Priority ring address */ +#define RT2560_DMACSR3 0x0104 /* Current ATIM ring address */ +#define RT2560_TXACKCSR0 0x0110 /* XXX not documented */ +#define RT2560_GPIOCSR 0x0120 /* */ +#define RT2560_BBBPPCSR 0x0124 /* BBP Pin Control */ +#define RT2560_FIFOCSR0 0x0128 /* TX FIFO pointer */ +#define RT2560_FIFOCSR1 0x012c /* RX FIFO pointer */ +#define RT2560_BCNOCSR 0x0130 /* Beacon time offset */ +#define RT2560_RLPWCSR 0x0134 /* RX_PE Low Width */ +#define RT2560_TESTCSR 0x0138 /* Test Mode Select */ +#define RT2560_PLCP1MCSR 0x013c /* Signal/Service/Length of ACK @1M */ +#define RT2560_PLCP2MCSR 0x0140 /* Signal/Service/Length of ACK @2M */ +#define RT2560_PLCP5p5MCSR 0x0144 /* Signal/Service/Length of ACK @5.5M */ +#define RT2560_PLCP11MCSR 0x0148 /* Signal/Service/Length of ACK @11M */ +#define RT2560_ACKPCTCSR 0x014c /* ACK/CTS padload consume time */ +#define RT2560_ARTCSR1 0x0150 /* ACK/CTS padload consume time */ +#define RT2560_ARTCSR2 0x0154 /* ACK/CTS padload consume time */ +#define RT2560_SECCSR1 0x0158 /* WEP control */ +#define RT2560_BBPCSR1 0x015c /* BBP TX Configuration */ + + +/* possible flags for register RXCSR0 */ +#define RT2560_DISABLE_RX (1 << 0) +#define RT2560_DROP_CRC_ERROR (1 << 1) +#define RT2560_DROP_PHY_ERROR (1 << 2) +#define RT2560_DROP_CTL (1 << 3) +#define RT2560_DROP_NOT_TO_ME (1 << 4) +#define RT2560_DROP_TODS (1 << 5) +#define RT2560_DROP_VERSION_ERROR (1 << 6) + +/* possible flags for register CSR1 */ +#define RT2560_RESET_ASIC (1 << 0) +#define RT2560_RESET_BBP (1 << 1) +#define RT2560_HOST_READY (1 << 2) + +/* possible flags for register CSR14 */ +#define RT2560_ENABLE_TSF (1 << 0) +#define RT2560_ENABLE_TSF_SYNC(x) (((x) & 0x3) << 1) +#define RT2560_ENABLE_TBCN (1 << 3) +#define RT2560_ENABLE_BEACON_GENERATOR (1 << 6) + +/* possible flags for register CSR21 */ +#define RT2560_C (1 << 1) +#define RT2560_S (1 << 2) +#define RT2560_D (1 << 3) +#define RT2560_Q (1 << 4) +#define RT2560_93C46 (1 << 5) + +#define RT2560_SHIFT_D 3 +#define RT2560_SHIFT_Q 4 + +/* possible flags for register TXCSR0 */ +#define RT2560_KICK_TX (1 << 0) +#define RT2560_KICK_ATIM (1 << 1) +#define RT2560_KICK_PRIO (1 << 2) +#define RT2560_ABORT_TX (1 << 3) + +/* possible flags for register SECCSR0 */ +#define RT2560_KICK_DECRYPT (1 << 0) + +/* possible flags for register SECCSR1 */ +#define RT2560_KICK_ENCRYPT (1 << 0) + +/* possible flags for register CSR7 */ +#define RT2560_BEACON_EXPIRE 0x00000001 +#define RT2560_WAKEUP_EXPIRE 0x00000002 +#define RT2560_ATIM_EXPIRE 0x00000004 +#define RT2560_TX_DONE 0x00000008 +#define RT2560_ATIM_DONE 0x00000010 +#define RT2560_PRIO_DONE 0x00000020 +#define RT2560_RX_DONE 0x00000040 +#define RT2560_DECRYPTION_DONE 0x00000080 +#define RT2560_ENCRYPTION_DONE 0x00000100 + +#define RT2560_INTR_MASK \ + (~(RT2560_BEACON_EXPIRE | RT2560_WAKEUP_EXPIRE | RT2560_TX_DONE | \ + RT2560_PRIO_DONE | RT2560_RX_DONE | RT2560_DECRYPTION_DONE | \ + RT2560_ENCRYPTION_DONE)) + +/* Tx descriptor */ +struct rt2560_tx_desc { + uint32_t flags; +#define RT2560_TX_BUSY (1 << 0) +#define RT2560_TX_VALID (1 << 1) + +#define RT2560_TX_RESULT_MASK 0x0000001c +#define RT2560_TX_SUCCESS (0 << 2) +#define RT2560_TX_SUCCESS_RETRY (1 << 2) +#define RT2560_TX_FAIL_RETRY (2 << 2) +#define RT2560_TX_FAIL_INVALID (3 << 2) +#define RT2560_TX_FAIL_OTHER (4 << 2) + +#define RT2560_TX_MORE_FRAG (1 << 8) +#define RT2560_TX_ACK (1 << 9) +#define RT2560_TX_TIMESTAMP (1 << 10) +#define RT2560_TX_OFDM (1 << 11) +#define RT2560_TX_CIPHER_BUSY (1 << 12) + +#define RT2560_TX_IFS_MASK 0x00006000 +#define RT2560_TX_IFS_BACKOFF (0 << 13) +#define RT2560_TX_IFS_SIFS (1 << 13) +#define RT2560_TX_IFS_NEWBACKOFF (2 << 13) +#define RT2560_TX_IFS_NONE (3 << 13) + +#define RT2560_TX_LONG_RETRY (1 << 15) + +#define RT2560_TX_CIPHER_MASK 0xe0000000 +#define RT2560_TX_CIPHER_NONE (0 << 29) +#define RT2560_TX_CIPHER_WEP40 (1 << 29) +#define RT2560_TX_CIPHER_WEP104 (2 << 29) +#define RT2560_TX_CIPHER_TKIP (3 << 29) +#define RT2560_TX_CIPHER_AES (4 << 29) + +#define RT2560_TX_RETRYCNT(v) (((v) >> 5) & 0x7) + + uint32_t physaddr; + uint16_t wme; +#define RT2560_LOGCWMAX(x) (((x) & 0xf) << 12) +#define RT2560_LOGCWMIN(x) (((x) & 0xf) << 8) +#define RT2560_AIFSN(x) (((x) & 0x3) << 6) +#define RT2560_IVOFFSET(x) (((x) & 0x3f)) + + uint16_t reserved1; + uint8_t plcp_signal; + uint8_t plcp_service; +#define RT2560_PLCP_LENGEXT 0x80 + + uint8_t plcp_length_lo; + uint8_t plcp_length_hi; + uint32_t iv; + uint32_t eiv; + uint8_t key[IEEE80211_KEYBUF_SIZE]; + uint32_t reserved2[2]; +} __packed; + +/* Rx descriptor */ +struct rt2560_rx_desc { + uint32_t flags; +#define RT2560_RX_BUSY (1 << 0) +#define RT2560_RX_CRC_ERROR (1 << 5) +#define RT2560_RX_OFDM (1 << 6) +#define RT2560_RX_PHY_ERROR (1 << 7) +#define RT2560_RX_CIPHER_BUSY (1 << 8) +#define RT2560_RX_ICV_ERROR (1 << 9) + +#define RT2560_RX_CIPHER_MASK 0xe0000000 +#define RT2560_RX_CIPHER_NONE (0 << 29) +#define RT2560_RX_CIPHER_WEP40 (1 << 29) +#define RT2560_RX_CIPHER_WEP104 (2 << 29) +#define RT2560_RX_CIPHER_TKIP (3 << 29) +#define RT2560_RX_CIPHER_AES (4 << 29) + + uint32_t physaddr; + uint8_t rate; + uint8_t rssi; + uint8_t ta[IEEE80211_ADDR_LEN]; + uint32_t iv; + uint32_t eiv; + uint8_t key[IEEE80211_KEYBUF_SIZE]; + uint32_t reserved[2]; +} __packed; + +#define RAL_RF1 0 +#define RAL_RF2 2 +#define RAL_RF3 1 +#define RAL_RF4 3 + +#define RT2560_RF1_AUTOTUNE 0x08000 +#define RT2560_RF3_AUTOTUNE 0x00040 + +#define RT2560_BBP_BUSY (1 << 15) +#define RT2560_BBP_WRITE (1 << 16) +#define RT2560_RF_20BIT (20 << 24) +#define RT2560_RF_BUSY (1 << 31) + +#define RT2560_RF_2522 0x00 +#define RT2560_RF_2523 0x01 +#define RT2560_RF_2524 0x02 +#define RT2560_RF_2525 0x03 +#define RT2560_RF_2525E 0x04 +#define RT2560_RF_2526 0x05 +/* dual-band RF */ +#define RT2560_RF_5222 0x10 + +#define RT2560_BBP_VERSION 0 +#define RT2560_BBP_TX 2 +#define RT2560_BBP_RX 14 + +#define RT2560_BBP_ANTA 0x00 +#define RT2560_BBP_DIVERSITY 0x01 +#define RT2560_BBP_ANTB 0x02 +#define RT2560_BBP_ANTMASK 0x03 +#define RT2560_BBP_FLIPIQ 0x04 + +#define RT2560_LED_MODE_DEFAULT 0 +#define RT2560_LED_MODE_TXRX_ACTIVITY 1 +#define RT2560_LED_MODE_SINGLE 2 +#define RT2560_LED_MODE_ASUS 3 + +#define RT2560_JAPAN_FILTER 0x8 + +#define RT2560_EEPROM_DELAY 1 /* minimum hold time (microsecond) */ + +#define RT2560_EEPROM_CONFIG0 16 +#define RT2560_EEPROM_BBP_BASE 19 +#define RT2560_EEPROM_TXPOWER 35 +#define RT2560_EEPROM_CALIBRATE 62 + +/* + * control and status registers access macros + */ +#define RAL_READ(sc, reg) \ + bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) + +#define RAL_WRITE(sc, reg, val) \ + bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) + +/* + * EEPROM access macro + */ +#define RT2560_EEPROM_CTL(sc, val) do { \ + RAL_WRITE((sc), RT2560_CSR21, (val)); \ + DELAY(RT2560_EEPROM_DELAY); \ +} while (/* CONSTCOND */0) + +/* + * Default values for MAC registers; values taken from the reference driver. + */ +#define RT2560_DEF_MAC \ + { RT2560_PSCSR0, 0x00020002 }, \ + { RT2560_PSCSR1, 0x00000002 }, \ + { RT2560_PSCSR2, 0x00020002 }, \ + { RT2560_PSCSR3, 0x00000002 }, \ + { RT2560_TIMECSR, 0x00003f21 }, \ + { RT2560_CSR9, 0x00000780 }, \ + { RT2560_CSR11, 0x07041483 }, \ + { RT2560_CNT3, 0x00000000 }, \ + { RT2560_TXCSR1, 0x07614562 }, \ + { RT2560_ARSP_PLCP_0, 0x8c8d8b8a }, \ + { RT2560_ACKPCTCSR, 0x7038140a }, \ + { RT2560_ARTCSR1, 0x21212929 }, \ + { RT2560_ARTCSR2, 0x1d1d1d1d }, \ + { RT2560_RXCSR0, 0xffffffff }, \ + { RT2560_RXCSR3, 0xb3aab3af }, \ + { RT2560_PCICSR, 0x000003b8 }, \ + { RT2560_PWRCSR0, 0x3f3b3100 }, \ + { RT2560_GPIOCSR, 0x0000ff00 }, \ + { RT2560_TESTCSR, 0x000000f0 }, \ + { RT2560_PWRCSR1, 0x000001ff }, \ + { RT2560_MACCSR0, 0x00213223 }, \ + { RT2560_MACCSR1, 0x00235518 }, \ + { RT2560_RLPWCSR, 0x00000040 }, \ + { RT2560_RALINKCSR, 0x9a009a11 }, \ + { RT2560_CSR7, 0xffffffff }, \ + { RT2560_BBPCSR1, 0x82188200 }, \ + { RT2560_TXACKCSR0, 0x00000020 }, \ + { RT2560_SECCSR3, 0x0000e78f } + +/* + * Default values for BBP registers; values taken from the reference driver. + */ +#define RT2560_DEF_BBP \ + { 3, 0x02 }, \ + { 4, 0x19 }, \ + { 14, 0x1c }, \ + { 15, 0x30 }, \ + { 16, 0xac }, \ + { 17, 0x48 }, \ + { 18, 0x18 }, \ + { 19, 0xff }, \ + { 20, 0x1e }, \ + { 21, 0x08 }, \ + { 22, 0x08 }, \ + { 23, 0x08 }, \ + { 24, 0x80 }, \ + { 25, 0x50 }, \ + { 26, 0x08 }, \ + { 27, 0x23 }, \ + { 30, 0x10 }, \ + { 31, 0x2b }, \ + { 32, 0xb9 }, \ + { 34, 0x12 }, \ + { 35, 0x50 }, \ + { 39, 0xc4 }, \ + { 40, 0x02 }, \ + { 41, 0x60 }, \ + { 53, 0x10 }, \ + { 54, 0x18 }, \ + { 56, 0x08 }, \ + { 57, 0x10 }, \ + { 58, 0x08 }, \ + { 61, 0x60 }, \ + { 62, 0x10 }, \ + { 75, 0xff } + +/* + * Default values for RF register R2 indexed by channel numbers; values taken + * from the reference driver. + */ +#define RT2560_RF2522_R2 \ +{ \ + 0x307f6, 0x307fb, 0x30800, 0x30805, 0x3080a, 0x3080f, 0x30814, \ + 0x30819, 0x3081e, 0x30823, 0x30828, 0x3082d, 0x30832, 0x3083e \ +} + +#define RT2560_RF2523_R2 \ +{ \ + 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, \ + 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 \ +} + +#define RT2560_RF2524_R2 \ +{ \ + 0x00327, 0x00328, 0x00329, 0x0032a, 0x0032b, 0x0032c, 0x0032d, \ + 0x0032e, 0x0032f, 0x00340, 0x00341, 0x00342, 0x00343, 0x00346 \ +} + +#define RT2560_RF2525_R2 \ +{ \ + 0x20327, 0x20328, 0x20329, 0x2032a, 0x2032b, 0x2032c, 0x2032d, \ + 0x2032e, 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20346 \ +} + +#define RT2560_RF2525_HI_R2 \ +{ \ + 0x2032f, 0x20340, 0x20341, 0x20342, 0x20343, 0x20344, 0x20345, \ + 0x20346, 0x20347, 0x20348, 0x20349, 0x2034a, 0x2034b, 0x2034e \ +} + +#define RT2560_RF2525E_R2 \ +{ \ + 0x2044d, 0x2044e, 0x2044f, 0x20460, 0x20461, 0x20462, 0x20463, \ + 0x20464, 0x20465, 0x20466, 0x20467, 0x20468, 0x20469, 0x2046b \ +} + +#define RT2560_RF2526_HI_R2 \ +{ \ + 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d, 0x0022d, \ + 0x0022e, 0x0022e, 0x0022f, 0x0022d, 0x00240, 0x00240, 0x00241 \ +} + +#define RT2560_RF2526_R2 \ +{ \ + 0x00226, 0x00227, 0x00227, 0x00228, 0x00228, 0x00229, 0x00229, \ + 0x0022a, 0x0022a, 0x0022b, 0x0022b, 0x0022c, 0x0022c, 0x0022d \ +} + +/* + * For dual-band RF, RF registers R1 and R4 also depend on channel number; + * values taken from the reference driver. + */ +#define RT2560_RF5222 \ + { 1, 0x08808, 0x0044d, 0x00282 }, \ + { 2, 0x08808, 0x0044e, 0x00282 }, \ + { 3, 0x08808, 0x0044f, 0x00282 }, \ + { 4, 0x08808, 0x00460, 0x00282 }, \ + { 5, 0x08808, 0x00461, 0x00282 }, \ + { 6, 0x08808, 0x00462, 0x00282 }, \ + { 7, 0x08808, 0x00463, 0x00282 }, \ + { 8, 0x08808, 0x00464, 0x00282 }, \ + { 9, 0x08808, 0x00465, 0x00282 }, \ + { 10, 0x08808, 0x00466, 0x00282 }, \ + { 11, 0x08808, 0x00467, 0x00282 }, \ + { 12, 0x08808, 0x00468, 0x00282 }, \ + { 13, 0x08808, 0x00469, 0x00282 }, \ + { 14, 0x08808, 0x0046b, 0x00286 }, \ + \ + { 36, 0x08804, 0x06225, 0x00287 }, \ + { 40, 0x08804, 0x06226, 0x00287 }, \ + { 44, 0x08804, 0x06227, 0x00287 }, \ + { 48, 0x08804, 0x06228, 0x00287 }, \ + { 52, 0x08804, 0x06229, 0x00287 }, \ + { 56, 0x08804, 0x0622a, 0x00287 }, \ + { 60, 0x08804, 0x0622b, 0x00287 }, \ + { 64, 0x08804, 0x0622c, 0x00287 }, \ + \ + { 100, 0x08804, 0x02200, 0x00283 }, \ + { 104, 0x08804, 0x02201, 0x00283 }, \ + { 108, 0x08804, 0x02202, 0x00283 }, \ + { 112, 0x08804, 0x02203, 0x00283 }, \ + { 116, 0x08804, 0x02204, 0x00283 }, \ + { 120, 0x08804, 0x02205, 0x00283 }, \ + { 124, 0x08804, 0x02206, 0x00283 }, \ + { 128, 0x08804, 0x02207, 0x00283 }, \ + { 132, 0x08804, 0x02208, 0x00283 }, \ + { 136, 0x08804, 0x02209, 0x00283 }, \ + { 140, 0x08804, 0x0220a, 0x00283 }, \ + \ + { 149, 0x08808, 0x02429, 0x00281 }, \ + { 153, 0x08808, 0x0242b, 0x00281 }, \ + { 157, 0x08808, 0x0242d, 0x00281 }, \ + { 161, 0x08808, 0x0242f, 0x00281 } diff --git a/src/add-ons/kernel/drivers/network/wlan/ralinkwifi/dev/ral/rt2560var.h b/src/add-ons/kernel/drivers/network/wlan/ralinkwifi/dev/ral/rt2560var.h new file mode 100644 index 0000000000..288577b626 --- /dev/null +++ b/src/add-ons/kernel/drivers/network/wlan/ralinkwifi/dev/ral/rt2560var.h @@ -0,0 +1,175 @@ +/* $FreeBSD$ */ + +/*- + * Copyright (c) 2005, 2006 + * Damien Bergamini + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +struct rt2560_rx_radiotap_header { + struct ieee80211_radiotap_header wr_ihdr; + uint64_t wr_tsf; + uint8_t wr_flags; + uint8_t wr_rate; + uint16_t wr_chan_freq; + uint16_t wr_chan_flags; + int8_t wr_antsignal; + int8_t wr_antnoise; + uint8_t wr_antenna; +}; + +#define RT2560_RX_RADIOTAP_PRESENT \ + ((1 << IEEE80211_RADIOTAP_TSFT) | \ + (1 << IEEE80211_RADIOTAP_FLAGS) | \ + (1 << IEEE80211_RADIOTAP_RATE) | \ + (1 << IEEE80211_RADIOTAP_CHANNEL) | \ + (1 << IEEE80211_RADIOTAP_ANTENNA) | \ + (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \ + (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE)) + +struct rt2560_tx_radiotap_header { + struct ieee80211_radiotap_header wt_ihdr; + uint8_t wt_flags; + uint8_t wt_rate; + uint16_t wt_chan_freq; + uint16_t wt_chan_flags; + uint8_t wt_antenna; +}; + +#define RT2560_TX_RADIOTAP_PRESENT \ + ((1 << IEEE80211_RADIOTAP_FLAGS) | \ + (1 << IEEE80211_RADIOTAP_RATE) | \ + (1 << IEEE80211_RADIOTAP_CHANNEL) | \ + (1 << IEEE80211_RADIOTAP_ANTENNA)) + +struct rt2560_tx_data { + bus_dmamap_t map; + struct mbuf *m; + struct ieee80211_node *ni; + uint8_t rix; + int8_t rssi; +}; + +struct rt2560_tx_ring { + bus_dma_tag_t desc_dmat; + bus_dma_tag_t data_dmat; + bus_dmamap_t desc_map; + bus_addr_t physaddr; + struct rt2560_tx_desc *desc; + struct rt2560_tx_data *data; + int count; + int queued; + int cur; + int next; + int cur_encrypt; + int next_encrypt; +}; + +struct rt2560_rx_data { + bus_dmamap_t map; + struct mbuf *m; + int drop; +}; + +struct rt2560_rx_ring { + bus_dma_tag_t desc_dmat; + bus_dma_tag_t data_dmat; + bus_dmamap_t desc_map; + bus_addr_t physaddr; + struct rt2560_rx_desc *desc; + struct rt2560_rx_data *data; + int count; + int cur; + int next; + int cur_decrypt; +}; + +struct rt2560_node { + struct ieee80211_node ni; + struct ieee80211_amrr_node amrr; +}; +#define RT2560_NODE(ni) ((struct rt2560_node *)(ni)) + +struct rt2560_vap { + struct ieee80211vap ral_vap; + struct ieee80211_beacon_offsets ral_bo; + struct ieee80211_amrr amrr; + + int (*ral_newstate)(struct ieee80211vap *, + enum ieee80211_state, int); +}; +#define RT2560_VAP(vap) ((struct rt2560_vap *)(vap)) + +struct rt2560_softc { + struct ifnet *sc_ifp; + device_t sc_dev; + bus_space_tag_t sc_st; + bus_space_handle_t sc_sh; + + struct mtx sc_mtx; + + struct callout watchdog_ch; + + int sc_tx_timer; + int sc_invalid; + int sc_debug; +/* + * The same in both up to here + * ------------------------------------------------ + */ + uint32_t asic_rev; + uint32_t eeprom_rev; + uint8_t rf_rev; + uint8_t rssi_corr; + + struct rt2560_tx_ring txq; + struct rt2560_tx_ring prioq; + struct rt2560_tx_ring atimq; + struct rt2560_tx_ring bcnq; + struct rt2560_rx_ring rxq; + + uint32_t rf_regs[4]; + uint8_t txpow[14]; + + struct { + uint8_t reg; + uint8_t val; + } bbp_prom[16]; + + int led_mode; + int hw_radio; + int rx_ant; + int tx_ant; + int nb_ant; + + struct rt2560_rx_radiotap_header sc_rxtap; + int sc_rxtap_len; + + struct rt2560_tx_radiotap_header sc_txtap; + int sc_txtap_len; +#define RT2560_F_INPUT_RUNNING 0x1 +#define RT2560_F_PRIO_OACTIVE 0x2 +#define RT2560_F_DATA_OACTIVE 0x4 + int sc_flags; +}; + +int rt2560_attach(device_t, int); +int rt2560_detach(void *); +void rt2560_stop(void *); +void rt2560_resume(void *); +void rt2560_intr(void *); + +#define RAL_LOCK(sc) mtx_lock(&(sc)->sc_mtx) +#define RAL_LOCK_ASSERT(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED) +#define RAL_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx) diff --git a/src/add-ons/kernel/drivers/network/wlan/ralinkwifi/dev/ral/rt2661.c b/src/add-ons/kernel/drivers/network/wlan/ralinkwifi/dev/ral/rt2661.c new file mode 100644 index 0000000000..9e6693f43d --- /dev/null +++ b/src/add-ons/kernel/drivers/network/wlan/ralinkwifi/dev/ral/rt2661.c @@ -0,0 +1,2878 @@ +/* $FreeBSD$ */ + +/*- + * Copyright (c) 2006 + * Damien Bergamini + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#include +__FBSDID("$FreeBSD$"); + +/*- + * Ralink Technology RT2561, RT2561S and RT2661 chipset driver + * http://www.ralinktech.com/ + */ + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include + +#include +#include +#include +#include +#include +#include +#include + +#include +#include +#include +#include + +#include +#include +#include +#include +#include + +#include +#include + +#define RAL_DEBUG +#ifdef RAL_DEBUG +#define DPRINTF(sc, fmt, ...) do { \ + if (sc->sc_debug > 0) \ + printf(fmt, __VA_ARGS__); \ +} while (0) +#define DPRINTFN(sc, n, fmt, ...) do { \ + if (sc->sc_debug >= (n)) \ + printf(fmt, __VA_ARGS__); \ +} while (0) +#else +#define DPRINTF(sc, fmt, ...) +#define DPRINTFN(sc, n, fmt, ...) +#endif + +static struct ieee80211vap *rt2661_vap_create(struct ieee80211com *, + const char name[IFNAMSIZ], int unit, int opmode, + int flags, const uint8_t bssid[IEEE80211_ADDR_LEN], + const uint8_t mac[IEEE80211_ADDR_LEN]); +static void rt2661_vap_delete(struct ieee80211vap *); +static void rt2661_dma_map_addr(void *, bus_dma_segment_t *, int, + int); +static int rt2661_alloc_tx_ring(struct rt2661_softc *, + struct rt2661_tx_ring *, int); +static void rt2661_reset_tx_ring(struct rt2661_softc *, + struct rt2661_tx_ring *); +static void rt2661_free_tx_ring(struct rt2661_softc *, + struct rt2661_tx_ring *); +static int rt2661_alloc_rx_ring(struct rt2661_softc *, + struct rt2661_rx_ring *, int); +static void rt2661_reset_rx_ring(struct rt2661_softc *, + struct rt2661_rx_ring *); +static void rt2661_free_rx_ring(struct rt2661_softc *, + struct rt2661_rx_ring *); +static struct ieee80211_node *rt2661_node_alloc(struct ieee80211vap *, + const uint8_t [IEEE80211_ADDR_LEN]); +static void rt2661_newassoc(struct ieee80211_node *, int); +static int rt2661_newstate(struct ieee80211vap *, + enum ieee80211_state, int); +static uint16_t rt2661_eeprom_read(struct rt2661_softc *, uint8_t); +static void rt2661_rx_intr(struct rt2661_softc *); +static void rt2661_tx_intr(struct rt2661_softc *); +static void rt2661_tx_dma_intr(struct rt2661_softc *, + struct rt2661_tx_ring *); +static void rt2661_mcu_beacon_expire(struct rt2661_softc *); +static void rt2661_mcu_wakeup(struct rt2661_softc *); +static void rt2661_mcu_cmd_intr(struct rt2661_softc *); +static void rt2661_scan_start(struct ieee80211com *); +static void rt2661_scan_end(struct ieee80211com *); +static void rt2661_set_channel(struct ieee80211com *); +static void rt2661_setup_tx_desc(struct rt2661_softc *, + struct rt2661_tx_desc *, uint32_t, uint16_t, int, + int, const bus_dma_segment_t *, int, int); +static int rt2661_tx_data(struct rt2661_softc *, struct mbuf *, + struct ieee80211_node *, int); +static int rt2661_tx_mgt(struct rt2661_softc *, struct mbuf *, + struct ieee80211_node *); +static void rt2661_start_locked(struct ifnet *); +static void rt2661_start(struct ifnet *); +static int rt2661_raw_xmit(struct ieee80211_node *, struct mbuf *, + const struct ieee80211_bpf_params *); +static void rt2661_watchdog(void *); +static int rt2661_ioctl(struct ifnet *, u_long, caddr_t); +static void rt2661_bbp_write(struct rt2661_softc *, uint8_t, + uint8_t); +static uint8_t rt2661_bbp_read(struct rt2661_softc *, uint8_t); +static void rt2661_rf_write(struct rt2661_softc *, uint8_t, + uint32_t); +static int rt2661_tx_cmd(struct rt2661_softc *, uint8_t, + uint16_t); +static void rt2661_select_antenna(struct rt2661_softc *); +static void rt2661_enable_mrr(struct rt2661_softc *); +static void rt2661_set_txpreamble(struct rt2661_softc *); +static void rt2661_set_basicrates(struct rt2661_softc *, + const struct ieee80211_rateset *); +static void rt2661_select_band(struct rt2661_softc *, + struct ieee80211_channel *); +static void rt2661_set_chan(struct rt2661_softc *, + struct ieee80211_channel *); +static void rt2661_set_bssid(struct rt2661_softc *, + const uint8_t *); +static void rt2661_set_macaddr(struct rt2661_softc *, + const uint8_t *); +static void rt2661_update_promisc(struct ifnet *); +static int rt2661_wme_update(struct ieee80211com *) __unused; +static void rt2661_update_slot(struct ifnet *); +static const char *rt2661_get_rf(int); +static void rt2661_read_eeprom(struct rt2661_softc *, + uint8_t macaddr[IEEE80211_ADDR_LEN]); +static int rt2661_bbp_init(struct rt2661_softc *); +static void rt2661_init_locked(struct rt2661_softc *); +static void rt2661_init(void *); +static void rt2661_stop_locked(struct rt2661_softc *); +static void rt2661_stop(void *); +static int rt2661_load_microcode(struct rt2661_softc *); +#ifdef notyet +static void rt2661_rx_tune(struct rt2661_softc *); +static void rt2661_radar_start(struct rt2661_softc *); +static int rt2661_radar_stop(struct rt2661_softc *); +#endif +static int rt2661_prepare_beacon(struct rt2661_softc *, + struct ieee80211vap *); +static void rt2661_enable_tsf_sync(struct rt2661_softc *); +static void rt2661_enable_tsf(struct rt2661_softc *); +static int rt2661_get_rssi(struct rt2661_softc *, uint8_t); + +static const struct { + uint32_t reg; + uint32_t val; +} rt2661_def_mac[] = { + RT2661_DEF_MAC +}; + +static const struct { + uint8_t reg; + uint8_t val; +} rt2661_def_bbp[] = { + RT2661_DEF_BBP +}; + +static const struct rfprog { + uint8_t chan; + uint32_t r1, r2, r3, r4; +} rt2661_rf5225_1[] = { + RT2661_RF5225_1 +}, rt2661_rf5225_2[] = { + RT2661_RF5225_2 +}; + +int +rt2661_attach(device_t dev, int id) +{ + struct rt2661_softc *sc = device_get_softc(dev); + struct ieee80211com *ic; + struct ifnet *ifp; + uint32_t val; + int error, ac, ntries; + uint8_t bands; + uint8_t macaddr[IEEE80211_ADDR_LEN]; + + sc->sc_id = id; + sc->sc_dev = dev; + + ifp = sc->sc_ifp = if_alloc(IFT_IEEE80211); + if (ifp == NULL) { + device_printf(sc->sc_dev, "can not if_alloc()\n"); + return ENOMEM; + } + ic = ifp->if_l2com; + + mtx_init(&sc->sc_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, + MTX_DEF | MTX_RECURSE); + + callout_init_mtx(&sc->watchdog_ch, &sc->sc_mtx, 0); + + /* wait for NIC to initialize */ + for (ntries = 0; ntries < 1000; ntries++) { + if ((val = RAL_READ(sc, RT2661_MAC_CSR0)) != 0) + break; + DELAY(1000); + } + if (ntries == 1000) { + device_printf(sc->sc_dev, + "timeout waiting for NIC to initialize\n"); + error = EIO; + goto fail1; + } + + /* retrieve RF rev. no and various other things from EEPROM */ + rt2661_read_eeprom(sc, macaddr); + + device_printf(dev, "MAC/BBP RT%X, RF %s\n", val, + rt2661_get_rf(sc->rf_rev)); + + /* + * Allocate Tx and Rx rings. + */ + for (ac = 0; ac < 4; ac++) { + error = rt2661_alloc_tx_ring(sc, &sc->txq[ac], + RT2661_TX_RING_COUNT); + if (error != 0) { + device_printf(sc->sc_dev, + "could not allocate Tx ring %d\n", ac); + goto fail2; + } + } + + error = rt2661_alloc_tx_ring(sc, &sc->mgtq, RT2661_MGT_RING_COUNT); + if (error != 0) { + device_printf(sc->sc_dev, "could not allocate Mgt ring\n"); + goto fail2; + } + + error = rt2661_alloc_rx_ring(sc, &sc->rxq, RT2661_RX_RING_COUNT); + if (error != 0) { + device_printf(sc->sc_dev, "could not allocate Rx ring\n"); + goto fail3; + } + + ifp->if_softc = sc; + if_initname(ifp, device_get_name(dev), device_get_unit(dev)); + ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; + ifp->if_init = rt2661_init; + ifp->if_ioctl = rt2661_ioctl; + ifp->if_start = rt2661_start; + IFQ_SET_MAXLEN(&ifp->if_snd, IFQ_MAXLEN); + ifp->if_snd.ifq_drv_maxlen = IFQ_MAXLEN; + IFQ_SET_READY(&ifp->if_snd); + + ic->ic_ifp = ifp; + ic->ic_opmode = IEEE80211_M_STA; + ic->ic_phytype = IEEE80211_T_OFDM; /* not only, but not used */ + + /* set device capabilities */ + ic->ic_caps = + IEEE80211_C_STA /* station mode */ + | IEEE80211_C_IBSS /* ibss, nee adhoc, mode */ + | IEEE80211_C_HOSTAP /* hostap mode */ + | IEEE80211_C_MONITOR /* monitor mode */ + | IEEE80211_C_AHDEMO /* adhoc demo mode */ + | IEEE80211_C_WDS /* 4-address traffic works */ + | IEEE80211_C_MBSS /* mesh point link mode */ + | IEEE80211_C_SHPREAMBLE /* short preamble supported */ + | IEEE80211_C_SHSLOT /* short slot time supported */ + | IEEE80211_C_WPA /* capable of WPA1+WPA2 */ + | IEEE80211_C_BGSCAN /* capable of bg scanning */ +#ifdef notyet + | IEEE80211_C_TXFRAG /* handle tx frags */ + | IEEE80211_C_WME /* 802.11e */ +#endif + ; + + bands = 0; + setbit(&bands, IEEE80211_MODE_11B); + setbit(&bands, IEEE80211_MODE_11G); + if (sc->rf_rev == RT2661_RF_5225 || sc->rf_rev == RT2661_RF_5325) + setbit(&bands, IEEE80211_MODE_11A); + ieee80211_init_channels(ic, NULL, &bands); + + ieee80211_ifattach(ic, macaddr); + ic->ic_newassoc = rt2661_newassoc; + ic->ic_node_alloc = rt2661_node_alloc; +#if 0 + ic->ic_wme.wme_update = rt2661_wme_update; +#endif + ic->ic_scan_start = rt2661_scan_start; + ic->ic_scan_end = rt2661_scan_end; + ic->ic_set_channel = rt2661_set_channel; + ic->ic_updateslot = rt2661_update_slot; + ic->ic_update_promisc = rt2661_update_promisc; + ic->ic_raw_xmit = rt2661_raw_xmit; + + ic->ic_vap_create = rt2661_vap_create; + ic->ic_vap_delete = rt2661_vap_delete; + + ieee80211_radiotap_attach(ic, + &sc->sc_txtap.wt_ihdr, sizeof(sc->sc_txtap), + RT2661_TX_RADIOTAP_PRESENT, + &sc->sc_rxtap.wr_ihdr, sizeof(sc->sc_rxtap), + RT2661_RX_RADIOTAP_PRESENT); + +#ifdef RAL_DEBUG + SYSCTL_ADD_INT(device_get_sysctl_ctx(dev), + SYSCTL_CHILDREN(device_get_sysctl_tree(dev)), OID_AUTO, + "debug", CTLFLAG_RW, &sc->sc_debug, 0, "debug msgs"); +#endif + if (bootverbose) + ieee80211_announce(ic); + + return 0; + +fail3: rt2661_free_tx_ring(sc, &sc->mgtq); +fail2: while (--ac >= 0) + rt2661_free_tx_ring(sc, &sc->txq[ac]); +fail1: mtx_destroy(&sc->sc_mtx); + if_free(ifp); + return error; +} + +int +rt2661_detach(void *xsc) +{ + struct rt2661_softc *sc = xsc; + struct ifnet *ifp = sc->sc_ifp; + struct ieee80211com *ic = ifp->if_l2com; + + RAL_LOCK(sc); + rt2661_stop_locked(sc); + RAL_UNLOCK(sc); + + ieee80211_ifdetach(ic); + + rt2661_free_tx_ring(sc, &sc->txq[0]); + rt2661_free_tx_ring(sc, &sc->txq[1]); + rt2661_free_tx_ring(sc, &sc->txq[2]); + rt2661_free_tx_ring(sc, &sc->txq[3]); + rt2661_free_tx_ring(sc, &sc->mgtq); + rt2661_free_rx_ring(sc, &sc->rxq); + + if_free(ifp); + + mtx_destroy(&sc->sc_mtx); + + return 0; +} + +static struct ieee80211vap * +rt2661_vap_create(struct ieee80211com *ic, + const char name[IFNAMSIZ], int unit, int opmode, int flags, + const uint8_t bssid[IEEE80211_ADDR_LEN], + const uint8_t mac[IEEE80211_ADDR_LEN]) +{ + struct ifnet *ifp = ic->ic_ifp; + struct rt2661_vap *rvp; + struct ieee80211vap *vap; + + switch (opmode) { + case IEEE80211_M_STA: + case IEEE80211_M_IBSS: + case IEEE80211_M_AHDEMO: + case IEEE80211_M_MONITOR: + case IEEE80211_M_HOSTAP: + case IEEE80211_M_MBSS: + /* XXXRP: TBD */ + if (!TAILQ_EMPTY(&ic->ic_vaps)) { + if_printf(ifp, "only 1 vap supported\n"); + return NULL; + } + if (opmode == IEEE80211_M_STA) + flags |= IEEE80211_CLONE_NOBEACONS; + break; + case IEEE80211_M_WDS: + if (TAILQ_EMPTY(&ic->ic_vaps) || + ic->ic_opmode != IEEE80211_M_HOSTAP) { + if_printf(ifp, "wds only supported in ap mode\n"); + return NULL; + } + /* + * Silently remove any request for a unique + * bssid; WDS vap's always share the local + * mac address. + */ + flags &= ~IEEE80211_CLONE_BSSID; + break; + default: + if_printf(ifp, "unknown opmode %d\n", opmode); + return NULL; + } + rvp = (struct rt2661_vap *) malloc(sizeof(struct rt2661_vap), + M_80211_VAP, M_NOWAIT | M_ZERO); + if (rvp == NULL) + return NULL; + vap = &rvp->ral_vap; + ieee80211_vap_setup(ic, vap, name, unit, opmode, flags, bssid, mac); + + /* override state transition machine */ + rvp->ral_newstate = vap->iv_newstate; + vap->iv_newstate = rt2661_newstate; +#if 0 + vap->iv_update_beacon = rt2661_beacon_update; +#endif + + ieee80211_amrr_init(&rvp->amrr, vap, + IEEE80211_AMRR_MIN_SUCCESS_THRESHOLD, + IEEE80211_AMRR_MAX_SUCCESS_THRESHOLD, + 500 /* ms */); + + /* complete setup */ + ieee80211_vap_attach(vap, ieee80211_media_change, ieee80211_media_status); + if (TAILQ_FIRST(&ic->ic_vaps) == vap) + ic->ic_opmode = opmode; + return vap; +} + +static void +rt2661_vap_delete(struct ieee80211vap *vap) +{ + struct rt2661_vap *rvp = RT2661_VAP(vap); + + ieee80211_amrr_cleanup(&rvp->amrr); + ieee80211_vap_detach(vap); + free(rvp, M_80211_VAP); +} + +void +rt2661_shutdown(void *xsc) +{ + struct rt2661_softc *sc = xsc; + + rt2661_stop(sc); +} + +void +rt2661_suspend(void *xsc) +{ + struct rt2661_softc *sc = xsc; + + rt2661_stop(sc); +} + +void +rt2661_resume(void *xsc) +{ + struct rt2661_softc *sc = xsc; + struct ifnet *ifp = sc->sc_ifp; + + if (ifp->if_flags & IFF_UP) + rt2661_init(sc); +} + +static void +rt2661_dma_map_addr(void *arg, bus_dma_segment_t *segs, int nseg, int error) +{ + if (error != 0) + return; + + KASSERT(nseg == 1, ("too many DMA segments, %d should be 1", nseg)); + + *(bus_addr_t *)arg = segs[0].ds_addr; +} + +static int +rt2661_alloc_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring, + int count) +{ + int i, error; + + ring->count = count; + ring->queued = 0; + ring->cur = ring->next = ring->stat = 0; + + error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0, + BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, + count * RT2661_TX_DESC_SIZE, 1, count * RT2661_TX_DESC_SIZE, + 0, NULL, NULL, &ring->desc_dmat); + if (error != 0) { + device_printf(sc->sc_dev, "could not create desc DMA tag\n"); + goto fail; + } + + error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, + BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); + if (error != 0) { + device_printf(sc->sc_dev, "could not allocate DMA memory\n"); + goto fail; + } + + error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, + count * RT2661_TX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, + 0); + if (error != 0) { + device_printf(sc->sc_dev, "could not load desc DMA map\n"); + goto fail; + } + + ring->data = malloc(count * sizeof (struct rt2661_tx_data), M_DEVBUF, + M_NOWAIT | M_ZERO); + if (ring->data == NULL) { + device_printf(sc->sc_dev, "could not allocate soft data\n"); + error = ENOMEM; + goto fail; + } + + error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, + BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, + RT2661_MAX_SCATTER, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); + if (error != 0) { + device_printf(sc->sc_dev, "could not create data DMA tag\n"); + goto fail; + } + + for (i = 0; i < count; i++) { + error = bus_dmamap_create(ring->data_dmat, 0, + &ring->data[i].map); + if (error != 0) { + device_printf(sc->sc_dev, "could not create DMA map\n"); + goto fail; + } + } + + return 0; + +fail: rt2661_free_tx_ring(sc, ring); + return error; +} + +static void +rt2661_reset_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) +{ + struct rt2661_tx_desc *desc; + struct rt2661_tx_data *data; + int i; + + for (i = 0; i < ring->count; i++) { + desc = &ring->desc[i]; + data = &ring->data[i]; + + if (data->m != NULL) { + bus_dmamap_sync(ring->data_dmat, data->map, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(ring->data_dmat, data->map); + m_freem(data->m); + data->m = NULL; + } + + if (data->ni != NULL) { + ieee80211_free_node(data->ni); + data->ni = NULL; + } + + desc->flags = 0; + } + + bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); + + ring->queued = 0; + ring->cur = ring->next = ring->stat = 0; +} + +static void +rt2661_free_tx_ring(struct rt2661_softc *sc, struct rt2661_tx_ring *ring) +{ + struct rt2661_tx_data *data; + int i; + + if (ring->desc != NULL) { + bus_dmamap_sync(ring->desc_dmat, ring->desc_map, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(ring->desc_dmat, ring->desc_map); + bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); + } + + if (ring->desc_dmat != NULL) + bus_dma_tag_destroy(ring->desc_dmat); + + if (ring->data != NULL) { + for (i = 0; i < ring->count; i++) { + data = &ring->data[i]; + + if (data->m != NULL) { + bus_dmamap_sync(ring->data_dmat, data->map, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(ring->data_dmat, data->map); + m_freem(data->m); + } + + if (data->ni != NULL) + ieee80211_free_node(data->ni); + + if (data->map != NULL) + bus_dmamap_destroy(ring->data_dmat, data->map); + } + + free(ring->data, M_DEVBUF); + } + + if (ring->data_dmat != NULL) + bus_dma_tag_destroy(ring->data_dmat); +} + +static int +rt2661_alloc_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring, + int count) +{ + struct rt2661_rx_desc *desc; + struct rt2661_rx_data *data; + bus_addr_t physaddr; + int i, error; + + ring->count = count; + ring->cur = ring->next = 0; + + error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 4, 0, + BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, + count * RT2661_RX_DESC_SIZE, 1, count * RT2661_RX_DESC_SIZE, + 0, NULL, NULL, &ring->desc_dmat); + if (error != 0) { + device_printf(sc->sc_dev, "could not create desc DMA tag\n"); + goto fail; + } + + error = bus_dmamem_alloc(ring->desc_dmat, (void **)&ring->desc, + BUS_DMA_NOWAIT | BUS_DMA_ZERO, &ring->desc_map); + if (error != 0) { + device_printf(sc->sc_dev, "could not allocate DMA memory\n"); + goto fail; + } + + error = bus_dmamap_load(ring->desc_dmat, ring->desc_map, ring->desc, + count * RT2661_RX_DESC_SIZE, rt2661_dma_map_addr, &ring->physaddr, + 0); + if (error != 0) { + device_printf(sc->sc_dev, "could not load desc DMA map\n"); + goto fail; + } + + ring->data = malloc(count * sizeof (struct rt2661_rx_data), M_DEVBUF, + M_NOWAIT | M_ZERO); + if (ring->data == NULL) { + device_printf(sc->sc_dev, "could not allocate soft data\n"); + error = ENOMEM; + goto fail; + } + + /* + * Pre-allocate Rx buffers and populate Rx ring. + */ + error = bus_dma_tag_create(bus_get_dma_tag(sc->sc_dev), 1, 0, + BUS_SPACE_MAXADDR_32BIT, BUS_SPACE_MAXADDR, NULL, NULL, MCLBYTES, + 1, MCLBYTES, 0, NULL, NULL, &ring->data_dmat); + if (error != 0) { + device_printf(sc->sc_dev, "could not create data DMA tag\n"); + goto fail; + } + + for (i = 0; i < count; i++) { + desc = &sc->rxq.desc[i]; + data = &sc->rxq.data[i]; + + error = bus_dmamap_create(ring->data_dmat, 0, &data->map); + if (error != 0) { + device_printf(sc->sc_dev, "could not create DMA map\n"); + goto fail; + } + + data->m = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + if (data->m == NULL) { + device_printf(sc->sc_dev, + "could not allocate rx mbuf\n"); + error = ENOMEM; + goto fail; + } + + error = bus_dmamap_load(ring->data_dmat, data->map, + mtod(data->m, void *), MCLBYTES, rt2661_dma_map_addr, + &physaddr, 0); + if (error != 0) { + device_printf(sc->sc_dev, + "could not load rx buf DMA map"); + goto fail; + } + + desc->flags = htole32(RT2661_RX_BUSY); + desc->physaddr = htole32(physaddr); + } + + bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); + + return 0; + +fail: rt2661_free_rx_ring(sc, ring); + return error; +} + +static void +rt2661_reset_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) +{ + int i; + + for (i = 0; i < ring->count; i++) + ring->desc[i].flags = htole32(RT2661_RX_BUSY); + + bus_dmamap_sync(ring->desc_dmat, ring->desc_map, BUS_DMASYNC_PREWRITE); + + ring->cur = ring->next = 0; +} + +static void +rt2661_free_rx_ring(struct rt2661_softc *sc, struct rt2661_rx_ring *ring) +{ + struct rt2661_rx_data *data; + int i; + + if (ring->desc != NULL) { + bus_dmamap_sync(ring->desc_dmat, ring->desc_map, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(ring->desc_dmat, ring->desc_map); + bus_dmamem_free(ring->desc_dmat, ring->desc, ring->desc_map); + } + + if (ring->desc_dmat != NULL) + bus_dma_tag_destroy(ring->desc_dmat); + + if (ring->data != NULL) { + for (i = 0; i < ring->count; i++) { + data = &ring->data[i]; + + if (data->m != NULL) { + bus_dmamap_sync(ring->data_dmat, data->map, + BUS_DMASYNC_POSTREAD); + bus_dmamap_unload(ring->data_dmat, data->map); + m_freem(data->m); + } + + if (data->map != NULL) + bus_dmamap_destroy(ring->data_dmat, data->map); + } + + free(ring->data, M_DEVBUF); + } + + if (ring->data_dmat != NULL) + bus_dma_tag_destroy(ring->data_dmat); +} + +static struct ieee80211_node * +rt2661_node_alloc(struct ieee80211vap *vap, + const uint8_t mac[IEEE80211_ADDR_LEN]) +{ + struct rt2661_node *rn; + + rn = malloc(sizeof (struct rt2661_node), M_80211_NODE, + M_NOWAIT | M_ZERO); + + return (rn != NULL) ? &rn->ni : NULL; +} + +static void +rt2661_newassoc(struct ieee80211_node *ni, int isnew) +{ + struct ieee80211vap *vap = ni->ni_vap; + + ieee80211_amrr_node_init(&RT2661_VAP(vap)->amrr, + &RT2661_NODE(ni)->amrr, ni); +} + +static int +rt2661_newstate(struct ieee80211vap *vap, enum ieee80211_state nstate, int arg) +{ + struct rt2661_vap *rvp = RT2661_VAP(vap); + struct ieee80211com *ic = vap->iv_ic; + struct rt2661_softc *sc = ic->ic_ifp->if_softc; + int error; + + if (nstate == IEEE80211_S_INIT && vap->iv_state == IEEE80211_S_RUN) { + uint32_t tmp; + + /* abort TSF synchronization */ + tmp = RAL_READ(sc, RT2661_TXRX_CSR9); + RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0x00ffffff); + } + + error = rvp->ral_newstate(vap, nstate, arg); + + if (error == 0 && nstate == IEEE80211_S_RUN) { + struct ieee80211_node *ni = vap->iv_bss; + + if (vap->iv_opmode != IEEE80211_M_MONITOR) { + rt2661_enable_mrr(sc); + rt2661_set_txpreamble(sc); + rt2661_set_basicrates(sc, &ni->ni_rates); + rt2661_set_bssid(sc, ni->ni_bssid); + } + + if (vap->iv_opmode == IEEE80211_M_HOSTAP || + vap->iv_opmode == IEEE80211_M_IBSS || + vap->iv_opmode == IEEE80211_M_MBSS) { + error = rt2661_prepare_beacon(sc, vap); + if (error != 0) + return error; + } + if (vap->iv_opmode != IEEE80211_M_MONITOR) + rt2661_enable_tsf_sync(sc); + else + rt2661_enable_tsf(sc); + } + return error; +} + +/* + * Read 16 bits at address 'addr' from the serial EEPROM (either 93C46 or + * 93C66). + */ +static uint16_t +rt2661_eeprom_read(struct rt2661_softc *sc, uint8_t addr) +{ + uint32_t tmp; + uint16_t val; + int n; + + /* clock C once before the first command */ + RT2661_EEPROM_CTL(sc, 0); + + RT2661_EEPROM_CTL(sc, RT2661_S); + RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); + RT2661_EEPROM_CTL(sc, RT2661_S); + + /* write start bit (1) */ + RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); + RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); + + /* write READ opcode (10) */ + RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D); + RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_D | RT2661_C); + RT2661_EEPROM_CTL(sc, RT2661_S); + RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); + + /* write address (A5-A0 or A7-A0) */ + n = (RAL_READ(sc, RT2661_E2PROM_CSR) & RT2661_93C46) ? 5 : 7; + for (; n >= 0; n--) { + RT2661_EEPROM_CTL(sc, RT2661_S | + (((addr >> n) & 1) << RT2661_SHIFT_D)); + RT2661_EEPROM_CTL(sc, RT2661_S | + (((addr >> n) & 1) << RT2661_SHIFT_D) | RT2661_C); + } + + RT2661_EEPROM_CTL(sc, RT2661_S); + + /* read data Q15-Q0 */ + val = 0; + for (n = 15; n >= 0; n--) { + RT2661_EEPROM_CTL(sc, RT2661_S | RT2661_C); + tmp = RAL_READ(sc, RT2661_E2PROM_CSR); + val |= ((tmp & RT2661_Q) >> RT2661_SHIFT_Q) << n; + RT2661_EEPROM_CTL(sc, RT2661_S); + } + + RT2661_EEPROM_CTL(sc, 0); + + /* clear Chip Select and clock C */ + RT2661_EEPROM_CTL(sc, RT2661_S); + RT2661_EEPROM_CTL(sc, 0); + RT2661_EEPROM_CTL(sc, RT2661_C); + + return val; +} + +static void +rt2661_tx_intr(struct rt2661_softc *sc) +{ + struct ifnet *ifp = sc->sc_ifp; + struct rt2661_tx_ring *txq; + struct rt2661_tx_data *data; + struct rt2661_node *rn; + uint32_t val; + int qid, retrycnt; + + for (;;) { + struct ieee80211_node *ni; + struct mbuf *m; + + val = RAL_READ(sc, RT2661_STA_CSR4); + if (!(val & RT2661_TX_STAT_VALID)) + break; + + /* retrieve the queue in which this frame was sent */ + qid = RT2661_TX_QID(val); + txq = (qid <= 3) ? &sc->txq[qid] : &sc->mgtq; + + /* retrieve rate control algorithm context */ + data = &txq->data[txq->stat]; + m = data->m; + data->m = NULL; + ni = data->ni; + data->ni = NULL; + + /* if no frame has been sent, ignore */ + if (ni == NULL) + continue; + + rn = RT2661_NODE(ni); + + switch (RT2661_TX_RESULT(val)) { + case RT2661_TX_SUCCESS: + retrycnt = RT2661_TX_RETRYCNT(val); + + DPRINTFN(sc, 10, "data frame sent successfully after " + "%d retries\n", retrycnt); + if (data->rix != IEEE80211_FIXED_RATE_NONE) + ieee80211_amrr_tx_complete(&rn->amrr, + IEEE80211_AMRR_SUCCESS, retrycnt); + ifp->if_opackets++; + break; + + case RT2661_TX_RETRY_FAIL: + retrycnt = RT2661_TX_RETRYCNT(val); + + DPRINTFN(sc, 9, "%s\n", + "sending data frame failed (too much retries)"); + if (data->rix != IEEE80211_FIXED_RATE_NONE) + ieee80211_amrr_tx_complete(&rn->amrr, + IEEE80211_AMRR_FAILURE, retrycnt); + ifp->if_oerrors++; + break; + + default: + /* other failure */ + device_printf(sc->sc_dev, + "sending data frame failed 0x%08x\n", val); + ifp->if_oerrors++; + } + + DPRINTFN(sc, 15, "tx done q=%d idx=%u\n", qid, txq->stat); + + txq->queued--; + if (++txq->stat >= txq->count) /* faster than % count */ + txq->stat = 0; + + if (m->m_flags & M_TXCB) + ieee80211_process_callback(ni, m, + RT2661_TX_RESULT(val) != RT2661_TX_SUCCESS); + m_freem(m); + ieee80211_free_node(ni); + } + + sc->sc_tx_timer = 0; + ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; + + rt2661_start_locked(ifp); +} + +static void +rt2661_tx_dma_intr(struct rt2661_softc *sc, struct rt2661_tx_ring *txq) +{ + struct rt2661_tx_desc *desc; + struct rt2661_tx_data *data; + + bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_POSTREAD); + + for (;;) { + desc = &txq->desc[txq->next]; + data = &txq->data[txq->next]; + + if ((le32toh(desc->flags) & RT2661_TX_BUSY) || + !(le32toh(desc->flags) & RT2661_TX_VALID)) + break; + + bus_dmamap_sync(txq->data_dmat, data->map, + BUS_DMASYNC_POSTWRITE); + bus_dmamap_unload(txq->data_dmat, data->map); + + /* descriptor is no longer valid */ + desc->flags &= ~htole32(RT2661_TX_VALID); + + DPRINTFN(sc, 15, "tx dma done q=%p idx=%u\n", txq, txq->next); + + if (++txq->next >= txq->count) /* faster than % count */ + txq->next = 0; + } + + bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); +} + +static void +rt2661_rx_intr(struct rt2661_softc *sc) +{ + struct ifnet *ifp = sc->sc_ifp; + struct ieee80211com *ic = ifp->if_l2com; + struct rt2661_rx_desc *desc; + struct rt2661_rx_data *data; + bus_addr_t physaddr; + struct ieee80211_frame *wh; + struct ieee80211_node *ni; + struct mbuf *mnew, *m; + int error; + + bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, + BUS_DMASYNC_POSTREAD); + + for (;;) { + int8_t rssi, nf; + + desc = &sc->rxq.desc[sc->rxq.cur]; + data = &sc->rxq.data[sc->rxq.cur]; + + if (le32toh(desc->flags) & RT2661_RX_BUSY) + break; + + if ((le32toh(desc->flags) & RT2661_RX_PHY_ERROR) || + (le32toh(desc->flags) & RT2661_RX_CRC_ERROR)) { + /* + * This should not happen since we did not request + * to receive those frames when we filled TXRX_CSR0. + */ + DPRINTFN(sc, 5, "PHY or CRC error flags 0x%08x\n", + le32toh(desc->flags)); + ifp->if_ierrors++; + goto skip; + } + + if ((le32toh(desc->flags) & RT2661_RX_CIPHER_MASK) != 0) { + ifp->if_ierrors++; + goto skip; + } + + /* + * Try to allocate a new mbuf for this ring element and load it + * before processing the current mbuf. If the ring element + * cannot be loaded, drop the received packet and reuse the old + * mbuf. In the unlikely case that the old mbuf can't be + * reloaded either, explicitly panic. + */ + mnew = m_getcl(M_DONTWAIT, MT_DATA, M_PKTHDR); + if (mnew == NULL) { + ifp->if_ierrors++; + goto skip; + } + + bus_dmamap_sync(sc->rxq.data_dmat, data->map, + BUS_DMASYNC_POSTREAD); + bus_dmamap_unload(sc->rxq.data_dmat, data->map); + + error = bus_dmamap_load(sc->rxq.data_dmat, data->map, + mtod(mnew, void *), MCLBYTES, rt2661_dma_map_addr, + &physaddr, 0); + if (error != 0) { + m_freem(mnew); + + /* try to reload the old mbuf */ + error = bus_dmamap_load(sc->rxq.data_dmat, data->map, + mtod(data->m, void *), MCLBYTES, + rt2661_dma_map_addr, &physaddr, 0); + if (error != 0) { + /* very unlikely that it will fail... */ + panic("%s: could not load old rx mbuf", + device_get_name(sc->sc_dev)); + } + ifp->if_ierrors++; + goto skip; + } + + /* + * New mbuf successfully loaded, update Rx ring and continue + * processing. + */ + m = data->m; + data->m = mnew; + desc->physaddr = htole32(physaddr); + + /* finalize mbuf */ + m->m_pkthdr.rcvif = ifp; + m->m_pkthdr.len = m->m_len = + (le32toh(desc->flags) >> 16) & 0xfff; + + rssi = rt2661_get_rssi(sc, desc->rssi); + /* Error happened during RSSI conversion. */ + if (rssi < 0) + rssi = -30; /* XXX ignored by net80211 */ + nf = RT2661_NOISE_FLOOR; + + if (ieee80211_radiotap_active(ic)) { + struct rt2661_rx_radiotap_header *tap = &sc->sc_rxtap; + uint32_t tsf_lo, tsf_hi; + + /* get timestamp (low and high 32 bits) */ + tsf_hi = RAL_READ(sc, RT2661_TXRX_CSR13); + tsf_lo = RAL_READ(sc, RT2661_TXRX_CSR12); + + tap->wr_tsf = + htole64(((uint64_t)tsf_hi << 32) | tsf_lo); + tap->wr_flags = 0; + tap->wr_rate = ieee80211_plcp2rate(desc->rate, + (desc->flags & htole32(RT2661_RX_OFDM)) ? + IEEE80211_T_OFDM : IEEE80211_T_CCK); + tap->wr_antsignal = nf + rssi; + tap->wr_antnoise = nf; + } + sc->sc_flags |= RAL_INPUT_RUNNING; + RAL_UNLOCK(sc); + wh = mtod(m, struct ieee80211_frame *); + + /* send the frame to the 802.11 layer */ + ni = ieee80211_find_rxnode(ic, + (struct ieee80211_frame_min *)wh); + if (ni != NULL) { + (void) ieee80211_input(ni, m, rssi, nf); + ieee80211_free_node(ni); + } else + (void) ieee80211_input_all(ic, m, rssi, nf); + + RAL_LOCK(sc); + sc->sc_flags &= ~RAL_INPUT_RUNNING; + +skip: desc->flags |= htole32(RT2661_RX_BUSY); + + DPRINTFN(sc, 15, "rx intr idx=%u\n", sc->rxq.cur); + + sc->rxq.cur = (sc->rxq.cur + 1) % RT2661_RX_RING_COUNT; + } + + bus_dmamap_sync(sc->rxq.desc_dmat, sc->rxq.desc_map, + BUS_DMASYNC_PREWRITE); +} + +/* ARGSUSED */ +static void +rt2661_mcu_beacon_expire(struct rt2661_softc *sc) +{ + /* do nothing */ +} + +static void +rt2661_mcu_wakeup(struct rt2661_softc *sc) +{ + RAL_WRITE(sc, RT2661_MAC_CSR11, 5 << 16); + + RAL_WRITE(sc, RT2661_SOFT_RESET_CSR, 0x7); + RAL_WRITE(sc, RT2661_IO_CNTL_CSR, 0x18); + RAL_WRITE(sc, RT2661_PCI_USEC_CSR, 0x20); + + /* send wakeup command to MCU */ + rt2661_tx_cmd(sc, RT2661_MCU_CMD_WAKEUP, 0); +} + +static void +rt2661_mcu_cmd_intr(struct rt2661_softc *sc) +{ + RAL_READ(sc, RT2661_M2H_CMD_DONE_CSR); + RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); +} + +void +rt2661_intr(void *arg) +{ + struct rt2661_softc *sc = arg; + struct ifnet *ifp = sc->sc_ifp; + uint32_t r1, r2; + + RAL_LOCK(sc); + + /* disable MAC and MCU interrupts */ + RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffff7f); + RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); + + /* don't re-enable interrupts if we're shutting down */ + if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { + RAL_UNLOCK(sc); + return; + } + + r1 = RAL_READ(sc, RT2661_INT_SOURCE_CSR); + RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, r1); + + r2 = RAL_READ(sc, RT2661_MCU_INT_SOURCE_CSR); + RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, r2); + + if (r1 & RT2661_MGT_DONE) + rt2661_tx_dma_intr(sc, &sc->mgtq); + + if (r1 & RT2661_RX_DONE) + rt2661_rx_intr(sc); + + if (r1 & RT2661_TX0_DMA_DONE) + rt2661_tx_dma_intr(sc, &sc->txq[0]); + + if (r1 & RT2661_TX1_DMA_DONE) + rt2661_tx_dma_intr(sc, &sc->txq[1]); + + if (r1 & RT2661_TX2_DMA_DONE) + rt2661_tx_dma_intr(sc, &sc->txq[2]); + + if (r1 & RT2661_TX3_DMA_DONE) + rt2661_tx_dma_intr(sc, &sc->txq[3]); + + if (r1 & RT2661_TX_DONE) + rt2661_tx_intr(sc); + + if (r2 & RT2661_MCU_CMD_DONE) + rt2661_mcu_cmd_intr(sc); + + if (r2 & RT2661_MCU_BEACON_EXPIRE) + rt2661_mcu_beacon_expire(sc); + + if (r2 & RT2661_MCU_WAKEUP) + rt2661_mcu_wakeup(sc); + + /* re-enable MAC and MCU interrupts */ + RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); + RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); + + RAL_UNLOCK(sc); +} + +static uint8_t +rt2661_plcp_signal(int rate) +{ + switch (rate) { + /* OFDM rates (cf IEEE Std 802.11a-1999, pp. 14 Table 80) */ + case 12: return 0xb; + case 18: return 0xf; + case 24: return 0xa; + case 36: return 0xe; + case 48: return 0x9; + case 72: return 0xd; + case 96: return 0x8; + case 108: return 0xc; + + /* CCK rates (NB: not IEEE std, device-specific) */ + case 2: return 0x0; + case 4: return 0x1; + case 11: return 0x2; + case 22: return 0x3; + } + return 0xff; /* XXX unsupported/unknown rate */ +} + +static void +rt2661_setup_tx_desc(struct rt2661_softc *sc, struct rt2661_tx_desc *desc, + uint32_t flags, uint16_t xflags, int len, int rate, + const bus_dma_segment_t *segs, int nsegs, int ac) +{ + struct ifnet *ifp = sc->sc_ifp; + struct ieee80211com *ic = ifp->if_l2com; + uint16_t plcp_length; + int i, remainder; + + desc->flags = htole32(flags); + desc->flags |= htole32(len << 16); + desc->flags |= htole32(RT2661_TX_BUSY | RT2661_TX_VALID); + + desc->xflags = htole16(xflags); + desc->xflags |= htole16(nsegs << 13); + + desc->wme = htole16( + RT2661_QID(ac) | + RT2661_AIFSN(2) | + RT2661_LOGCWMIN(4) | + RT2661_LOGCWMAX(10)); + + /* + * Remember in which queue this frame was sent. This field is driver + * private data only. It will be made available by the NIC in STA_CSR4 + * on Tx interrupts. + */ + desc->qid = ac; + + /* setup PLCP fields */ + desc->plcp_signal = rt2661_plcp_signal(rate); + desc->plcp_service = 4; + + len += IEEE80211_CRC_LEN; + if (ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) { + desc->flags |= htole32(RT2661_TX_OFDM); + + plcp_length = len & 0xfff; + desc->plcp_length_hi = plcp_length >> 6; + desc->plcp_length_lo = plcp_length & 0x3f; + } else { + plcp_length = (16 * len + rate - 1) / rate; + if (rate == 22) { + remainder = (16 * len) % 22; + if (remainder != 0 && remainder < 7) + desc->plcp_service |= RT2661_PLCP_LENGEXT; + } + desc->plcp_length_hi = plcp_length >> 8; + desc->plcp_length_lo = plcp_length & 0xff; + + if (rate != 2 && (ic->ic_flags & IEEE80211_F_SHPREAMBLE)) + desc->plcp_signal |= 0x08; + } + + /* RT2x61 supports scatter with up to 5 segments */ + for (i = 0; i < nsegs; i++) { + desc->addr[i] = htole32(segs[i].ds_addr); + desc->len [i] = htole16(segs[i].ds_len); + } +} + +static int +rt2661_tx_mgt(struct rt2661_softc *sc, struct mbuf *m0, + struct ieee80211_node *ni) +{ + struct ieee80211vap *vap = ni->ni_vap; + struct ieee80211com *ic = ni->ni_ic; + struct rt2661_tx_desc *desc; + struct rt2661_tx_data *data; + struct ieee80211_frame *wh; + struct ieee80211_key *k; + bus_dma_segment_t segs[RT2661_MAX_SCATTER]; + uint16_t dur; + uint32_t flags = 0; /* XXX HWSEQ */ + int nsegs, rate, error; + + desc = &sc->mgtq.desc[sc->mgtq.cur]; + data = &sc->mgtq.data[sc->mgtq.cur]; + + rate = vap->iv_txparms[ieee80211_chan2mode(ic->ic_curchan)].mgmtrate; + + wh = mtod(m0, struct ieee80211_frame *); + + if (wh->i_fc[1] & IEEE80211_FC1_WEP) { + k = ieee80211_crypto_encap(ni, m0); + if (k == NULL) { + m_freem(m0); + return ENOBUFS; + } + } + + error = bus_dmamap_load_mbuf_sg(sc->mgtq.data_dmat, data->map, m0, + segs, &nsegs, 0); + if (error != 0) { + device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", + error); + m_freem(m0); + return error; + } + + if (ieee80211_radiotap_active_vap(vap)) { + struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; + + tap->wt_flags = 0; + tap->wt_rate = rate; + + ieee80211_radiotap_tx(vap, m0); + } + + data->m = m0; + data->ni = ni; + /* management frames are not taken into account for amrr */ + data->rix = IEEE80211_FIXED_RATE_NONE; + + wh = mtod(m0, struct ieee80211_frame *); + + if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { + flags |= RT2661_TX_NEED_ACK; + + dur = ieee80211_ack_duration(ic->ic_rt, + rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE); + *(uint16_t *)wh->i_dur = htole16(dur); + + /* tell hardware to add timestamp in probe responses */ + if ((wh->i_fc[0] & + (IEEE80211_FC0_TYPE_MASK | IEEE80211_FC0_SUBTYPE_MASK)) == + (IEEE80211_FC0_TYPE_MGT | IEEE80211_FC0_SUBTYPE_PROBE_RESP)) + flags |= RT2661_TX_TIMESTAMP; + } + + rt2661_setup_tx_desc(sc, desc, flags, 0 /* XXX HWSEQ */, + m0->m_pkthdr.len, rate, segs, nsegs, RT2661_QID_MGT); + + bus_dmamap_sync(sc->mgtq.data_dmat, data->map, BUS_DMASYNC_PREWRITE); + bus_dmamap_sync(sc->mgtq.desc_dmat, sc->mgtq.desc_map, + BUS_DMASYNC_PREWRITE); + + DPRINTFN(sc, 10, "sending mgt frame len=%u idx=%u rate=%u\n", + m0->m_pkthdr.len, sc->mgtq.cur, rate); + + /* kick mgt */ + sc->mgtq.queued++; + sc->mgtq.cur = (sc->mgtq.cur + 1) % RT2661_MGT_RING_COUNT; + RAL_WRITE(sc, RT2661_TX_CNTL_CSR, RT2661_KICK_MGT); + + return 0; +} + +static int +rt2661_sendprot(struct rt2661_softc *sc, int ac, + const struct mbuf *m, struct ieee80211_node *ni, int prot, int rate) +{ + struct ieee80211com *ic = ni->ni_ic; + struct rt2661_tx_ring *txq = &sc->txq[ac]; + const struct ieee80211_frame *wh; + struct rt2661_tx_desc *desc; + struct rt2661_tx_data *data; + struct mbuf *mprot; + int protrate, ackrate, pktlen, flags, isshort, error; + uint16_t dur; + bus_dma_segment_t segs[RT2661_MAX_SCATTER]; + int nsegs; + + KASSERT(prot == IEEE80211_PROT_RTSCTS || prot == IEEE80211_PROT_CTSONLY, + ("protection %d", prot)); + + wh = mtod(m, const struct ieee80211_frame *); + pktlen = m->m_pkthdr.len + IEEE80211_CRC_LEN; + + protrate = ieee80211_ctl_rate(ic->ic_rt, rate); + ackrate = ieee80211_ack_rate(ic->ic_rt, rate); + + isshort = (ic->ic_flags & IEEE80211_F_SHPREAMBLE) != 0; + dur = ieee80211_compute_duration(ic->ic_rt, pktlen, rate, isshort) + + ieee80211_ack_duration(ic->ic_rt, rate, isshort); + flags = RT2661_TX_MORE_FRAG; + if (prot == IEEE80211_PROT_RTSCTS) { + /* NB: CTS is the same size as an ACK */ + dur += ieee80211_ack_duration(ic->ic_rt, rate, isshort); + flags |= RT2661_TX_NEED_ACK; + mprot = ieee80211_alloc_rts(ic, wh->i_addr1, wh->i_addr2, dur); + } else { + mprot = ieee80211_alloc_cts(ic, ni->ni_vap->iv_myaddr, dur); + } + if (mprot == NULL) { + /* XXX stat + msg */ + return ENOBUFS; + } + + data = &txq->data[txq->cur]; + desc = &txq->desc[txq->cur]; + + error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, mprot, segs, + &nsegs, 0); + if (error != 0) { + device_printf(sc->sc_dev, + "could not map mbuf (error %d)\n", error); + m_freem(mprot); + return error; + } + + data->m = mprot; + data->ni = ieee80211_ref_node(ni); + /* ctl frames are not taken into account for amrr */ + data->rix = IEEE80211_FIXED_RATE_NONE; + + rt2661_setup_tx_desc(sc, desc, flags, 0, mprot->m_pkthdr.len, + protrate, segs, 1, ac); + + bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE); + bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); + + txq->queued++; + txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; + + return 0; +} + +static int +rt2661_tx_data(struct rt2661_softc *sc, struct mbuf *m0, + struct ieee80211_node *ni, int ac) +{ + struct ieee80211vap *vap = ni->ni_vap; + struct ifnet *ifp = sc->sc_ifp; + struct ieee80211com *ic = ifp->if_l2com; + struct rt2661_tx_ring *txq = &sc->txq[ac]; + struct rt2661_tx_desc *desc; + struct rt2661_tx_data *data; + struct ieee80211_frame *wh; + const struct ieee80211_txparam *tp; + struct ieee80211_key *k; + const struct chanAccParams *cap; + struct mbuf *mnew; + bus_dma_segment_t segs[RT2661_MAX_SCATTER]; + uint16_t dur; + uint32_t flags; + int error, nsegs, rate, noack = 0; + + wh = mtod(m0, struct ieee80211_frame *); + + tp = &vap->iv_txparms[ieee80211_chan2mode(ni->ni_chan)]; + if (IEEE80211_IS_MULTICAST(wh->i_addr1)) { + rate = tp->mcastrate; + } else if (m0->m_flags & M_EAPOL) { + rate = tp->mgmtrate; + } else if (tp->ucastrate != IEEE80211_FIXED_RATE_NONE) { + rate = tp->ucastrate; + } else { + (void) ieee80211_amrr_choose(ni, &RT2661_NODE(ni)->amrr); + rate = ni->ni_txrate; + } + rate &= IEEE80211_RATE_VAL; + + if (wh->i_fc[0] & IEEE80211_FC0_SUBTYPE_QOS) { + cap = &ic->ic_wme.wme_chanParams; + noack = cap->cap_wmeParams[ac].wmep_noackPolicy; + } + + if (wh->i_fc[1] & IEEE80211_FC1_WEP) { + k = ieee80211_crypto_encap(ni, m0); + if (k == NULL) { + m_freem(m0); + return ENOBUFS; + } + + /* packet header may have moved, reset our local pointer */ + wh = mtod(m0, struct ieee80211_frame *); + } + + flags = 0; + if (!IEEE80211_IS_MULTICAST(wh->i_addr1)) { + int prot = IEEE80211_PROT_NONE; + if (m0->m_pkthdr.len + IEEE80211_CRC_LEN > vap->iv_rtsthreshold) + prot = IEEE80211_PROT_RTSCTS; + else if ((ic->ic_flags & IEEE80211_F_USEPROT) && + ieee80211_rate2phytype(ic->ic_rt, rate) == IEEE80211_T_OFDM) + prot = ic->ic_protmode; + if (prot != IEEE80211_PROT_NONE) { + error = rt2661_sendprot(sc, ac, m0, ni, prot, rate); + if (error) { + m_freem(m0); + return error; + } + flags |= RT2661_TX_LONG_RETRY | RT2661_TX_IFS; + } + } + + data = &txq->data[txq->cur]; + desc = &txq->desc[txq->cur]; + + error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0, segs, + &nsegs, 0); + if (error != 0 && error != EFBIG) { + device_printf(sc->sc_dev, "could not map mbuf (error %d)\n", + error); + m_freem(m0); + return error; + } + if (error != 0) { + mnew = m_defrag(m0, M_DONTWAIT); + if (mnew == NULL) { + device_printf(sc->sc_dev, + "could not defragment mbuf\n"); + m_freem(m0); + return ENOBUFS; + } + m0 = mnew; + + error = bus_dmamap_load_mbuf_sg(txq->data_dmat, data->map, m0, + segs, &nsegs, 0); + if (error != 0) { + device_printf(sc->sc_dev, + "could not map mbuf (error %d)\n", error); + m_freem(m0); + return error; + } + + /* packet header have moved, reset our local pointer */ + wh = mtod(m0, struct ieee80211_frame *); + } + + if (ieee80211_radiotap_active_vap(vap)) { + struct rt2661_tx_radiotap_header *tap = &sc->sc_txtap; + + tap->wt_flags = 0; + tap->wt_rate = rate; + + ieee80211_radiotap_tx(vap, m0); + } + + data->m = m0; + data->ni = ni; + + /* remember link conditions for rate adaptation algorithm */ + if (tp->ucastrate == IEEE80211_FIXED_RATE_NONE) { + data->rix = ni->ni_txrate; + /* XXX probably need last rssi value and not avg */ + data->rssi = ic->ic_node_getrssi(ni); + } else + data->rix = IEEE80211_FIXED_RATE_NONE; + + if (!noack && !IEEE80211_IS_MULTICAST(wh->i_addr1)) { + flags |= RT2661_TX_NEED_ACK; + + dur = ieee80211_ack_duration(ic->ic_rt, + rate, ic->ic_flags & IEEE80211_F_SHPREAMBLE); + *(uint16_t *)wh->i_dur = htole16(dur); + } + + rt2661_setup_tx_desc(sc, desc, flags, 0, m0->m_pkthdr.len, rate, segs, + nsegs, ac); + + bus_dmamap_sync(txq->data_dmat, data->map, BUS_DMASYNC_PREWRITE); + bus_dmamap_sync(txq->desc_dmat, txq->desc_map, BUS_DMASYNC_PREWRITE); + + DPRINTFN(sc, 10, "sending data frame len=%u idx=%u rate=%u\n", + m0->m_pkthdr.len, txq->cur, rate); + + /* kick Tx */ + txq->queued++; + txq->cur = (txq->cur + 1) % RT2661_TX_RING_COUNT; + RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 1 << ac); + + return 0; +} + +static void +rt2661_start_locked(struct ifnet *ifp) +{ + struct rt2661_softc *sc = ifp->if_softc; + struct mbuf *m; + struct ieee80211_node *ni; + int ac; + + RAL_LOCK_ASSERT(sc); + + /* prevent management frames from being sent if we're not ready */ + if (!(ifp->if_drv_flags & IFF_DRV_RUNNING) || sc->sc_invalid) + return; + + for (;;) { + IFQ_DRV_DEQUEUE(&ifp->if_snd, m); + if (m == NULL) + break; + + ac = M_WME_GETAC(m); + if (sc->txq[ac].queued >= RT2661_TX_RING_COUNT - 1) { + /* there is no place left in this ring */ + IFQ_DRV_PREPEND(&ifp->if_snd, m); + ifp->if_drv_flags |= IFF_DRV_OACTIVE; + break; + } + ni = (struct ieee80211_node *) m->m_pkthdr.rcvif; + if (rt2661_tx_data(sc, m, ni, ac) != 0) { + ieee80211_free_node(ni); + ifp->if_oerrors++; + break; + } + + sc->sc_tx_timer = 5; + } +} + +static void +rt2661_start(struct ifnet *ifp) +{ + struct rt2661_softc *sc = ifp->if_softc; + + RAL_LOCK(sc); + rt2661_start_locked(ifp); + RAL_UNLOCK(sc); +} + +static int +rt2661_raw_xmit(struct ieee80211_node *ni, struct mbuf *m, + const struct ieee80211_bpf_params *params) +{ + struct ieee80211com *ic = ni->ni_ic; + struct ifnet *ifp = ic->ic_ifp; + struct rt2661_softc *sc = ifp->if_softc; + + RAL_LOCK(sc); + + /* prevent management frames from being sent if we're not ready */ + if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) { + RAL_UNLOCK(sc); + m_freem(m); + ieee80211_free_node(ni); + return ENETDOWN; + } + if (sc->mgtq.queued >= RT2661_MGT_RING_COUNT) { + ifp->if_drv_flags |= IFF_DRV_OACTIVE; + RAL_UNLOCK(sc); + m_freem(m); + ieee80211_free_node(ni); + return ENOBUFS; /* XXX */ + } + + ifp->if_opackets++; + + /* + * Legacy path; interpret frame contents to decide + * precisely how to send the frame. + * XXX raw path + */ + if (rt2661_tx_mgt(sc, m, ni) != 0) + goto bad; + sc->sc_tx_timer = 5; + + RAL_UNLOCK(sc); + + return 0; +bad: + ifp->if_oerrors++; + ieee80211_free_node(ni); + RAL_UNLOCK(sc); + return EIO; /* XXX */ +} + +static void +rt2661_watchdog(void *arg) +{ + struct rt2661_softc *sc = (struct rt2661_softc *)arg; + struct ifnet *ifp = sc->sc_ifp; + + RAL_LOCK_ASSERT(sc); + + KASSERT(ifp->if_drv_flags & IFF_DRV_RUNNING, ("not running")); + + if (sc->sc_invalid) /* card ejected */ + return; + + if (sc->sc_tx_timer > 0 && --sc->sc_tx_timer == 0) { + if_printf(ifp, "device timeout\n"); + rt2661_init_locked(sc); + ifp->if_oerrors++; + /* NB: callout is reset in rt2661_init() */ + return; + } + callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog, sc); +} + +static int +rt2661_ioctl(struct ifnet *ifp, u_long cmd, caddr_t data) +{ + struct rt2661_softc *sc = ifp->if_softc; + struct ieee80211com *ic = ifp->if_l2com; + struct ifreq *ifr = (struct ifreq *) data; + int error = 0, startall = 0; + + switch (cmd) { + case SIOCSIFFLAGS: + RAL_LOCK(sc); + if (ifp->if_flags & IFF_UP) { + if ((ifp->if_drv_flags & IFF_DRV_RUNNING) == 0) { + rt2661_init_locked(sc); + startall = 1; + } else + rt2661_update_promisc(ifp); + } else { + if (ifp->if_drv_flags & IFF_DRV_RUNNING) + rt2661_stop_locked(sc); + } + RAL_UNLOCK(sc); + if (startall) + ieee80211_start_all(ic); + break; + case SIOCGIFMEDIA: + error = ifmedia_ioctl(ifp, ifr, &ic->ic_media, cmd); + break; + case SIOCGIFADDR: + error = ether_ioctl(ifp, cmd, data); + break; + default: + error = EINVAL; + break; + } + return error; +} + +static void +rt2661_bbp_write(struct rt2661_softc *sc, uint8_t reg, uint8_t val) +{ + uint32_t tmp; + int ntries; + + for (ntries = 0; ntries < 100; ntries++) { + if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) + break; + DELAY(1); + } + if (ntries == 100) { + device_printf(sc->sc_dev, "could not write to BBP\n"); + return; + } + + tmp = RT2661_BBP_BUSY | (reg & 0x7f) << 8 | val; + RAL_WRITE(sc, RT2661_PHY_CSR3, tmp); + + DPRINTFN(sc, 15, "BBP R%u <- 0x%02x\n", reg, val); +} + +static uint8_t +rt2661_bbp_read(struct rt2661_softc *sc, uint8_t reg) +{ + uint32_t val; + int ntries; + + for (ntries = 0; ntries < 100; ntries++) { + if (!(RAL_READ(sc, RT2661_PHY_CSR3) & RT2661_BBP_BUSY)) + break; + DELAY(1); + } + if (ntries == 100) { + device_printf(sc->sc_dev, "could not read from BBP\n"); + return 0; + } + + val = RT2661_BBP_BUSY | RT2661_BBP_READ | reg << 8; + RAL_WRITE(sc, RT2661_PHY_CSR3, val); + + for (ntries = 0; ntries < 100; ntries++) { + val = RAL_READ(sc, RT2661_PHY_CSR3); + if (!(val & RT2661_BBP_BUSY)) + return val & 0xff; + DELAY(1); + } + + device_printf(sc->sc_dev, "could not read from BBP\n"); + return 0; +} + +static void +rt2661_rf_write(struct rt2661_softc *sc, uint8_t reg, uint32_t val) +{ + uint32_t tmp; + int ntries; + + for (ntries = 0; ntries < 100; ntries++) { + if (!(RAL_READ(sc, RT2661_PHY_CSR4) & RT2661_RF_BUSY)) + break; + DELAY(1); + } + if (ntries == 100) { + device_printf(sc->sc_dev, "could not write to RF\n"); + return; + } + + tmp = RT2661_RF_BUSY | RT2661_RF_21BIT | (val & 0x1fffff) << 2 | + (reg & 3); + RAL_WRITE(sc, RT2661_PHY_CSR4, tmp); + + /* remember last written value in sc */ + sc->rf_regs[reg] = val; + + DPRINTFN(sc, 15, "RF R[%u] <- 0x%05x\n", reg & 3, val & 0x1fffff); +} + +static int +rt2661_tx_cmd(struct rt2661_softc *sc, uint8_t cmd, uint16_t arg) +{ + if (RAL_READ(sc, RT2661_H2M_MAILBOX_CSR) & RT2661_H2M_BUSY) + return EIO; /* there is already a command pending */ + + RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, + RT2661_H2M_BUSY | RT2661_TOKEN_NO_INTR << 16 | arg); + + RAL_WRITE(sc, RT2661_HOST_CMD_CSR, RT2661_KICK_CMD | cmd); + + return 0; +} + +static void +rt2661_select_antenna(struct rt2661_softc *sc) +{ + uint8_t bbp4, bbp77; + uint32_t tmp; + + bbp4 = rt2661_bbp_read(sc, 4); + bbp77 = rt2661_bbp_read(sc, 77); + + /* TBD */ + + /* make sure Rx is disabled before switching antenna */ + tmp = RAL_READ(sc, RT2661_TXRX_CSR0); + RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); + + rt2661_bbp_write(sc, 4, bbp4); + rt2661_bbp_write(sc, 77, bbp77); + + /* restore Rx filter */ + RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); +} + +/* + * Enable multi-rate retries for frames sent at OFDM rates. + * In 802.11b/g mode, allow fallback to CCK rates. + */ +static void +rt2661_enable_mrr(struct rt2661_softc *sc) +{ + struct ifnet *ifp = sc->sc_ifp; + struct ieee80211com *ic = ifp->if_l2com; + uint32_t tmp; + + tmp = RAL_READ(sc, RT2661_TXRX_CSR4); + + tmp &= ~RT2661_MRR_CCK_FALLBACK; + if (!IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan)) + tmp |= RT2661_MRR_CCK_FALLBACK; + tmp |= RT2661_MRR_ENABLED; + + RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); +} + +static void +rt2661_set_txpreamble(struct rt2661_softc *sc) +{ + struct ifnet *ifp = sc->sc_ifp; + struct ieee80211com *ic = ifp->if_l2com; + uint32_t tmp; + + tmp = RAL_READ(sc, RT2661_TXRX_CSR4); + + tmp &= ~RT2661_SHORT_PREAMBLE; + if (ic->ic_flags & IEEE80211_F_SHPREAMBLE) + tmp |= RT2661_SHORT_PREAMBLE; + + RAL_WRITE(sc, RT2661_TXRX_CSR4, tmp); +} + +static void +rt2661_set_basicrates(struct rt2661_softc *sc, + const struct ieee80211_rateset *rs) +{ +#define RV(r) ((r) & IEEE80211_RATE_VAL) + struct ifnet *ifp = sc->sc_ifp; + struct ieee80211com *ic = ifp->if_l2com; + uint32_t mask = 0; + uint8_t rate; + int i, j; + + for (i = 0; i < rs->rs_nrates; i++) { + rate = rs->rs_rates[i]; + + if (!(rate & IEEE80211_RATE_BASIC)) + continue; + + /* + * Find h/w rate index. We know it exists because the rate + * set has already been negotiated. + */ + for (j = 0; ic->ic_sup_rates[IEEE80211_MODE_11G].rs_rates[j] != RV(rate); j++); + + mask |= 1 << j; + } + + RAL_WRITE(sc, RT2661_TXRX_CSR5, mask); + + DPRINTF(sc, "Setting basic rate mask to 0x%x\n", mask); +#undef RV +} + +/* + * Reprogram MAC/BBP to switch to a new band. Values taken from the reference + * driver. + */ +static void +rt2661_select_band(struct rt2661_softc *sc, struct ieee80211_channel *c) +{ + uint8_t bbp17, bbp35, bbp96, bbp97, bbp98, bbp104; + uint32_t tmp; + + /* update all BBP registers that depend on the band */ + bbp17 = 0x20; bbp96 = 0x48; bbp104 = 0x2c; + bbp35 = 0x50; bbp97 = 0x48; bbp98 = 0x48; + if (IEEE80211_IS_CHAN_5GHZ(c)) { + bbp17 += 0x08; bbp96 += 0x10; bbp104 += 0x0c; + bbp35 += 0x10; bbp97 += 0x10; bbp98 += 0x10; + } + if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || + (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { + bbp17 += 0x10; bbp96 += 0x10; bbp104 += 0x10; + } + + rt2661_bbp_write(sc, 17, bbp17); + rt2661_bbp_write(sc, 96, bbp96); + rt2661_bbp_write(sc, 104, bbp104); + + if ((IEEE80211_IS_CHAN_2GHZ(c) && sc->ext_2ghz_lna) || + (IEEE80211_IS_CHAN_5GHZ(c) && sc->ext_5ghz_lna)) { + rt2661_bbp_write(sc, 75, 0x80); + rt2661_bbp_write(sc, 86, 0x80); + rt2661_bbp_write(sc, 88, 0x80); + } + + rt2661_bbp_write(sc, 35, bbp35); + rt2661_bbp_write(sc, 97, bbp97); + rt2661_bbp_write(sc, 98, bbp98); + + tmp = RAL_READ(sc, RT2661_PHY_CSR0); + tmp &= ~(RT2661_PA_PE_2GHZ | RT2661_PA_PE_5GHZ); + if (IEEE80211_IS_CHAN_2GHZ(c)) + tmp |= RT2661_PA_PE_2GHZ; + else + tmp |= RT2661_PA_PE_5GHZ; + RAL_WRITE(sc, RT2661_PHY_CSR0, tmp); +} + +static void +rt2661_set_chan(struct rt2661_softc *sc, struct ieee80211_channel *c) +{ + struct ifnet *ifp = sc->sc_ifp; + struct ieee80211com *ic = ifp->if_l2com; + const struct rfprog *rfprog; + uint8_t bbp3, bbp94 = RT2661_BBPR94_DEFAULT; + int8_t power; + u_int i, chan; + + chan = ieee80211_chan2ieee(ic, c); + KASSERT(chan != 0 && chan != IEEE80211_CHAN_ANY, ("chan 0x%x", chan)); + + /* select the appropriate RF settings based on what EEPROM says */ + rfprog = (sc->rfprog == 0) ? rt2661_rf5225_1 : rt2661_rf5225_2; + + /* find the settings for this channel (we know it exists) */ + for (i = 0; rfprog[i].chan != chan; i++); + + power = sc->txpow[i]; + if (power < 0) { + bbp94 += power; + power = 0; + } else if (power > 31) { + bbp94 += power - 31; + power = 31; + } + + /* + * If we are switching from the 2GHz band to the 5GHz band or + * vice-versa, BBP registers need to be reprogrammed. + */ + if (c->ic_flags != sc->sc_curchan->ic_flags) { + rt2661_select_band(sc, c); + rt2661_select_antenna(sc); + } + sc->sc_curchan = c; + + rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); + rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); + rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); + rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); + + DELAY(200); + + rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); + rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); + rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7 | 1); + rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); + + DELAY(200); + + rt2661_rf_write(sc, RAL_RF1, rfprog[i].r1); + rt2661_rf_write(sc, RAL_RF2, rfprog[i].r2); + rt2661_rf_write(sc, RAL_RF3, rfprog[i].r3 | power << 7); + rt2661_rf_write(sc, RAL_RF4, rfprog[i].r4 | sc->rffreq << 10); + + /* enable smart mode for MIMO-capable RFs */ + bbp3 = rt2661_bbp_read(sc, 3); + + bbp3 &= ~RT2661_SMART_MODE; + if (sc->rf_rev == RT2661_RF_5325 || sc->rf_rev == RT2661_RF_2529) + bbp3 |= RT2661_SMART_MODE; + + rt2661_bbp_write(sc, 3, bbp3); + + if (bbp94 != RT2661_BBPR94_DEFAULT) + rt2661_bbp_write(sc, 94, bbp94); + + /* 5GHz radio needs a 1ms delay here */ + if (IEEE80211_IS_CHAN_5GHZ(c)) + DELAY(1000); +} + +static void +rt2661_set_bssid(struct rt2661_softc *sc, const uint8_t *bssid) +{ + uint32_t tmp; + + tmp = bssid[0] | bssid[1] << 8 | bssid[2] << 16 | bssid[3] << 24; + RAL_WRITE(sc, RT2661_MAC_CSR4, tmp); + + tmp = bssid[4] | bssid[5] << 8 | RT2661_ONE_BSSID << 16; + RAL_WRITE(sc, RT2661_MAC_CSR5, tmp); +} + +static void +rt2661_set_macaddr(struct rt2661_softc *sc, const uint8_t *addr) +{ + uint32_t tmp; + + tmp = addr[0] | addr[1] << 8 | addr[2] << 16 | addr[3] << 24; + RAL_WRITE(sc, RT2661_MAC_CSR2, tmp); + + tmp = addr[4] | addr[5] << 8; + RAL_WRITE(sc, RT2661_MAC_CSR3, tmp); +} + +static void +rt2661_update_promisc(struct ifnet *ifp) +{ + struct rt2661_softc *sc = ifp->if_softc; + uint32_t tmp; + + tmp = RAL_READ(sc, RT2661_TXRX_CSR0); + + tmp &= ~RT2661_DROP_NOT_TO_ME; + if (!(ifp->if_flags & IFF_PROMISC)) + tmp |= RT2661_DROP_NOT_TO_ME; + + RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); + + DPRINTF(sc, "%s promiscuous mode\n", (ifp->if_flags & IFF_PROMISC) ? + "entering" : "leaving"); +} + +/* + * Update QoS (802.11e) settings for each h/w Tx ring. + */ +static int +rt2661_wme_update(struct ieee80211com *ic) +{ + struct rt2661_softc *sc = ic->ic_ifp->if_softc; + const struct wmeParams *wmep; + + wmep = ic->ic_wme.wme_chanParams.cap_wmeParams; + + /* XXX: not sure about shifts. */ + /* XXX: the reference driver plays with AC_VI settings too. */ + + /* update TxOp */ + RAL_WRITE(sc, RT2661_AC_TXOP_CSR0, + wmep[WME_AC_BE].wmep_txopLimit << 16 | + wmep[WME_AC_BK].wmep_txopLimit); + RAL_WRITE(sc, RT2661_AC_TXOP_CSR1, + wmep[WME_AC_VI].wmep_txopLimit << 16 | + wmep[WME_AC_VO].wmep_txopLimit); + + /* update CWmin */ + RAL_WRITE(sc, RT2661_CWMIN_CSR, + wmep[WME_AC_BE].wmep_logcwmin << 12 | + wmep[WME_AC_BK].wmep_logcwmin << 8 | + wmep[WME_AC_VI].wmep_logcwmin << 4 | + wmep[WME_AC_VO].wmep_logcwmin); + + /* update CWmax */ + RAL_WRITE(sc, RT2661_CWMAX_CSR, + wmep[WME_AC_BE].wmep_logcwmax << 12 | + wmep[WME_AC_BK].wmep_logcwmax << 8 | + wmep[WME_AC_VI].wmep_logcwmax << 4 | + wmep[WME_AC_VO].wmep_logcwmax); + + /* update Aifsn */ + RAL_WRITE(sc, RT2661_AIFSN_CSR, + wmep[WME_AC_BE].wmep_aifsn << 12 | + wmep[WME_AC_BK].wmep_aifsn << 8 | + wmep[WME_AC_VI].wmep_aifsn << 4 | + wmep[WME_AC_VO].wmep_aifsn); + + return 0; +} + +static void +rt2661_update_slot(struct ifnet *ifp) +{ + struct rt2661_softc *sc = ifp->if_softc; + struct ieee80211com *ic = ifp->if_l2com; + uint8_t slottime; + uint32_t tmp; + + slottime = (ic->ic_flags & IEEE80211_F_SHSLOT) ? 9 : 20; + + tmp = RAL_READ(sc, RT2661_MAC_CSR9); + tmp = (tmp & ~0xff) | slottime; + RAL_WRITE(sc, RT2661_MAC_CSR9, tmp); +} + +static const char * +rt2661_get_rf(int rev) +{ + switch (rev) { + case RT2661_RF_5225: return "RT5225"; + case RT2661_RF_5325: return "RT5325 (MIMO XR)"; + case RT2661_RF_2527: return "RT2527"; + case RT2661_RF_2529: return "RT2529 (MIMO XR)"; + default: return "unknown"; + } +} + +static void +rt2661_read_eeprom(struct rt2661_softc *sc, uint8_t macaddr[IEEE80211_ADDR_LEN]) +{ + uint16_t val; + int i; + + /* read MAC address */ + val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC01); + macaddr[0] = val & 0xff; + macaddr[1] = val >> 8; + + val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC23); + macaddr[2] = val & 0xff; + macaddr[3] = val >> 8; + + val = rt2661_eeprom_read(sc, RT2661_EEPROM_MAC45); + macaddr[4] = val & 0xff; + macaddr[5] = val >> 8; + + val = rt2661_eeprom_read(sc, RT2661_EEPROM_ANTENNA); + /* XXX: test if different from 0xffff? */ + sc->rf_rev = (val >> 11) & 0x1f; + sc->hw_radio = (val >> 10) & 0x1; + sc->rx_ant = (val >> 4) & 0x3; + sc->tx_ant = (val >> 2) & 0x3; + sc->nb_ant = val & 0x3; + + DPRINTF(sc, "RF revision=%d\n", sc->rf_rev); + + val = rt2661_eeprom_read(sc, RT2661_EEPROM_CONFIG2); + sc->ext_5ghz_lna = (val >> 6) & 0x1; + sc->ext_2ghz_lna = (val >> 4) & 0x1; + + DPRINTF(sc, "External 2GHz LNA=%d\nExternal 5GHz LNA=%d\n", + sc->ext_2ghz_lna, sc->ext_5ghz_lna); + + val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_2GHZ_OFFSET); + if ((val & 0xff) != 0xff) + sc->rssi_2ghz_corr = (int8_t)(val & 0xff); /* signed */ + + /* Only [-10, 10] is valid */ + if (sc->rssi_2ghz_corr < -10 || sc->rssi_2ghz_corr > 10) + sc->rssi_2ghz_corr = 0; + + val = rt2661_eeprom_read(sc, RT2661_EEPROM_RSSI_5GHZ_OFFSET); + if ((val & 0xff) != 0xff) + sc->rssi_5ghz_corr = (int8_t)(val & 0xff); /* signed */ + + /* Only [-10, 10] is valid */ + if (sc->rssi_5ghz_corr < -10 || sc->rssi_5ghz_corr > 10) + sc->rssi_5ghz_corr = 0; + + /* adjust RSSI correction for external low-noise amplifier */ + if (sc->ext_2ghz_lna) + sc->rssi_2ghz_corr -= 14; + if (sc->ext_5ghz_lna) + sc->rssi_5ghz_corr -= 14; + + DPRINTF(sc, "RSSI 2GHz corr=%d\nRSSI 5GHz corr=%d\n", + sc->rssi_2ghz_corr, sc->rssi_5ghz_corr); + + val = rt2661_eeprom_read(sc, RT2661_EEPROM_FREQ_OFFSET); + if ((val >> 8) != 0xff) + sc->rfprog = (val >> 8) & 0x3; + if ((val & 0xff) != 0xff) + sc->rffreq = val & 0xff; + + DPRINTF(sc, "RF prog=%d\nRF freq=%d\n", sc->rfprog, sc->rffreq); + + /* read Tx power for all a/b/g channels */ + for (i = 0; i < 19; i++) { + val = rt2661_eeprom_read(sc, RT2661_EEPROM_TXPOWER + i); + sc->txpow[i * 2] = (int8_t)(val >> 8); /* signed */ + DPRINTF(sc, "Channel=%d Tx power=%d\n", + rt2661_rf5225_1[i * 2].chan, sc->txpow[i * 2]); + sc->txpow[i * 2 + 1] = (int8_t)(val & 0xff); /* signed */ + DPRINTF(sc, "Channel=%d Tx power=%d\n", + rt2661_rf5225_1[i * 2 + 1].chan, sc->txpow[i * 2 + 1]); + } + + /* read vendor-specific BBP values */ + for (i = 0; i < 16; i++) { + val = rt2661_eeprom_read(sc, RT2661_EEPROM_BBP_BASE + i); + if (val == 0 || val == 0xffff) + continue; /* skip invalid entries */ + sc->bbp_prom[i].reg = val >> 8; + sc->bbp_prom[i].val = val & 0xff; + DPRINTF(sc, "BBP R%d=%02x\n", sc->bbp_prom[i].reg, + sc->bbp_prom[i].val); + } +} + +static int +rt2661_bbp_init(struct rt2661_softc *sc) +{ +#define N(a) (sizeof (a) / sizeof ((a)[0])) + int i, ntries; + uint8_t val; + + /* wait for BBP to be ready */ + for (ntries = 0; ntries < 100; ntries++) { + val = rt2661_bbp_read(sc, 0); + if (val != 0 && val != 0xff) + break; + DELAY(100); + } + if (ntries == 100) { + device_printf(sc->sc_dev, "timeout waiting for BBP\n"); + return EIO; + } + + /* initialize BBP registers to default values */ + for (i = 0; i < N(rt2661_def_bbp); i++) { + rt2661_bbp_write(sc, rt2661_def_bbp[i].reg, + rt2661_def_bbp[i].val); + } + + /* write vendor-specific BBP values (from EEPROM) */ + for (i = 0; i < 16; i++) { + if (sc->bbp_prom[i].reg == 0) + continue; + rt2661_bbp_write(sc, sc->bbp_prom[i].reg, sc->bbp_prom[i].val); + } + + return 0; +#undef N +} + +static void +rt2661_init_locked(struct rt2661_softc *sc) +{ +#define N(a) (sizeof (a) / sizeof ((a)[0])) + struct ifnet *ifp = sc->sc_ifp; + struct ieee80211com *ic = ifp->if_l2com; + uint32_t tmp, sta[3]; + int i, error, ntries; + + RAL_LOCK_ASSERT(sc); + + if ((sc->sc_flags & RAL_FW_LOADED) == 0) { + error = rt2661_load_microcode(sc); + if (error != 0) { + if_printf(ifp, + "%s: could not load 8051 microcode, error %d\n", + __func__, error); + return; + } + sc->sc_flags |= RAL_FW_LOADED; + } + + rt2661_stop_locked(sc); + + /* initialize Tx rings */ + RAL_WRITE(sc, RT2661_AC1_BASE_CSR, sc->txq[1].physaddr); + RAL_WRITE(sc, RT2661_AC0_BASE_CSR, sc->txq[0].physaddr); + RAL_WRITE(sc, RT2661_AC2_BASE_CSR, sc->txq[2].physaddr); + RAL_WRITE(sc, RT2661_AC3_BASE_CSR, sc->txq[3].physaddr); + + /* initialize Mgt ring */ + RAL_WRITE(sc, RT2661_MGT_BASE_CSR, sc->mgtq.physaddr); + + /* initialize Rx ring */ + RAL_WRITE(sc, RT2661_RX_BASE_CSR, sc->rxq.physaddr); + + /* initialize Tx rings sizes */ + RAL_WRITE(sc, RT2661_TX_RING_CSR0, + RT2661_TX_RING_COUNT << 24 | + RT2661_TX_RING_COUNT << 16 | + RT2661_TX_RING_COUNT << 8 | + RT2661_TX_RING_COUNT); + + RAL_WRITE(sc, RT2661_TX_RING_CSR1, + RT2661_TX_DESC_WSIZE << 16 | + RT2661_TX_RING_COUNT << 8 | /* XXX: HCCA ring unused */ + RT2661_MGT_RING_COUNT); + + /* initialize Rx rings */ + RAL_WRITE(sc, RT2661_RX_RING_CSR, + RT2661_RX_DESC_BACK << 16 | + RT2661_RX_DESC_WSIZE << 8 | + RT2661_RX_RING_COUNT); + + /* XXX: some magic here */ + RAL_WRITE(sc, RT2661_TX_DMA_DST_CSR, 0xaa); + + /* load base addresses of all 5 Tx rings (4 data + 1 mgt) */ + RAL_WRITE(sc, RT2661_LOAD_TX_RING_CSR, 0x1f); + + /* load base address of Rx ring */ + RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 2); + + /* initialize MAC registers to default values */ + for (i = 0; i < N(rt2661_def_mac); i++) + RAL_WRITE(sc, rt2661_def_mac[i].reg, rt2661_def_mac[i].val); + + rt2661_set_macaddr(sc, IF_LLADDR(ifp)); + + /* set host ready */ + RAL_WRITE(sc, RT2661_MAC_CSR1, 3); + RAL_WRITE(sc, RT2661_MAC_CSR1, 0); + + /* wait for BBP/RF to wakeup */ + for (ntries = 0; ntries < 1000; ntries++) { + if (RAL_READ(sc, RT2661_MAC_CSR12) & 8) + break; + DELAY(1000); + } + if (ntries == 1000) { + printf("timeout waiting for BBP/RF to wakeup\n"); + rt2661_stop_locked(sc); + return; + } + + if (rt2661_bbp_init(sc) != 0) { + rt2661_stop_locked(sc); + return; + } + + /* select default channel */ + sc->sc_curchan = ic->ic_curchan; + rt2661_select_band(sc, sc->sc_curchan); + rt2661_select_antenna(sc); + rt2661_set_chan(sc, sc->sc_curchan); + + /* update Rx filter */ + tmp = RAL_READ(sc, RT2661_TXRX_CSR0) & 0xffff; + + tmp |= RT2661_DROP_PHY_ERROR | RT2661_DROP_CRC_ERROR; + if (ic->ic_opmode != IEEE80211_M_MONITOR) { + tmp |= RT2661_DROP_CTL | RT2661_DROP_VER_ERROR | + RT2661_DROP_ACKCTS; + if (ic->ic_opmode != IEEE80211_M_HOSTAP && + ic->ic_opmode != IEEE80211_M_MBSS) + tmp |= RT2661_DROP_TODS; + if (!(ifp->if_flags & IFF_PROMISC)) + tmp |= RT2661_DROP_NOT_TO_ME; + } + + RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); + + /* clear STA registers */ + RAL_READ_REGION_4(sc, RT2661_STA_CSR0, sta, N(sta)); + + /* initialize ASIC */ + RAL_WRITE(sc, RT2661_MAC_CSR1, 4); + + /* clear any pending interrupt */ + RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); + + /* enable interrupts */ + RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0x0000ff10); + RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0); + + /* kick Rx */ + RAL_WRITE(sc, RT2661_RX_CNTL_CSR, 1); + + ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; + ifp->if_drv_flags |= IFF_DRV_RUNNING; + + callout_reset(&sc->watchdog_ch, hz, rt2661_watchdog, sc); +#undef N +} + +static void +rt2661_init(void *priv) +{ + struct rt2661_softc *sc = priv; + struct ifnet *ifp = sc->sc_ifp; + struct ieee80211com *ic = ifp->if_l2com; + + RAL_LOCK(sc); + rt2661_init_locked(sc); + RAL_UNLOCK(sc); + + if (ifp->if_drv_flags & IFF_DRV_RUNNING) + ieee80211_start_all(ic); /* start all vap's */ +} + +void +rt2661_stop_locked(struct rt2661_softc *sc) +{ + struct ifnet *ifp = sc->sc_ifp; + uint32_t tmp; + volatile int *flags = &sc->sc_flags; + + while (*flags & RAL_INPUT_RUNNING) + msleep(sc, &sc->sc_mtx, 0, "ralrunning", hz/10); + + callout_stop(&sc->watchdog_ch); + sc->sc_tx_timer = 0; + + if (ifp->if_drv_flags & IFF_DRV_RUNNING) { + ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); + + /* abort Tx (for all 5 Tx rings) */ + RAL_WRITE(sc, RT2661_TX_CNTL_CSR, 0x1f << 16); + + /* disable Rx (value remains after reset!) */ + tmp = RAL_READ(sc, RT2661_TXRX_CSR0); + RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); + + /* reset ASIC */ + RAL_WRITE(sc, RT2661_MAC_CSR1, 3); + RAL_WRITE(sc, RT2661_MAC_CSR1, 0); + + /* disable interrupts */ + RAL_WRITE(sc, RT2661_INT_MASK_CSR, 0xffffffff); + RAL_WRITE(sc, RT2661_MCU_INT_MASK_CSR, 0xffffffff); + + /* clear any pending interrupt */ + RAL_WRITE(sc, RT2661_INT_SOURCE_CSR, 0xffffffff); + RAL_WRITE(sc, RT2661_MCU_INT_SOURCE_CSR, 0xffffffff); + + /* reset Tx and Rx rings */ + rt2661_reset_tx_ring(sc, &sc->txq[0]); + rt2661_reset_tx_ring(sc, &sc->txq[1]); + rt2661_reset_tx_ring(sc, &sc->txq[2]); + rt2661_reset_tx_ring(sc, &sc->txq[3]); + rt2661_reset_tx_ring(sc, &sc->mgtq); + rt2661_reset_rx_ring(sc, &sc->rxq); + } +} + +void +rt2661_stop(void *priv) +{ + struct rt2661_softc *sc = priv; + + RAL_LOCK(sc); + rt2661_stop_locked(sc); + RAL_UNLOCK(sc); +} + +static int +rt2661_load_microcode(struct rt2661_softc *sc) +{ + struct ifnet *ifp = sc->sc_ifp; + const struct firmware *fp; + const char *imagename; + int ntries, error; + + RAL_LOCK_ASSERT(sc); + + switch (sc->sc_id) { + case 0x0301: imagename = "rt2561sfw"; break; + case 0x0302: imagename = "rt2561fw"; break; + case 0x0401: imagename = "rt2661fw"; break; + default: + if_printf(ifp, "%s: unexpected pci device id 0x%x, " + "don't know how to retrieve firmware\n", + __func__, sc->sc_id); + return EINVAL; + } + RAL_UNLOCK(sc); + fp = firmware_get(imagename); + RAL_LOCK(sc); + if (fp == NULL) { + if_printf(ifp, "%s: unable to retrieve firmware image %s\n", + __func__, imagename); + return EINVAL; + } + + /* + * Load 8051 microcode into NIC. + */ + /* reset 8051 */ + RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); + + /* cancel any pending Host to MCU command */ + RAL_WRITE(sc, RT2661_H2M_MAILBOX_CSR, 0); + RAL_WRITE(sc, RT2661_M2H_CMD_DONE_CSR, 0xffffffff); + RAL_WRITE(sc, RT2661_HOST_CMD_CSR, 0); + + /* write 8051's microcode */ + RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET | RT2661_MCU_SEL); + RAL_WRITE_REGION_1(sc, RT2661_MCU_CODE_BASE, fp->data, fp->datasize); + RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, RT2661_MCU_RESET); + + /* kick 8051's ass */ + RAL_WRITE(sc, RT2661_MCU_CNTL_CSR, 0); + + /* wait for 8051 to initialize */ + for (ntries = 0; ntries < 500; ntries++) { + if (RAL_READ(sc, RT2661_MCU_CNTL_CSR) & RT2661_MCU_READY) + break; + DELAY(100); + } + if (ntries == 500) { + if_printf(ifp, "%s: timeout waiting for MCU to initialize\n", + __func__); + error = EIO; + } else + error = 0; + + firmware_put(fp, FIRMWARE_UNLOAD); + return error; +} + +#ifdef notyet +/* + * Dynamically tune Rx sensitivity (BBP register 17) based on average RSSI and + * false CCA count. This function is called periodically (every seconds) when + * in the RUN state. Values taken from the reference driver. + */ +static void +rt2661_rx_tune(struct rt2661_softc *sc) +{ + uint8_t bbp17; + uint16_t cca; + int lo, hi, dbm; + + /* + * Tuning range depends on operating band and on the presence of an + * external low-noise amplifier. + */ + lo = 0x20; + if (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan)) + lo += 0x08; + if ((IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan) && sc->ext_2ghz_lna) || + (IEEE80211_IS_CHAN_5GHZ(sc->sc_curchan) && sc->ext_5ghz_lna)) + lo += 0x10; + hi = lo + 0x20; + + /* retrieve false CCA count since last call (clear on read) */ + cca = RAL_READ(sc, RT2661_STA_CSR1) & 0xffff; + + if (dbm >= -35) { + bbp17 = 0x60; + } else if (dbm >= -58) { + bbp17 = hi; + } else if (dbm >= -66) { + bbp17 = lo + 0x10; + } else if (dbm >= -74) { + bbp17 = lo + 0x08; + } else { + /* RSSI < -74dBm, tune using false CCA count */ + + bbp17 = sc->bbp17; /* current value */ + + hi -= 2 * (-74 - dbm); + if (hi < lo) + hi = lo; + + if (bbp17 > hi) { + bbp17 = hi; + + } else if (cca > 512) { + if (++bbp17 > hi) + bbp17 = hi; + } else if (cca < 100) { + if (--bbp17 < lo) + bbp17 = lo; + } + } + + if (bbp17 != sc->bbp17) { + rt2661_bbp_write(sc, 17, bbp17); + sc->bbp17 = bbp17; + } +} + +/* + * Enter/Leave radar detection mode. + * This is for 802.11h additional regulatory domains. + */ +static void +rt2661_radar_start(struct rt2661_softc *sc) +{ + uint32_t tmp; + + /* disable Rx */ + tmp = RAL_READ(sc, RT2661_TXRX_CSR0); + RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp | RT2661_DISABLE_RX); + + rt2661_bbp_write(sc, 82, 0x20); + rt2661_bbp_write(sc, 83, 0x00); + rt2661_bbp_write(sc, 84, 0x40); + + /* save current BBP registers values */ + sc->bbp18 = rt2661_bbp_read(sc, 18); + sc->bbp21 = rt2661_bbp_read(sc, 21); + sc->bbp22 = rt2661_bbp_read(sc, 22); + sc->bbp16 = rt2661_bbp_read(sc, 16); + sc->bbp17 = rt2661_bbp_read(sc, 17); + sc->bbp64 = rt2661_bbp_read(sc, 64); + + rt2661_bbp_write(sc, 18, 0xff); + rt2661_bbp_write(sc, 21, 0x3f); + rt2661_bbp_write(sc, 22, 0x3f); + rt2661_bbp_write(sc, 16, 0xbd); + rt2661_bbp_write(sc, 17, sc->ext_5ghz_lna ? 0x44 : 0x34); + rt2661_bbp_write(sc, 64, 0x21); + + /* restore Rx filter */ + RAL_WRITE(sc, RT2661_TXRX_CSR0, tmp); +} + +static int +rt2661_radar_stop(struct rt2661_softc *sc) +{ + uint8_t bbp66; + + /* read radar detection result */ + bbp66 = rt2661_bbp_read(sc, 66); + + /* restore BBP registers values */ + rt2661_bbp_write(sc, 16, sc->bbp16); + rt2661_bbp_write(sc, 17, sc->bbp17); + rt2661_bbp_write(sc, 18, sc->bbp18); + rt2661_bbp_write(sc, 21, sc->bbp21); + rt2661_bbp_write(sc, 22, sc->bbp22); + rt2661_bbp_write(sc, 64, sc->bbp64); + + return bbp66 == 1; +} +#endif + +static int +rt2661_prepare_beacon(struct rt2661_softc *sc, struct ieee80211vap *vap) +{ + struct ieee80211com *ic = vap->iv_ic; + struct ieee80211_beacon_offsets bo; + struct rt2661_tx_desc desc; + struct mbuf *m0; + int rate; + + m0 = ieee80211_beacon_alloc(vap->iv_bss, &bo); + if (m0 == NULL) { + device_printf(sc->sc_dev, "could not allocate beacon frame\n"); + return ENOBUFS; + } + + /* send beacons at the lowest available rate */ + rate = IEEE80211_IS_CHAN_5GHZ(ic->ic_bsschan) ? 12 : 2; + + rt2661_setup_tx_desc(sc, &desc, RT2661_TX_TIMESTAMP, RT2661_TX_HWSEQ, + m0->m_pkthdr.len, rate, NULL, 0, RT2661_QID_MGT); + + /* copy the first 24 bytes of Tx descriptor into NIC memory */ + RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0, (uint8_t *)&desc, 24); + + /* copy beacon header and payload into NIC memory */ + RAL_WRITE_REGION_1(sc, RT2661_HW_BEACON_BASE0 + 24, + mtod(m0, uint8_t *), m0->m_pkthdr.len); + + m_freem(m0); + + return 0; +} + +/* + * Enable TSF synchronization and tell h/w to start sending beacons for IBSS + * and HostAP operating modes. + */ +static void +rt2661_enable_tsf_sync(struct rt2661_softc *sc) +{ + struct ifnet *ifp = sc->sc_ifp; + struct ieee80211com *ic = ifp->if_l2com; + struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); + uint32_t tmp; + + if (vap->iv_opmode != IEEE80211_M_STA) { + /* + * Change default 16ms TBTT adjustment to 8ms. + * Must be done before enabling beacon generation. + */ + RAL_WRITE(sc, RT2661_TXRX_CSR10, 1 << 12 | 8); + } + + tmp = RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000; + + /* set beacon interval (in 1/16ms unit) */ + tmp |= vap->iv_bss->ni_intval * 16; + + tmp |= RT2661_TSF_TICKING | RT2661_ENABLE_TBTT; + if (vap->iv_opmode == IEEE80211_M_STA) + tmp |= RT2661_TSF_MODE(1); + else + tmp |= RT2661_TSF_MODE(2) | RT2661_GENERATE_BEACON; + + RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp); +} + +static void +rt2661_enable_tsf(struct rt2661_softc *sc) +{ + RAL_WRITE(sc, RT2661_TXRX_CSR9, + (RAL_READ(sc, RT2661_TXRX_CSR9) & 0xff000000) + | RT2661_TSF_TICKING | RT2661_TSF_MODE(2)); +} + +/* + * Retrieve the "Received Signal Strength Indicator" from the raw values + * contained in Rx descriptors. The computation depends on which band the + * frame was received. Correction values taken from the reference driver. + */ +static int +rt2661_get_rssi(struct rt2661_softc *sc, uint8_t raw) +{ + int lna, agc, rssi; + + lna = (raw >> 5) & 0x3; + agc = raw & 0x1f; + + if (lna == 0) { + /* + * No mapping available. + * + * NB: Since RSSI is relative to noise floor, -1 is + * adequate for caller to know error happened. + */ + return -1; + } + + rssi = (2 * agc) - RT2661_NOISE_FLOOR; + + if (IEEE80211_IS_CHAN_2GHZ(sc->sc_curchan)) { + rssi += sc->rssi_2ghz_corr; + + if (lna == 1) + rssi -= 64; + else if (lna == 2) + rssi -= 74; + else if (lna == 3) + rssi -= 90; + } else { + rssi += sc->rssi_5ghz_corr; + + if (lna == 1) + rssi -= 64; + else if (lna == 2) + rssi -= 86; + else if (lna == 3) + rssi -= 100; + } + return rssi; +} + +static void +rt2661_scan_start(struct ieee80211com *ic) +{ + struct ifnet *ifp = ic->ic_ifp; + struct rt2661_softc *sc = ifp->if_softc; + uint32_t tmp; + + /* abort TSF synchronization */ + tmp = RAL_READ(sc, RT2661_TXRX_CSR9); + RAL_WRITE(sc, RT2661_TXRX_CSR9, tmp & ~0xffffff); + rt2661_set_bssid(sc, ifp->if_broadcastaddr); +} + +static void +rt2661_scan_end(struct ieee80211com *ic) +{ + struct ifnet *ifp = ic->ic_ifp; + struct rt2661_softc *sc = ifp->if_softc; + struct ieee80211vap *vap = TAILQ_FIRST(&ic->ic_vaps); + + rt2661_enable_tsf_sync(sc); + /* XXX keep local copy */ + rt2661_set_bssid(sc, vap->iv_bss->ni_bssid); +} + +static void +rt2661_set_channel(struct ieee80211com *ic) +{ + struct ifnet *ifp = ic->ic_ifp; + struct rt2661_softc *sc = ifp->if_softc; + + RAL_LOCK(sc); + rt2661_set_chan(sc, ic->ic_curchan); + RAL_UNLOCK(sc); + +} diff --git a/src/add-ons/kernel/drivers/network/wlan/ralinkwifi/dev/ral/rt2661reg.h b/src/add-ons/kernel/drivers/network/wlan/ralinkwifi/dev/ral/rt2661reg.h new file mode 100644 index 0000000000..b4325b053d --- /dev/null +++ b/src/add-ons/kernel/drivers/network/wlan/ralinkwifi/dev/ral/rt2661reg.h @@ -0,0 +1,488 @@ +/* $FreeBSD$ */ + +/*- + * Copyright (c) 2006 + * Damien Bergamini + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +#define RT2661_NOISE_FLOOR -95 + +#define RT2661_TX_RING_COUNT 32 +#define RT2661_MGT_RING_COUNT 32 +#define RT2661_RX_RING_COUNT 64 + +#define RT2661_TX_DESC_SIZE (sizeof (struct rt2661_tx_desc)) +#define RT2661_TX_DESC_WSIZE (RT2661_TX_DESC_SIZE / 4) +#define RT2661_RX_DESC_SIZE (sizeof (struct rt2661_rx_desc)) +#define RT2661_RX_DESC_WSIZE (RT2661_RX_DESC_SIZE / 4) + +#define RT2661_MAX_SCATTER 5 + +/* + * Control and status registers. + */ +#define RT2661_HOST_CMD_CSR 0x0008 +#define RT2661_MCU_CNTL_CSR 0x000c +#define RT2661_SOFT_RESET_CSR 0x0010 +#define RT2661_MCU_INT_SOURCE_CSR 0x0014 +#define RT2661_MCU_INT_MASK_CSR 0x0018 +#define RT2661_PCI_USEC_CSR 0x001c +#define RT2661_H2M_MAILBOX_CSR 0x2100 +#define RT2661_M2H_CMD_DONE_CSR 0x2104 +#define RT2661_HW_BEACON_BASE0 0x2c00 +#define RT2661_MAC_CSR0 0x3000 +#define RT2661_MAC_CSR1 0x3004 +#define RT2661_MAC_CSR2 0x3008 +#define RT2661_MAC_CSR3 0x300c +#define RT2661_MAC_CSR4 0x3010 +#define RT2661_MAC_CSR5 0x3014 +#define RT2661_MAC_CSR6 0x3018 +#define RT2661_MAC_CSR7 0x301c +#define RT2661_MAC_CSR8 0x3020 +#define RT2661_MAC_CSR9 0x3024 +#define RT2661_MAC_CSR10 0x3028 +#define RT2661_MAC_CSR11 0x302c +#define RT2661_MAC_CSR12 0x3030 +#define RT2661_MAC_CSR13 0x3034 +#define RT2661_MAC_CSR14 0x3038 +#define RT2661_MAC_CSR15 0x303c +#define RT2661_TXRX_CSR0 0x3040 +#define RT2661_TXRX_CSR1 0x3044 +#define RT2661_TXRX_CSR2 0x3048 +#define RT2661_TXRX_CSR3 0x304c +#define RT2661_TXRX_CSR4 0x3050 +#define RT2661_TXRX_CSR5 0x3054 +#define RT2661_TXRX_CSR6 0x3058 +#define RT2661_TXRX_CSR7 0x305c +#define RT2661_TXRX_CSR8 0x3060 +#define RT2661_TXRX_CSR9 0x3064 +#define RT2661_TXRX_CSR10 0x3068 +#define RT2661_TXRX_CSR11 0x306c +#define RT2661_TXRX_CSR12 0x3070 +#define RT2661_TXRX_CSR13 0x3074 +#define RT2661_TXRX_CSR14 0x3078 +#define RT2661_TXRX_CSR15 0x307c +#define RT2661_PHY_CSR0 0x3080 +#define RT2661_PHY_CSR1 0x3084 +#define RT2661_PHY_CSR2 0x3088 +#define RT2661_PHY_CSR3 0x308c +#define RT2661_PHY_CSR4 0x3090 +#define RT2661_PHY_CSR5 0x3094 +#define RT2661_PHY_CSR6 0x3098 +#define RT2661_PHY_CSR7 0x309c +#define RT2661_SEC_CSR0 0x30a0 +#define RT2661_SEC_CSR1 0x30a4 +#define RT2661_SEC_CSR2 0x30a8 +#define RT2661_SEC_CSR3 0x30ac +#define RT2661_SEC_CSR4 0x30b0 +#define RT2661_SEC_CSR5 0x30b4 +#define RT2661_STA_CSR0 0x30c0 +#define RT2661_STA_CSR1 0x30c4 +#define RT2661_STA_CSR2 0x30c8 +#define RT2661_STA_CSR3 0x30cc +#define RT2661_STA_CSR4 0x30d0 +#define RT2661_AC0_BASE_CSR 0x3400 +#define RT2661_AC1_BASE_CSR 0x3404 +#define RT2661_AC2_BASE_CSR 0x3408 +#define RT2661_AC3_BASE_CSR 0x340c +#define RT2661_MGT_BASE_CSR 0x3410 +#define RT2661_TX_RING_CSR0 0x3418 +#define RT2661_TX_RING_CSR1 0x341c +#define RT2661_AIFSN_CSR 0x3420 +#define RT2661_CWMIN_CSR 0x3424 +#define RT2661_CWMAX_CSR 0x3428 +#define RT2661_TX_DMA_DST_CSR 0x342c +#define RT2661_TX_CNTL_CSR 0x3430 +#define RT2661_LOAD_TX_RING_CSR 0x3434 +#define RT2661_RX_BASE_CSR 0x3450 +#define RT2661_RX_RING_CSR 0x3454 +#define RT2661_RX_CNTL_CSR 0x3458 +#define RT2661_PCI_CFG_CSR 0x3460 +#define RT2661_INT_SOURCE_CSR 0x3468 +#define RT2661_INT_MASK_CSR 0x346c +#define RT2661_E2PROM_CSR 0x3470 +#define RT2661_AC_TXOP_CSR0 0x3474 +#define RT2661_AC_TXOP_CSR1 0x3478 +#define RT2661_TEST_MODE_CSR 0x3484 +#define RT2661_IO_CNTL_CSR 0x3498 +#define RT2661_MCU_CODE_BASE 0x4000 + + +/* possible flags for register HOST_CMD_CSR */ +#define RT2661_KICK_CMD (1 << 7) +/* Host to MCU (8051) command identifiers */ +#define RT2661_MCU_CMD_SLEEP 0x30 +#define RT2661_MCU_CMD_WAKEUP 0x31 +#define RT2661_MCU_SET_LED 0x50 +#define RT2661_MCU_SET_RSSI_LED 0x52 + +/* possible flags for register MCU_CNTL_CSR */ +#define RT2661_MCU_SEL (1 << 0) +#define RT2661_MCU_RESET (1 << 1) +#define RT2661_MCU_READY (1 << 2) + +/* possible flags for register MCU_INT_SOURCE_CSR */ +#define RT2661_MCU_CMD_DONE 0xff +#define RT2661_MCU_WAKEUP (1 << 8) +#define RT2661_MCU_BEACON_EXPIRE (1 << 9) + +/* possible flags for register H2M_MAILBOX_CSR */ +#define RT2661_H2M_BUSY (1 << 24) +#define RT2661_TOKEN_NO_INTR 0xff + +/* possible flags for register MAC_CSR5 */ +#define RT2661_ONE_BSSID 3 + +/* possible flags for register TXRX_CSR0 */ +/* Tx filter flags are in the low 16 bits */ +#define RT2661_AUTO_TX_SEQ (1 << 15) +/* Rx filter flags are in the high 16 bits */ +#define RT2661_DISABLE_RX (1 << 16) +#define RT2661_DROP_CRC_ERROR (1 << 17) +#define RT2661_DROP_PHY_ERROR (1 << 18) +#define RT2661_DROP_CTL (1 << 19) +#define RT2661_DROP_NOT_TO_ME (1 << 20) +#define RT2661_DROP_TODS (1 << 21) +#define RT2661_DROP_VER_ERROR (1 << 22) +#define RT2661_DROP_MULTICAST (1 << 23) +#define RT2661_DROP_BROADCAST (1 << 24) +#define RT2661_DROP_ACKCTS (1 << 25) + +/* possible flags for register TXRX_CSR4 */ +#define RT2661_SHORT_PREAMBLE (1 << 19) +#define RT2661_MRR_ENABLED (1 << 20) +#define RT2661_MRR_CCK_FALLBACK (1 << 23) + +/* possible flags for register TXRX_CSR9 */ +#define RT2661_TSF_TICKING (1 << 16) +#define RT2661_TSF_MODE(x) (((x) & 0x3) << 17) +/* TBTT stands for Target Beacon Transmission Time */ +#define RT2661_ENABLE_TBTT (1 << 19) +#define RT2661_GENERATE_BEACON (1 << 20) + +/* possible flags for register PHY_CSR0 */ +#define RT2661_PA_PE_2GHZ (1 << 16) +#define RT2661_PA_PE_5GHZ (1 << 17) + +/* possible flags for register PHY_CSR3 */ +#define RT2661_BBP_READ (1 << 15) +#define RT2661_BBP_BUSY (1 << 16) + +/* possible flags for register PHY_CSR4 */ +#define RT2661_RF_21BIT (21 << 24) +#define RT2661_RF_BUSY (1 << 31) + +/* possible values for register STA_CSR4 */ +#define RT2661_TX_STAT_VALID (1 << 0) +#define RT2661_TX_RESULT(v) (((v) >> 1) & 0x7) +#define RT2661_TX_RETRYCNT(v) (((v) >> 4) & 0xf) +#define RT2661_TX_QID(v) (((v) >> 8) & 0xf) +#define RT2661_TX_SUCCESS 0 +#define RT2661_TX_RETRY_FAIL 6 + +/* possible flags for register TX_CNTL_CSR */ +#define RT2661_KICK_MGT (1 << 4) + +/* possible flags for register INT_SOURCE_CSR */ +#define RT2661_TX_DONE (1 << 0) +#define RT2661_RX_DONE (1 << 1) +#define RT2661_TX0_DMA_DONE (1 << 16) +#define RT2661_TX1_DMA_DONE (1 << 17) +#define RT2661_TX2_DMA_DONE (1 << 18) +#define RT2661_TX3_DMA_DONE (1 << 19) +#define RT2661_MGT_DONE (1 << 20) + +/* possible flags for register E2PROM_CSR */ +#define RT2661_C (1 << 1) +#define RT2661_S (1 << 2) +#define RT2661_D (1 << 3) +#define RT2661_Q (1 << 4) +#define RT2661_93C46 (1 << 5) + +/* Tx descriptor */ +struct rt2661_tx_desc { + uint32_t flags; +#define RT2661_TX_BUSY (1 << 0) +#define RT2661_TX_VALID (1 << 1) +#define RT2661_TX_MORE_FRAG (1 << 2) +#define RT2661_TX_NEED_ACK (1 << 3) +#define RT2661_TX_TIMESTAMP (1 << 4) +#define RT2661_TX_OFDM (1 << 5) +#define RT2661_TX_IFS (1 << 6) +#define RT2661_TX_LONG_RETRY (1 << 7) +#define RT2661_TX_BURST (1 << 28) + + uint16_t wme; +#define RT2661_QID(v) (v) +#define RT2661_AIFSN(v) ((v) << 4) +#define RT2661_LOGCWMIN(v) ((v) << 8) +#define RT2661_LOGCWMAX(v) ((v) << 12) + + uint16_t xflags; +#define RT2661_TX_HWSEQ (1 << 12) + + uint8_t plcp_signal; + uint8_t plcp_service; +#define RT2661_PLCP_LENGEXT 0x80 + + uint8_t plcp_length_lo; + uint8_t plcp_length_hi; + + uint32_t iv; + uint32_t eiv; + + uint8_t offset; + uint8_t qid; +#define RT2661_QID_MGT 13 + + uint8_t txpower; +#define RT2661_DEFAULT_TXPOWER 0 + + uint8_t reserved1; + + uint32_t addr[RT2661_MAX_SCATTER]; + uint16_t len[RT2661_MAX_SCATTER]; + + uint16_t reserved2; +} __packed; + +/* Rx descriptor */ +struct rt2661_rx_desc { + uint32_t flags; +#define RT2661_RX_BUSY (1 << 0) +#define RT2661_RX_DROP (1 << 1) +#define RT2661_RX_CRC_ERROR (1 << 6) +#define RT2661_RX_OFDM (1 << 7) +#define RT2661_RX_PHY_ERROR (1 << 8) +#define RT2661_RX_CIPHER_MASK 0x00000600 + + uint8_t rate; + uint8_t rssi; + uint8_t reserved1; + uint8_t offset; + uint32_t iv; + uint32_t eiv; + uint32_t reserved2; + uint32_t physaddr; + uint32_t reserved3[10]; +} __packed; + +#define RAL_RF1 0 +#define RAL_RF2 2 +#define RAL_RF3 1 +#define RAL_RF4 3 + +/* dual-band RF */ +#define RT2661_RF_5225 1 +#define RT2661_RF_5325 2 +/* single-band RF */ +#define RT2661_RF_2527 3 +#define RT2661_RF_2529 4 + +#define RT2661_RX_DESC_BACK 4 + +#define RT2661_SMART_MODE (1 << 0) + +#define RT2661_BBPR94_DEFAULT 6 + +#define RT2661_SHIFT_D 3 +#define RT2661_SHIFT_Q 4 + +#define RT2661_EEPROM_MAC01 0x02 +#define RT2661_EEPROM_MAC23 0x03 +#define RT2661_EEPROM_MAC45 0x04 +#define RT2661_EEPROM_ANTENNA 0x10 +#define RT2661_EEPROM_CONFIG2 0x11 +#define RT2661_EEPROM_BBP_BASE 0x13 +#define RT2661_EEPROM_TXPOWER 0x23 +#define RT2661_EEPROM_FREQ_OFFSET 0x2f +#define RT2661_EEPROM_RSSI_2GHZ_OFFSET 0x4d +#define RT2661_EEPROM_RSSI_5GHZ_OFFSET 0x4e + +#define RT2661_EEPROM_DELAY 1 /* minimum hold time (microsecond) */ + +/* + * control and status registers access macros + */ +#define RAL_READ(sc, reg) \ + bus_space_read_4((sc)->sc_st, (sc)->sc_sh, (reg)) + +#define RAL_READ_REGION_4(sc, offset, datap, count) \ + bus_space_read_region_4((sc)->sc_st, (sc)->sc_sh, (offset), \ + (datap), (count)) + +#define RAL_WRITE(sc, reg, val) \ + bus_space_write_4((sc)->sc_st, (sc)->sc_sh, (reg), (val)) + +#define RAL_WRITE_REGION_1(sc, offset, datap, count) \ + bus_space_write_region_1((sc)->sc_st, (sc)->sc_sh, (offset), \ + (datap), (count)) + +/* + * EEPROM access macro + */ +#define RT2661_EEPROM_CTL(sc, val) do { \ + RAL_WRITE((sc), RT2661_E2PROM_CSR, (val)); \ + DELAY(RT2661_EEPROM_DELAY); \ +} while (/* CONSTCOND */0) + +/* + * Default values for MAC registers; values taken from the reference driver. + */ +#define RT2661_DEF_MAC \ + { RT2661_TXRX_CSR0, 0x0000b032 }, \ + { RT2661_TXRX_CSR1, 0x9eb39eb3 }, \ + { RT2661_TXRX_CSR2, 0x8a8b8c8d }, \ + { RT2661_TXRX_CSR3, 0x00858687 }, \ + { RT2661_TXRX_CSR7, 0x2e31353b }, \ + { RT2661_TXRX_CSR8, 0x2a2a2a2c }, \ + { RT2661_TXRX_CSR15, 0x0000000f }, \ + { RT2661_MAC_CSR6, 0x00000fff }, \ + { RT2661_MAC_CSR8, 0x016c030a }, \ + { RT2661_MAC_CSR10, 0x00000718 }, \ + { RT2661_MAC_CSR12, 0x00000004 }, \ + { RT2661_MAC_CSR13, 0x0000e000 }, \ + { RT2661_SEC_CSR0, 0x00000000 }, \ + { RT2661_SEC_CSR1, 0x00000000 }, \ + { RT2661_SEC_CSR5, 0x00000000 }, \ + { RT2661_PHY_CSR1, 0x000023b0 }, \ + { RT2661_PHY_CSR5, 0x060a100c }, \ + { RT2661_PHY_CSR6, 0x00080606 }, \ + { RT2661_PHY_CSR7, 0x00000a08 }, \ + { RT2661_PCI_CFG_CSR, 0x3cca4808 }, \ + { RT2661_AIFSN_CSR, 0x00002273 }, \ + { RT2661_CWMIN_CSR, 0x00002344 }, \ + { RT2661_CWMAX_CSR, 0x000034aa }, \ + { RT2661_TEST_MODE_CSR, 0x00000200 }, \ + { RT2661_M2H_CMD_DONE_CSR, 0xffffffff } + +/* + * Default values for BBP registers; values taken from the reference driver. + */ +#define RT2661_DEF_BBP \ + { 3, 0x00 }, \ + { 15, 0x30 }, \ + { 17, 0x20 }, \ + { 21, 0xc8 }, \ + { 22, 0x38 }, \ + { 23, 0x06 }, \ + { 24, 0xfe }, \ + { 25, 0x0a }, \ + { 26, 0x0d }, \ + { 34, 0x12 }, \ + { 37, 0x07 }, \ + { 39, 0xf8 }, \ + { 41, 0x60 }, \ + { 53, 0x10 }, \ + { 54, 0x18 }, \ + { 60, 0x10 }, \ + { 61, 0x04 }, \ + { 62, 0x04 }, \ + { 75, 0xfe }, \ + { 86, 0xfe }, \ + { 88, 0xfe }, \ + { 90, 0x0f }, \ + { 99, 0x00 }, \ + { 102, 0x16 }, \ + { 107, 0x04 } + +/* + * Default settings for RF registers; values taken from the reference driver. + */ +#define RT2661_RF5225_1 \ + { 1, 0x00b33, 0x011e1, 0x1a014, 0x30282 }, \ + { 2, 0x00b33, 0x011e1, 0x1a014, 0x30287 }, \ + { 3, 0x00b33, 0x011e2, 0x1a014, 0x30282 }, \ + { 4, 0x00b33, 0x011e2, 0x1a014, 0x30287 }, \ + { 5, 0x00b33, 0x011e3, 0x1a014, 0x30282 }, \ + { 6, 0x00b33, 0x011e3, 0x1a014, 0x30287 }, \ + { 7, 0x00b33, 0x011e4, 0x1a014, 0x30282 }, \ + { 8, 0x00b33, 0x011e4, 0x1a014, 0x30287 }, \ + { 9, 0x00b33, 0x011e5, 0x1a014, 0x30282 }, \ + { 10, 0x00b33, 0x011e5, 0x1a014, 0x30287 }, \ + { 11, 0x00b33, 0x011e6, 0x1a014, 0x30282 }, \ + { 12, 0x00b33, 0x011e6, 0x1a014, 0x30287 }, \ + { 13, 0x00b33, 0x011e7, 0x1a014, 0x30282 }, \ + { 14, 0x00b33, 0x011e8, 0x1a014, 0x30284 }, \ + \ + { 36, 0x00b33, 0x01266, 0x26014, 0x30288 }, \ + { 40, 0x00b33, 0x01268, 0x26014, 0x30280 }, \ + { 44, 0x00b33, 0x01269, 0x26014, 0x30282 }, \ + { 48, 0x00b33, 0x0126a, 0x26014, 0x30284 }, \ + { 52, 0x00b33, 0x0126b, 0x26014, 0x30286 }, \ + { 56, 0x00b33, 0x0126c, 0x26014, 0x30288 }, \ + { 60, 0x00b33, 0x0126e, 0x26014, 0x30280 }, \ + { 64, 0x00b33, 0x0126f, 0x26014, 0x30282 }, \ + \ + { 100, 0x00b33, 0x0128a, 0x2e014, 0x30280 }, \ + { 104, 0x00b33, 0x0128b, 0x2e014, 0x30282 }, \ + { 108, 0x00b33, 0x0128c, 0x2e014, 0x30284 }, \ + { 112, 0x00b33, 0x0128d, 0x2e014, 0x30286 }, \ + { 116, 0x00b33, 0x0128e, 0x2e014, 0x30288 }, \ + { 120, 0x00b33, 0x012a0, 0x2e014, 0x30280 }, \ + { 124, 0x00b33, 0x012a1, 0x2e014, 0x30282 }, \ + { 128, 0x00b33, 0x012a2, 0x2e014, 0x30284 }, \ + { 132, 0x00b33, 0x012a3, 0x2e014, 0x30286 }, \ + { 136, 0x00b33, 0x012a4, 0x2e014, 0x30288 }, \ + { 140, 0x00b33, 0x012a6, 0x2e014, 0x30280 }, \ + \ + { 149, 0x00b33, 0x012a8, 0x2e014, 0x30287 }, \ + { 153, 0x00b33, 0x012a9, 0x2e014, 0x30289 }, \ + { 157, 0x00b33, 0x012ab, 0x2e014, 0x30281 }, \ + { 161, 0x00b33, 0x012ac, 0x2e014, 0x30283 }, \ + { 165, 0x00b33, 0x012ad, 0x2e014, 0x30285 } + +#define RT2661_RF5225_2 \ + { 1, 0x00b33, 0x011e1, 0x1a014, 0x30282 }, \ + { 2, 0x00b33, 0x011e1, 0x1a014, 0x30287 }, \ + { 3, 0x00b33, 0x011e2, 0x1a014, 0x30282 }, \ + { 4, 0x00b33, 0x011e2, 0x1a014, 0x30287 }, \ + { 5, 0x00b33, 0x011e3, 0x1a014, 0x30282 }, \ + { 6, 0x00b33, 0x011e3, 0x1a014, 0x30287 }, \ + { 7, 0x00b33, 0x011e4, 0x1a014, 0x30282 }, \ + { 8, 0x00b33, 0x011e4, 0x1a014, 0x30287 }, \ + { 9, 0x00b33, 0x011e5, 0x1a014, 0x30282 }, \ + { 10, 0x00b33, 0x011e5, 0x1a014, 0x30287 }, \ + { 11, 0x00b33, 0x011e6, 0x1a014, 0x30282 }, \ + { 12, 0x00b33, 0x011e6, 0x1a014, 0x30287 }, \ + { 13, 0x00b33, 0x011e7, 0x1a014, 0x30282 }, \ + { 14, 0x00b33, 0x011e8, 0x1a014, 0x30284 }, \ + \ + { 36, 0x00b35, 0x11206, 0x26014, 0x30280 }, \ + { 40, 0x00b34, 0x111a0, 0x26014, 0x30280 }, \ + { 44, 0x00b34, 0x111a1, 0x26014, 0x30286 }, \ + { 48, 0x00b34, 0x111a3, 0x26014, 0x30282 }, \ + { 52, 0x00b34, 0x111a4, 0x26014, 0x30288 }, \ + { 56, 0x00b34, 0x111a6, 0x26014, 0x30284 }, \ + { 60, 0x00b34, 0x111a8, 0x26014, 0x30280 }, \ + { 64, 0x00b34, 0x111a9, 0x26014, 0x30286 }, \ + \ + { 100, 0x00b35, 0x11226, 0x2e014, 0x30280 }, \ + { 104, 0x00b35, 0x11228, 0x2e014, 0x30280 }, \ + { 108, 0x00b35, 0x1122a, 0x2e014, 0x30280 }, \ + { 112, 0x00b35, 0x1122c, 0x2e014, 0x30280 }, \ + { 116, 0x00b35, 0x1122e, 0x2e014, 0x30280 }, \ + { 120, 0x00b34, 0x111c0, 0x2e014, 0x30280 }, \ + { 124, 0x00b34, 0x111c1, 0x2e014, 0x30286 }, \ + { 128, 0x00b34, 0x111c3, 0x2e014, 0x30282 }, \ + { 132, 0x00b34, 0x111c4, 0x2e014, 0x30288 }, \ + { 136, 0x00b34, 0x111c6, 0x2e014, 0x30284 }, \ + { 140, 0x00b34, 0x111c8, 0x2e014, 0x30280 }, \ + \ + { 149, 0x00b34, 0x111cb, 0x2e014, 0x30286 }, \ + { 153, 0x00b34, 0x111cd, 0x2e014, 0x30282 }, \ + { 157, 0x00b35, 0x11242, 0x2e014, 0x30285 }, \ + { 161, 0x00b35, 0x11244, 0x2e014, 0x30285 }, \ + { 165, 0x00b35, 0x11246, 0x2e014, 0x30285 } diff --git a/src/add-ons/kernel/drivers/network/wlan/ralinkwifi/dev/ral/rt2661var.h b/src/add-ons/kernel/drivers/network/wlan/ralinkwifi/dev/ral/rt2661var.h new file mode 100644 index 0000000000..db1d4de56f --- /dev/null +++ b/src/add-ons/kernel/drivers/network/wlan/ralinkwifi/dev/ral/rt2661var.h @@ -0,0 +1,180 @@ +/* $FreeBSD$ */ + +/*- + * Copyright (c) 2005 + * Damien Bergamini + * + * Permission to use, copy, modify, and distribute this software for any + * purpose with or without fee is hereby granted, provided that the above + * copyright notice and this permission notice appear in all copies. + * + * THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES + * WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF + * MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR + * ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES + * WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN + * ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF + * OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE. + */ + +struct rt2661_rx_radiotap_header { + struct ieee80211_radiotap_header wr_ihdr; + uint64_t wr_tsf; + uint8_t wr_flags; + uint8_t wr_rate; + uint16_t wr_chan_freq; + uint16_t wr_chan_flags; + int8_t wr_antsignal; + int8_t wr_antnoise; +} __packed; + +#define RT2661_RX_RADIOTAP_PRESENT \ + ((1 << IEEE80211_RADIOTAP_TSFT) | \ + (1 << IEEE80211_RADIOTAP_FLAGS) | \ + (1 << IEEE80211_RADIOTAP_RATE) | \ + (1 << IEEE80211_RADIOTAP_CHANNEL) | \ + (1 << IEEE80211_RADIOTAP_DBM_ANTSIGNAL) | \ + (1 << IEEE80211_RADIOTAP_DBM_ANTNOISE)) + +struct rt2661_tx_radiotap_header { + struct ieee80211_radiotap_header wt_ihdr; + uint8_t wt_flags; + uint8_t wt_rate; + uint16_t wt_chan_freq; + uint16_t wt_chan_flags; +} __packed; + +#define RT2661_TX_RADIOTAP_PRESENT \ + ((1 << IEEE80211_RADIOTAP_FLAGS) | \ + (1 << IEEE80211_RADIOTAP_RATE) | \ + (1 << IEEE80211_RADIOTAP_CHANNEL)) + +struct rt2661_tx_data { + bus_dmamap_t map; + struct mbuf *m; + struct ieee80211_node *ni; + uint8_t rix; + int8_t rssi; +}; + +struct rt2661_tx_ring { + bus_dma_tag_t desc_dmat; + bus_dma_tag_t data_dmat; + bus_dmamap_t desc_map; + bus_addr_t physaddr; + struct rt2661_tx_desc *desc; + struct rt2661_tx_data *data; + int count; + int queued; + int cur; + int next; + int stat; +}; + +struct rt2661_rx_data { + bus_dmamap_t map; + struct mbuf *m; +}; + +struct rt2661_rx_ring { + bus_dma_tag_t desc_dmat; + bus_dma_tag_t data_dmat; + bus_dmamap_t desc_map; + bus_addr_t physaddr; + struct rt2661_rx_desc *desc; + struct rt2661_rx_data *data; + int count; + int cur; + int next; +}; + +struct rt2661_node { + struct ieee80211_node ni; + struct ieee80211_amrr_node amrr; +}; +#define RT2661_NODE(ni) ((struct rt2661_node *)(ni)) + +struct rt2661_vap { + struct ieee80211vap ral_vap; + struct ieee80211_amrr amrr; + + int (*ral_newstate)(struct ieee80211vap *, + enum ieee80211_state, int); +}; +#define RT2661_VAP(vap) ((struct rt2661_vap *)(vap)) + +struct rt2661_softc { + struct ifnet *sc_ifp; + device_t sc_dev; + bus_space_tag_t sc_st; + bus_space_handle_t sc_sh; + + struct mtx sc_mtx; + + struct callout watchdog_ch; + + int sc_tx_timer; + int sc_invalid; + int sc_debug; +/* + * The same in both up to here + * ------------------------------------------------ + */ + + int sc_flags; +#define RAL_FW_LOADED 0x1 +#define RAL_INPUT_RUNNING 0x2 + int sc_id; + struct ieee80211_channel *sc_curchan; + + uint8_t rf_rev; + + uint8_t rfprog; + uint8_t rffreq; + + struct rt2661_tx_ring txq[4]; + struct rt2661_tx_ring mgtq; + struct rt2661_rx_ring rxq; + + uint32_t rf_regs[4]; + int8_t txpow[38]; + + struct { + uint8_t reg; + uint8_t val; + } bbp_prom[16]; + + int hw_radio; + int rx_ant; + int tx_ant; + int nb_ant; + int ext_2ghz_lna; + int ext_5ghz_lna; + int rssi_2ghz_corr; + int rssi_5ghz_corr; + + uint8_t bbp18; + uint8_t bbp21; + uint8_t bbp22; + uint8_t bbp16; + uint8_t bbp17; + uint8_t bbp64; + + int dwelltime; + + struct rt2661_rx_radiotap_header sc_rxtap; + int sc_rxtap_len; + struct rt2661_tx_radiotap_header sc_txtap; + int sc_txtap_len; +}; + +int rt2661_attach(device_t, int); +int rt2661_detach(void *); +void rt2661_shutdown(void *); +void rt2661_suspend(void *); +void rt2661_resume(void *); +void rt2661_intr(void *); + +#define RAL_LOCK(sc) mtx_lock(&(sc)->sc_mtx) +#define RAL_LOCK_ASSERT(sc) mtx_assert(&(sc)->sc_mtx, MA_OWNED) +#define RAL_UNLOCK(sc) mtx_unlock(&(sc)->sc_mtx)