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another panel modeline update

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git-svn-id: file:///srv/svn/repos/haiku/trunk/current@7434 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen
2004-05-06 18:45:40 +00:00
parent 6bef4567da
commit bef5b86a74
3 changed files with 6 additions and 6 deletions
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src/add-ons/accelerants/nvidia/engine/nv_crtc.c
+2 -2
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@@ -131,8 +131,8 @@ status_t nv_crtc_set_timing(display_mode target)
target.timing.h_display)) & 0xfff8; target.timing.h_display)) & 0xfff8;
target.timing.h_total = target.timing.h_total =
((uint16)((p1.timing.h_total / ((float)p1.timing.h_display)) * (((uint16)((p1.timing.h_total / ((float)p1.timing.h_display)) *
target.timing.h_display)) & 0xfff8; target.timing.h_display)) & 0xfff8) - 8;
if (target.timing.h_sync_start == target.timing.h_display) if (target.timing.h_sync_start == target.timing.h_display)
target.timing.h_sync_start += 8; target.timing.h_sync_start += 8;
src/add-ons/accelerants/nvidia/engine/nv_crtc2.c
+2 -2
View File
@@ -117,8 +117,8 @@ status_t nv_crtc2_set_timing(display_mode target)
target.timing.h_display)) & 0xfff8; target.timing.h_display)) & 0xfff8;
target.timing.h_total = target.timing.h_total =
((uint16)((p2.timing.h_total / ((float)p2.timing.h_display)) * (((uint16)((p2.timing.h_total / ((float)p2.timing.h_display)) *
target.timing.h_display)) & 0xfff8; target.timing.h_display)) & 0xfff8) - 8;
if (target.timing.h_sync_start == target.timing.h_display) if (target.timing.h_sync_start == target.timing.h_display)
target.timing.h_sync_start += 8; target.timing.h_sync_start += 8;
src/add-ons/accelerants/nvidia/engine/nv_general.c
+2 -2
View File
@@ -80,7 +80,7 @@ status_t nv_general_powerup()
{ {
status_t status; status_t status;
LOG(1,("POWERUP: nVidia (open)BeOS Accelerant 0.10-20 running.\n")); LOG(1,("POWERUP: nVidia (open)BeOS Accelerant 0.10-21 running.\n"));
/* preset no laptop */ /* preset no laptop */
si->ps.laptop = false; si->ps.laptop = false;
@@ -1033,7 +1033,7 @@ static status_t nv_general_bios_to_powergraphics()
* bit 12: overlay engine (all cards), * bit 12: overlay engine (all cards),
* bit 9: TVout chip #2 (confirmed on NV18, NV25, NV28), * bit 9: TVout chip #2 (confirmed on NV18, NV25, NV28),
* bit 8: TVout chip #1 (all cards), * bit 8: TVout chip #1 (all cards),
* bit 4: DDC channel (all cards) */ * bit 4: both I2C busses (all cards) */
NV_REG32(NV32_2FUNCSEL) &= ~0x00001000; NV_REG32(NV32_2FUNCSEL) &= ~0x00001000;
NV_REG32(NV32_FUNCSEL) |= 0x00001000; NV_REG32(NV32_FUNCSEL) |= 0x00001000;
} }