diff --git a/headers/private/graphics/skeleton/DriverInterface.h b/headers/private/graphics/skeleton/DriverInterface.h index 121cd15484..67ed9c4a15 100644 --- a/headers/private/graphics/skeleton/DriverInterface.h +++ b/headers/private/graphics/skeleton/DriverInterface.h @@ -38,7 +38,7 @@ typedef struct { #define DELETE_BEN(x) delete_sem(x.sem); -#define NV_PRIVATE_DATA_MAGIC 0x0009 /* a private driver rev, of sorts */ +#define SKEL_PRIVATE_DATA_MAGIC 0x0009 /* a private driver rev, of sorts */ /*dualhead extensions to flags*/ #define DUALHEAD_OFF (0<<6) @@ -61,15 +61,15 @@ typedef struct { #define SKD_HANDLER_INSTALLED 0x80000000 enum { - NV_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, - NV_GET_PCI, - NV_SET_PCI, - NV_DEVICE_NAME, - NV_RUN_INTERRUPTS, - NV_GET_NTH_AGP_INFO, - NV_ENABLE_AGP, - NV_ISA_OUT, - NV_ISA_IN + ENG_GET_PRIVATE_DATA = B_DEVICE_OP_CODES_END + 1, + ENG_GET_PCI, + ENG_SET_PCI, + ENG_DEVICE_NAME, + ENG_RUN_INTERRUPTS, + ENG_GET_NTH_AGP_INFO, + ENG_ENABLE_AGP, + ENG_ISA_OUT, + ENG_ISA_IN }; /* max. number of overlay buffers */ diff --git a/headers/private/graphics/skeleton/macros.h b/headers/private/graphics/skeleton/macros.h index 1f146d0283..06caf0d88c 100644 --- a/headers/private/graphics/skeleton/macros.h +++ b/headers/private/graphics/skeleton/macros.h @@ -1,800 +1,800 @@ -/* NV registers definitions and macros for access to them */ +/* registers definitions and macros for access to them */ /* PCI_config_space */ -#define NVCFG_DEVID 0x00 -#define NVCFG_DEVCTRL 0x04 -#define NVCFG_CLASS 0x08 -#define NVCFG_HEADER 0x0c -#define NVCFG_BASE1REGS 0x10 -#define NVCFG_BASE2FB 0x14 -#define NVCFG_BASE3 0x18 -#define NVCFG_BASE4 0x1c //unknown if used -#define NVCFG_BASE5 0x20 //unknown if used -#define NVCFG_BASE6 0x24 //unknown if used -#define NVCFG_BASE7 0x28 //unknown if used -#define NVCFG_SUBSYSID1 0x2c -#define NVCFG_ROMBASE 0x30 -#define NVCFG_CAPPTR 0x34 -#define NVCFG_CFG_1 0x38 //unknown if used -#define NVCFG_INTERRUPT 0x3c -#define NVCFG_SUBSYSID2 0x40 -#define NVCFG_AGPREF 0x44 -#define NVCFG_AGPSTAT 0x48 -#define NVCFG_AGPCMD 0x4c -#define NVCFG_ROMSHADOW 0x50 -#define NVCFG_VGA 0x54 -#define NVCFG_SCHRATCH 0x58 -#define NVCFG_CFG_10 0x5c -#define NVCFG_CFG_11 0x60 -#define NVCFG_CFG_12 0x64 -#define NVCFG_CFG_13 0x68 //unknown if used -#define NVCFG_CFG_14 0x6c //unknown if used -#define NVCFG_CFG_15 0x70 //unknown if used -#define NVCFG_CFG_16 0x74 //unknown if used -#define NVCFG_CFG_17 0x78 //unknown if used -#define NVCFG_CFG_18 0x7c //unknown if used -#define NVCFG_CFG_19 0x80 //unknown if used -#define NVCFG_CFG_20 0x84 //unknown if used -#define NVCFG_CFG_21 0x88 //unknown if used -#define NVCFG_CFG_22 0x8c //unknown if used -#define NVCFG_CFG_23 0x90 //unknown if used -#define NVCFG_CFG_24 0x94 //unknown if used -#define NVCFG_CFG_25 0x98 //unknown if used -#define NVCFG_CFG_26 0x9c //unknown if used -#define NVCFG_CFG_27 0xa0 //unknown if used -#define NVCFG_CFG_28 0xa4 //unknown if used -#define NVCFG_CFG_29 0xa8 //unknown if used -#define NVCFG_CFG_30 0xac //unknown if used -#define NVCFG_CFG_31 0xb0 //unknown if used -#define NVCFG_CFG_32 0xb4 //unknown if used -#define NVCFG_CFG_33 0xb8 //unknown if used -#define NVCFG_CFG_34 0xbc //unknown if used -#define NVCFG_CFG_35 0xc0 //unknown if used -#define NVCFG_CFG_36 0xc4 //unknown if used -#define NVCFG_CFG_37 0xc8 //unknown if used -#define NVCFG_CFG_38 0xcc //unknown if used -#define NVCFG_CFG_39 0xd0 //unknown if used -#define NVCFG_CFG_40 0xd4 //unknown if used -#define NVCFG_CFG_41 0xd8 //unknown if used -#define NVCFG_CFG_42 0xdc //unknown if used -#define NVCFG_CFG_43 0xe0 //unknown if used -#define NVCFG_CFG_44 0xe4 //unknown if used -#define NVCFG_CFG_45 0xe8 //unknown if used -#define NVCFG_CFG_46 0xec //unknown if used -#define NVCFG_CFG_47 0xf0 //unknown if used -#define NVCFG_CFG_48 0xf4 //unknown if used -#define NVCFG_CFG_49 0xf8 //unknown if used -#define NVCFG_CFG_50 0xfc //unknown if used +#define ENCFG_DEVID 0x00 +#define ENCFG_DEVCTRL 0x04 +#define ENCFG_CLASS 0x08 +#define ENCFG_HEADER 0x0c +#define ENCFG_BASE1REGS 0x10 +#define ENCFG_BASE2FB 0x14 +#define ENCFG_BASE3 0x18 +#define ENCFG_BASE4 0x1c //unknown if used +#define ENCFG_BASE5 0x20 //unknown if used +#define ENCFG_BASE6 0x24 //unknown if used +#define ENCFG_BASE7 0x28 //unknown if used +#define ENCFG_SUBSYSID1 0x2c +#define ENCFG_ROMBASE 0x30 +#define ENCFG_CAPPTR 0x34 +#define ENCFG_CFG_1 0x38 //unknown if used +#define ENCFG_INTERRUPT 0x3c +#define ENCFG_SUBSYSID2 0x40 +#define ENCFG_AGPREF 0x44 +#define ENCFG_AGPSTAT 0x48 +#define ENCFG_AGPCMD 0x4c +#define ENCFG_ROMSHADOW 0x50 +#define ENCFG_VGA 0x54 +#define ENCFG_SCHRATCH 0x58 +#define ENCFG_CFG_10 0x5c +#define ENCFG_CFG_11 0x60 +#define ENCFG_CFG_12 0x64 +#define ENCFG_CFG_13 0x68 //unknown if used +#define ENCFG_CFG_14 0x6c //unknown if used +#define ENCFG_CFG_15 0x70 //unknown if used +#define ENCFG_CFG_16 0x74 //unknown if used +#define ENCFG_CFG_17 0x78 //unknown if used +#define ENCFG_CFG_18 0x7c //unknown if used +#define ENCFG_CFG_19 0x80 //unknown if used +#define ENCFG_CFG_20 0x84 //unknown if used +#define ENCFG_CFG_21 0x88 //unknown if used +#define ENCFG_CFG_22 0x8c //unknown if used +#define ENCFG_CFG_23 0x90 //unknown if used +#define ENCFG_CFG_24 0x94 //unknown if used +#define ENCFG_CFG_25 0x98 //unknown if used +#define ENCFG_CFG_26 0x9c //unknown if used +#define ENCFG_CFG_27 0xa0 //unknown if used +#define ENCFG_CFG_28 0xa4 //unknown if used +#define ENCFG_CFG_29 0xa8 //unknown if used +#define ENCFG_CFG_30 0xac //unknown if used +#define ENCFG_CFG_31 0xb0 //unknown if used +#define ENCFG_CFG_32 0xb4 //unknown if used +#define ENCFG_CFG_33 0xb8 //unknown if used +#define ENCFG_CFG_34 0xbc //unknown if used +#define ENCFG_CFG_35 0xc0 //unknown if used +#define ENCFG_CFG_36 0xc4 //unknown if used +#define ENCFG_CFG_37 0xc8 //unknown if used +#define ENCFG_CFG_38 0xcc //unknown if used +#define ENCFG_CFG_39 0xd0 //unknown if used +#define ENCFG_CFG_40 0xd4 //unknown if used +#define ENCFG_CFG_41 0xd8 //unknown if used +#define ENCFG_CFG_42 0xdc //unknown if used +#define ENCFG_CFG_43 0xe0 //unknown if used +#define ENCFG_CFG_44 0xe4 //unknown if used +#define ENCFG_CFG_45 0xe8 //unknown if used +#define ENCFG_CFG_46 0xec //unknown if used +#define ENCFG_CFG_47 0xf0 //unknown if used +#define ENCFG_CFG_48 0xf4 //unknown if used +#define ENCFG_CFG_49 0xf8 //unknown if used +#define ENCFG_CFG_50 0xfc //unknown if used -/* used NV INT registers for vblank */ -#define NV32_MAIN_INTE 0x00000140 -#define NV32_CRTC_INTS 0x00600100 -#define NV32_CRTC_INTE 0x00600140 +/* used INT registers for vblank */ +#define RG32_MAIN_INTE 0x00000140 +#define RG32_CRTC_INTS 0x00600100 +#define RG32_CRTC_INTE 0x00600140 -/* NV ACCeleration registers */ +/* ACCeleration registers */ /* engine initialisation registers */ -#define NVACC_FORMATS 0x00400618 -#define NVACC_OFFSET0 0x00400640 -#define NVACC_OFFSET1 0x00400644 -#define NVACC_OFFSET2 0x00400648 -#define NVACC_OFFSET3 0x0040064c -#define NVACC_OFFSET4 0x00400650 -#define NVACC_OFFSET5 0x00400654 -#define NVACC_BBASE0 0x00400658 -#define NVACC_BBASE1 0x0040065c -#define NVACC_BBASE2 0x00400660 -#define NVACC_BBASE3 0x00400664 -#define NVACC_NV10_BBASE4 0x00400668 -#define NVACC_NV10_BBASE5 0x0040066c -#define NVACC_PITCH0 0x00400670 -#define NVACC_PITCH1 0x00400674 -#define NVACC_PITCH2 0x00400678 -#define NVACC_PITCH3 0x0040067c -#define NVACC_PITCH4 0x00400680 -#define NVACC_BLIMIT0 0x00400684 -#define NVACC_BLIMIT1 0x00400688 -#define NVACC_BLIMIT2 0x0040068c -#define NVACC_BLIMIT3 0x00400690 -#define NVACC_NV10_BLIMIT4 0x00400694 -#define NVACC_NV10_BLIMIT5 0x00400698 -#define NVACC_BPIXEL 0x00400724 -#define NVACC_NV20_OFFSET0 0x00400820 -#define NVACC_NV20_OFFSET1 0x00400824 -#define NVACC_NV20_OFFSET2 0x00400828 -#define NVACC_NV20_OFFSET3 0x0040082c -#define NVACC_STRD_FMT 0x00400830 -#define NVACC_NV20_PITCH0 0x00400850 -#define NVACC_NV20_PITCH1 0x00400854 -#define NVACC_NV20_PITCH2 0x00400858 -#define NVACC_NV20_PITCH3 0x0040085c -#define NVACC_NV20_BLIMIT6 0x00400864 -#define NVACC_NV20_BLIMIT7 0x00400868 -#define NVACC_NV20_BLIMIT8 0x0040086c -#define NVACC_NV20_BLIMIT9 0x00400870 -#define NVACC_NV30_WHAT 0x00400890 +#define ENACC_FORMATS 0x00400618 +#define ENACC_OFFSET0 0x00400640 +#define ENACC_OFFSET1 0x00400644 +#define ENACC_OFFSET2 0x00400648 +#define ENACC_OFFSET3 0x0040064c +#define ENACC_OFFSET4 0x00400650 +#define ENACC_OFFSET5 0x00400654 +#define ENACC_BBASE0 0x00400658 +#define ENACC_BBASE1 0x0040065c +#define ENACC_BBASE2 0x00400660 +#define ENACC_BBASE3 0x00400664 +#define ENACC_NV10_BBASE4 0x00400668 +#define ENACC_NV10_BBASE5 0x0040066c +#define ENACC_PITCH0 0x00400670 +#define ENACC_PITCH1 0x00400674 +#define ENACC_PITCH2 0x00400678 +#define ENACC_PITCH3 0x0040067c +#define ENACC_PITCH4 0x00400680 +#define ENACC_BLIMIT0 0x00400684 +#define ENACC_BLIMIT1 0x00400688 +#define ENACC_BLIMIT2 0x0040068c +#define ENACC_BLIMIT3 0x00400690 +#define ENACC_NV10_BLIMIT4 0x00400694 +#define ENACC_NV10_BLIMIT5 0x00400698 +#define ENACC_BPIXEL 0x00400724 +#define ENACC_NV20_OFFSET0 0x00400820 +#define ENACC_NV20_OFFSET1 0x00400824 +#define ENACC_NV20_OFFSET2 0x00400828 +#define ENACC_NV20_OFFSET3 0x0040082c +#define ENACC_STRD_FMT 0x00400830 +#define ENACC_NV20_PITCH0 0x00400850 +#define ENACC_NV20_PITCH1 0x00400854 +#define ENACC_NV20_PITCH2 0x00400858 +#define ENACC_NV20_PITCH3 0x0040085c +#define ENACC_NV20_BLIMIT6 0x00400864 +#define ENACC_NV20_BLIMIT7 0x00400868 +#define ENACC_NV20_BLIMIT8 0x0040086c +#define ENACC_NV20_BLIMIT9 0x00400870 +#define ENACC_NV30_WHAT 0x00400890 /* specials */ -#define NVACC_DEBUG0 0x00400080 -#define NVACC_DEBUG1 0x00400084 -#define NVACC_DEBUG2 0x00400088 -#define NVACC_DEBUG3 0x0040008c -#define NVACC_NV10_DEBUG4 0x00400090 -#define NVACC_ACC_INTS 0x00400100 -#define NVACC_ACC_INTE 0x00400140 -#define NVACC_NV10_CTX_CTRL 0x00400144 -#define NVACC_STATUS 0x00400700 -#define NVACC_NV04_SURF_TYP 0x0040070c -#define NVACC_NV10_SURF_TYP 0x00400710 -#define NVACC_NV04_ACC_STAT 0x00400710 -#define NVACC_NV10_ACC_STAT 0x00400714 -#define NVACC_FIFO_EN 0x00400720 -#define NVACC_PAT_SHP 0x00400810 -#define NVACC_NV10_XFMOD0 0x00400f40 -#define NVACC_NV10_XFMOD1 0x00400f44 -#define NVACC_NV10_PIPEADR 0x00400f50 -#define NVACC_NV10_PIPEDAT 0x00400f54 +#define ENACC_DEBUG0 0x00400080 +#define ENACC_DEBUG1 0x00400084 +#define ENACC_DEBUG2 0x00400088 +#define ENACC_DEBUG3 0x0040008c +#define ENACC_NV10_DEBUG4 0x00400090 +#define ENACC_ACC_INTS 0x00400100 +#define ENACC_ACC_INTE 0x00400140 +#define ENACC_NV10_CTX_CTRL 0x00400144 +#define ENACC_STATUS 0x00400700 +#define ENACC_NV04_SURF_TYP 0x0040070c +#define ENACC_NV10_SURF_TYP 0x00400710 +#define ENACC_NV04_ACC_STAT 0x00400710 +#define ENACC_NV10_ACC_STAT 0x00400714 +#define ENACC_FIFO_EN 0x00400720 +#define ENACC_PAT_SHP 0x00400810 +#define ENACC_NV10_XFMOD0 0x00400f40 +#define ENACC_NV10_XFMOD1 0x00400f44 +#define ENACC_NV10_PIPEADR 0x00400f50 +#define ENACC_NV10_PIPEDAT 0x00400f54 /* PGRAPH cache registers */ -#define NVACC_CACHE1_1 0x00400160 -#define NVACC_CACHE1_2 0x00400180 -#define NVACC_CACHE1_3 0x004001a0 -#define NVACC_CACHE1_4 0x004001c0 -#define NVACC_CACHE1_5 0x004001e0 -#define NVACC_CACHE2_1 0x00400164 -#define NVACC_CACHE2_2 0x00400184 -#define NVACC_CACHE2_3 0x004001a4 -#define NVACC_CACHE2_4 0x004001c4 -#define NVACC_CACHE2_5 0x004001e4 -#define NVACC_CACHE3_1 0x00400168 -#define NVACC_CACHE3_2 0x00400188 -#define NVACC_CACHE3_3 0x004001a8 -#define NVACC_CACHE3_4 0x004001c8 -#define NVACC_CACHE3_5 0x004001e8 -#define NVACC_CACHE4_1 0x0040016c -#define NVACC_CACHE4_2 0x0040018c -#define NVACC_CACHE4_3 0x004001ac -#define NVACC_CACHE4_4 0x004001cc -#define NVACC_CACHE4_5 0x004001ec -#define NVACC_NV10_CACHE5_1 0x00400170 -#define NVACC_NV04_CTX_CTRL 0x00400170 -#define NVACC_CACHE5_2 0x00400190 -#define NVACC_CACHE5_3 0x004001b0 -#define NVACC_CACHE5_4 0x004001d0 -#define NVACC_CACHE5_5 0x004001f0 -#define NVACC_NV10_CACHE6_1 0x00400174 -#define NVACC_CACHE6_2 0x00400194 -#define NVACC_CACHE6_3 0x004001b4 -#define NVACC_CACHE6_4 0x004001d4 -#define NVACC_CACHE6_5 0x004001f4 -#define NVACC_NV10_CACHE7_1 0x00400178 -#define NVACC_CACHE7_2 0x00400198 -#define NVACC_CACHE7_3 0x004001b8 -#define NVACC_CACHE7_4 0x004001d8 -#define NVACC_CACHE7_5 0x004001f8 -#define NVACC_NV10_CACHE8_1 0x0040017c -#define NVACC_CACHE8_2 0x0040019c -#define NVACC_CACHE8_3 0x004001bc -#define NVACC_CACHE8_4 0x004001dc -#define NVACC_CACHE8_5 0x004001fc -#define NVACC_NV10_CTX_SW1 0x0040014c -#define NVACC_NV10_CTX_SW2 0x00400150 -#define NVACC_NV10_CTX_SW3 0x00400154 -#define NVACC_NV10_CTX_SW4 0x00400158 -#define NVACC_NV10_CTX_SW5 0x0040015c +#define ENACC_CACHE1_1 0x00400160 +#define ENACC_CACHE1_2 0x00400180 +#define ENACC_CACHE1_3 0x004001a0 +#define ENACC_CACHE1_4 0x004001c0 +#define ENACC_CACHE1_5 0x004001e0 +#define ENACC_CACHE2_1 0x00400164 +#define ENACC_CACHE2_2 0x00400184 +#define ENACC_CACHE2_3 0x004001a4 +#define ENACC_CACHE2_4 0x004001c4 +#define ENACC_CACHE2_5 0x004001e4 +#define ENACC_CACHE3_1 0x00400168 +#define ENACC_CACHE3_2 0x00400188 +#define ENACC_CACHE3_3 0x004001a8 +#define ENACC_CACHE3_4 0x004001c8 +#define ENACC_CACHE3_5 0x004001e8 +#define ENACC_CACHE4_1 0x0040016c +#define ENACC_CACHE4_2 0x0040018c +#define ENACC_CACHE4_3 0x004001ac +#define ENACC_CACHE4_4 0x004001cc +#define ENACC_CACHE4_5 0x004001ec +#define ENACC_NV10_CACHE5_1 0x00400170 +#define ENACC_NV04_CTX_CTRL 0x00400170 +#define ENACC_CACHE5_2 0x00400190 +#define ENACC_CACHE5_3 0x004001b0 +#define ENACC_CACHE5_4 0x004001d0 +#define ENACC_CACHE5_5 0x004001f0 +#define ENACC_NV10_CACHE6_1 0x00400174 +#define ENACC_CACHE6_2 0x00400194 +#define ENACC_CACHE6_3 0x004001b4 +#define ENACC_CACHE6_4 0x004001d4 +#define ENACC_CACHE6_5 0x004001f4 +#define ENACC_NV10_CACHE7_1 0x00400178 +#define ENACC_CACHE7_2 0x00400198 +#define ENACC_CACHE7_3 0x004001b8 +#define ENACC_CACHE7_4 0x004001d8 +#define ENACC_CACHE7_5 0x004001f8 +#define ENACC_NV10_CACHE8_1 0x0040017c +#define ENACC_CACHE8_2 0x0040019c +#define ENACC_CACHE8_3 0x004001bc +#define ENACC_CACHE8_4 0x004001dc +#define ENACC_CACHE8_5 0x004001fc +#define ENACC_NV10_CTX_SW1 0x0040014c +#define ENACC_NV10_CTX_SW2 0x00400150 +#define ENACC_NV10_CTX_SW3 0x00400154 +#define ENACC_NV10_CTX_SW4 0x00400158 +#define ENACC_NV10_CTX_SW5 0x0040015c /* engine tile registers src */ -#define NVACC_NV20_FBWHAT0 0x00100200 -#define NVACC_NV20_FBWHAT1 0x00100204 -#define NVACC_NV10_FBTIL0AD 0x00100240 -#define NVACC_NV10_FBTIL0ED 0x00100244 -#define NVACC_NV10_FBTIL0PT 0x00100248 -#define NVACC_NV10_FBTIL0ST 0x0010024c -#define NVACC_NV10_FBTIL1AD 0x00100250 -#define NVACC_NV10_FBTIL1ED 0x00100254 -#define NVACC_NV10_FBTIL1PT 0x00100258 -#define NVACC_NV10_FBTIL1ST 0x0010025c -#define NVACC_NV10_FBTIL2AD 0x00100260 -#define NVACC_NV10_FBTIL2ED 0x00100264 -#define NVACC_NV10_FBTIL2PT 0x00100268 -#define NVACC_NV10_FBTIL2ST 0x0010026c -#define NVACC_NV10_FBTIL3AD 0x00100270 -#define NVACC_NV10_FBTIL3ED 0x00100274 -#define NVACC_NV10_FBTIL3PT 0x00100278 -#define NVACC_NV10_FBTIL3ST 0x0010027c -#define NVACC_NV10_FBTIL4AD 0x00100280 -#define NVACC_NV10_FBTIL4ED 0x00100284 -#define NVACC_NV10_FBTIL4PT 0x00100288 -#define NVACC_NV10_FBTIL4ST 0x0010028c -#define NVACC_NV10_FBTIL5AD 0x00100290 -#define NVACC_NV10_FBTIL5ED 0x00100294 -#define NVACC_NV10_FBTIL5PT 0x00100298 -#define NVACC_NV10_FBTIL5ST 0x0010029c -#define NVACC_NV10_FBTIL6AD 0x001002a0 -#define NVACC_NV10_FBTIL6ED 0x001002a4 -#define NVACC_NV10_FBTIL6PT 0x001002a8 -#define NVACC_NV10_FBTIL6ST 0x001002ac -#define NVACC_NV10_FBTIL7AD 0x001002b0 -#define NVACC_NV10_FBTIL7ED 0x001002b4 -#define NVACC_NV10_FBTIL7PT 0x001002b8 -#define NVACC_NV10_FBTIL7ST 0x001002bc +#define ENACC_NV20_FBWHAT0 0x00100200 +#define ENACC_NV20_FBWHAT1 0x00100204 +#define ENACC_NV10_FBTIL0AD 0x00100240 +#define ENACC_NV10_FBTIL0ED 0x00100244 +#define ENACC_NV10_FBTIL0PT 0x00100248 +#define ENACC_NV10_FBTIL0ST 0x0010024c +#define ENACC_NV10_FBTIL1AD 0x00100250 +#define ENACC_NV10_FBTIL1ED 0x00100254 +#define ENACC_NV10_FBTIL1PT 0x00100258 +#define ENACC_NV10_FBTIL1ST 0x0010025c +#define ENACC_NV10_FBTIL2AD 0x00100260 +#define ENACC_NV10_FBTIL2ED 0x00100264 +#define ENACC_NV10_FBTIL2PT 0x00100268 +#define ENACC_NV10_FBTIL2ST 0x0010026c +#define ENACC_NV10_FBTIL3AD 0x00100270 +#define ENACC_NV10_FBTIL3ED 0x00100274 +#define ENACC_NV10_FBTIL3PT 0x00100278 +#define ENACC_NV10_FBTIL3ST 0x0010027c +#define ENACC_NV10_FBTIL4AD 0x00100280 +#define ENACC_NV10_FBTIL4ED 0x00100284 +#define ENACC_NV10_FBTIL4PT 0x00100288 +#define ENACC_NV10_FBTIL4ST 0x0010028c +#define ENACC_NV10_FBTIL5AD 0x00100290 +#define ENACC_NV10_FBTIL5ED 0x00100294 +#define ENACC_NV10_FBTIL5PT 0x00100298 +#define ENACC_NV10_FBTIL5ST 0x0010029c +#define ENACC_NV10_FBTIL6AD 0x001002a0 +#define ENACC_NV10_FBTIL6ED 0x001002a4 +#define ENACC_NV10_FBTIL6PT 0x001002a8 +#define ENACC_NV10_FBTIL6ST 0x001002ac +#define ENACC_NV10_FBTIL7AD 0x001002b0 +#define ENACC_NV10_FBTIL7ED 0x001002b4 +#define ENACC_NV10_FBTIL7PT 0x001002b8 +#define ENACC_NV10_FBTIL7ST 0x001002bc /* engine tile registers dst */ -#define NVACC_NV20_WHAT0 0x004009a4 -#define NVACC_NV20_WHAT1 0x004009a8 -#define NVACC_NV10_TIL0AD 0x00400b00 -#define NVACC_NV10_TIL0ED 0x00400b04 -#define NVACC_NV10_TIL0PT 0x00400b08 -#define NVACC_NV10_TIL0ST 0x00400b0c -#define NVACC_NV10_TIL1AD 0x00400b10 -#define NVACC_NV10_TIL1ED 0x00400b14 -#define NVACC_NV10_TIL1PT 0x00400b18 -#define NVACC_NV10_TIL1ST 0x00400b1c -#define NVACC_NV10_TIL2AD 0x00400b20 -#define NVACC_NV10_TIL2ED 0x00400b24 -#define NVACC_NV10_TIL2PT 0x00400b28 -#define NVACC_NV10_TIL2ST 0x00400b2c -#define NVACC_NV10_TIL3AD 0x00400b30 -#define NVACC_NV10_TIL3ED 0x00400b34 -#define NVACC_NV10_TIL3PT 0x00400b38 -#define NVACC_NV10_TIL3ST 0x00400b3c -#define NVACC_NV10_TIL4AD 0x00400b40 -#define NVACC_NV10_TIL4ED 0x00400b44 -#define NVACC_NV10_TIL4PT 0x00400b48 -#define NVACC_NV10_TIL4ST 0x00400b4c -#define NVACC_NV10_TIL5AD 0x00400b50 -#define NVACC_NV10_TIL5ED 0x00400b54 -#define NVACC_NV10_TIL5PT 0x00400b58 -#define NVACC_NV10_TIL5ST 0x00400b5c -#define NVACC_NV10_TIL6AD 0x00400b60 -#define NVACC_NV10_TIL6ED 0x00400b64 -#define NVACC_NV10_TIL6PT 0x00400b68 -#define NVACC_NV10_TIL6ST 0x00400b6c -#define NVACC_NV10_TIL7AD 0x00400b70 -#define NVACC_NV10_TIL7ED 0x00400b74 -#define NVACC_NV10_TIL7PT 0x00400b78 -#define NVACC_NV10_TIL7ST 0x00400b7c +#define ENACC_NV20_WHAT0 0x004009a4 +#define ENACC_NV20_WHAT1 0x004009a8 +#define ENACC_NV10_TIL0AD 0x00400b00 +#define ENACC_NV10_TIL0ED 0x00400b04 +#define ENACC_NV10_TIL0PT 0x00400b08 +#define ENACC_NV10_TIL0ST 0x00400b0c +#define ENACC_NV10_TIL1AD 0x00400b10 +#define ENACC_NV10_TIL1ED 0x00400b14 +#define ENACC_NV10_TIL1PT 0x00400b18 +#define ENACC_NV10_TIL1ST 0x00400b1c +#define ENACC_NV10_TIL2AD 0x00400b20 +#define ENACC_NV10_TIL2ED 0x00400b24 +#define ENACC_NV10_TIL2PT 0x00400b28 +#define ENACC_NV10_TIL2ST 0x00400b2c +#define ENACC_NV10_TIL3AD 0x00400b30 +#define ENACC_NV10_TIL3ED 0x00400b34 +#define ENACC_NV10_TIL3PT 0x00400b38 +#define ENACC_NV10_TIL3ST 0x00400b3c +#define ENACC_NV10_TIL4AD 0x00400b40 +#define ENACC_NV10_TIL4ED 0x00400b44 +#define ENACC_NV10_TIL4PT 0x00400b48 +#define ENACC_NV10_TIL4ST 0x00400b4c +#define ENACC_NV10_TIL5AD 0x00400b50 +#define ENACC_NV10_TIL5ED 0x00400b54 +#define ENACC_NV10_TIL5PT 0x00400b58 +#define ENACC_NV10_TIL5ST 0x00400b5c +#define ENACC_NV10_TIL6AD 0x00400b60 +#define ENACC_NV10_TIL6ED 0x00400b64 +#define ENACC_NV10_TIL6PT 0x00400b68 +#define ENACC_NV10_TIL6ST 0x00400b6c +#define ENACC_NV10_TIL7AD 0x00400b70 +#define ENACC_NV10_TIL7ED 0x00400b74 +#define ENACC_NV10_TIL7PT 0x00400b78 +#define ENACC_NV10_TIL7ST 0x00400b7c /* cache setup registers */ -#define NVACC_PF_INTSTAT 0x00002100 -#define NVACC_PF_INTEN 0x00002140 -#define NVACC_PF_RAMHT 0x00002210 -#define NVACC_PF_RAMFC 0x00002214 -#define NVACC_PF_RAMRO 0x00002218 -#define NVACC_PF_CACHES 0x00002500 -#define NVACC_PF_SIZE 0x0000250c -#define NVACC_PF_CACH0_PSH0 0x00003000 -#define NVACC_PF_CACH0_PUL0 0x00003050 -#define NVACC_PF_CACH0_PUL1 0x00003054 -#define NVACC_PF_CACH1_PSH0 0x00003200 -#define NVACC_PF_CACH1_PSH1 0x00003204 -#define NVACC_PF_CACH1_DMAI 0x0000322c -#define NVACC_PF_CACH1_PUL0 0x00003250 -#define NVACC_PF_CACH1_PUL1 0x00003254 -#define NVACC_PF_CACH1_HASH 0x00003258 +#define ENACC_PF_INTSTAT 0x00002100 +#define ENACC_PF_INTEN 0x00002140 +#define ENACC_PF_RAMHT 0x00002210 +#define ENACC_PF_RAMFC 0x00002214 +#define ENACC_PF_RAMRO 0x00002218 +#define ENACC_PF_CACHES 0x00002500 +#define ENACC_PF_SIZE 0x0000250c +#define ENACC_PF_CACH0_PSH0 0x00003000 +#define ENACC_PF_CACH0_PUL0 0x00003050 +#define ENACC_PF_CACH0_PUL1 0x00003054 +#define ENACC_PF_CACH1_PSH0 0x00003200 +#define ENACC_PF_CACH1_PSH1 0x00003204 +#define ENACC_PF_CACH1_DMAI 0x0000322c +#define ENACC_PF_CACH1_PUL0 0x00003250 +#define ENACC_PF_CACH1_PUL1 0x00003254 +#define ENACC_PF_CACH1_HASH 0x00003258 /* Ptimer registers */ -#define NVACC_PT_INTSTAT 0x00009100 -#define NVACC_PT_INTEN 0x00009140 -#define NVACC_PT_NUMERATOR 0x00009200 -#define NVACC_PT_DENOMINATR 0x00009210 +#define ENACC_PT_INTSTAT 0x00009100 +#define ENACC_PT_INTEN 0x00009140 +#define ENACC_PT_NUMERATOR 0x00009200 +#define ENACC_PT_DENOMINATR 0x00009210 /* used PRAMIN registers */ -#define NVACC_PR_CTX0_R 0x00711400 -#define NVACC_PR_CTX1_R 0x00711404 -#define NVACC_PR_CTX2_R 0x00711408 -#define NVACC_PR_CTX3_R 0x0071140c -#define NVACC_PR_CTX0_0 0x00711420 -#define NVACC_PR_CTX1_0 0x00711424 -#define NVACC_PR_CTX2_0 0x00711428 -#define NVACC_PR_CTX3_0 0x0071142c -#define NVACC_PR_CTX0_1 0x00711430 -#define NVACC_PR_CTX1_1 0x00711434 -#define NVACC_PR_CTX2_1 0x00711438 -#define NVACC_PR_CTX3_1 0x0071143c -#define NVACC_PR_CTX0_2 0x00711440 -#define NVACC_PR_CTX1_2 0x00711444 -#define NVACC_PR_CTX2_2 0x00711448 -#define NVACC_PR_CTX3_2 0x0071144c -#define NVACC_PR_CTX0_3 0x00711450 -#define NVACC_PR_CTX1_3 0x00711454 -#define NVACC_PR_CTX2_3 0x00711458 -#define NVACC_PR_CTX3_3 0x0071145c -#define NVACC_PR_CTX0_4 0x00711460 -#define NVACC_PR_CTX1_4 0x00711464 -#define NVACC_PR_CTX2_4 0x00711468 -#define NVACC_PR_CTX3_4 0x0071146c -#define NVACC_PR_CTX0_5 0x00711470 -#define NVACC_PR_CTX1_5 0x00711474 -#define NVACC_PR_CTX2_5 0x00711478 -#define NVACC_PR_CTX3_5 0x0071147c -#define NVACC_PR_CTX0_6 0x00711480 -#define NVACC_PR_CTX1_6 0x00711484 -#define NVACC_PR_CTX2_6 0x00711488 -#define NVACC_PR_CTX3_6 0x0071148c -#define NVACC_PR_CTX0_7 0x00711490 -#define NVACC_PR_CTX1_7 0x00711494 -#define NVACC_PR_CTX2_7 0x00711498 -#define NVACC_PR_CTX3_7 0x0071149c -#define NVACC_PR_CTX0_8 0x007114a0 -#define NVACC_PR_CTX1_8 0x007114a4 -#define NVACC_PR_CTX2_8 0x007114a8 -#define NVACC_PR_CTX3_8 0x007114ac -#define NVACC_PR_CTX0_9 0x007114b0 -#define NVACC_PR_CTX1_9 0x007114b4 -#define NVACC_PR_CTX2_9 0x007114b8 -#define NVACC_PR_CTX3_9 0x007114bc -#define NVACC_PR_CTX0_A 0x007114c0 -#define NVACC_PR_CTX1_A 0x007114c4 /* not used */ -#define NVACC_PR_CTX2_A 0x007114c8 -#define NVACC_PR_CTX3_A 0x007114cc -#define NVACC_PR_CTX0_B 0x007114d0 -#define NVACC_PR_CTX1_B 0x007114d4 -#define NVACC_PR_CTX2_B 0x007114d8 -#define NVACC_PR_CTX3_B 0x007114dc -#define NVACC_PR_CTX0_C 0x007114e0 -#define NVACC_PR_CTX1_C 0x007114e4 -#define NVACC_PR_CTX2_C 0x007114e8 -#define NVACC_PR_CTX3_C 0x007114ec -#define NVACC_PR_CTX0_D 0x007114f0 -#define NVACC_PR_CTX1_D 0x007114f4 -#define NVACC_PR_CTX2_D 0x007114f8 -#define NVACC_PR_CTX3_D 0x007114fc -#define NVACC_PR_CTX0_E 0x00711500 -#define NVACC_PR_CTX1_E 0x00711504 -#define NVACC_PR_CTX2_E 0x00711508 -#define NVACC_PR_CTX3_E 0x0071150c +#define ENACC_PR_CTX0_R 0x00711400 +#define ENACC_PR_CTX1_R 0x00711404 +#define ENACC_PR_CTX2_R 0x00711408 +#define ENACC_PR_CTX3_R 0x0071140c +#define ENACC_PR_CTX0_0 0x00711420 +#define ENACC_PR_CTX1_0 0x00711424 +#define ENACC_PR_CTX2_0 0x00711428 +#define ENACC_PR_CTX3_0 0x0071142c +#define ENACC_PR_CTX0_1 0x00711430 +#define ENACC_PR_CTX1_1 0x00711434 +#define ENACC_PR_CTX2_1 0x00711438 +#define ENACC_PR_CTX3_1 0x0071143c +#define ENACC_PR_CTX0_2 0x00711440 +#define ENACC_PR_CTX1_2 0x00711444 +#define ENACC_PR_CTX2_2 0x00711448 +#define ENACC_PR_CTX3_2 0x0071144c +#define ENACC_PR_CTX0_3 0x00711450 +#define ENACC_PR_CTX1_3 0x00711454 +#define ENACC_PR_CTX2_3 0x00711458 +#define ENACC_PR_CTX3_3 0x0071145c +#define ENACC_PR_CTX0_4 0x00711460 +#define ENACC_PR_CTX1_4 0x00711464 +#define ENACC_PR_CTX2_4 0x00711468 +#define ENACC_PR_CTX3_4 0x0071146c +#define ENACC_PR_CTX0_5 0x00711470 +#define ENACC_PR_CTX1_5 0x00711474 +#define ENACC_PR_CTX2_5 0x00711478 +#define ENACC_PR_CTX3_5 0x0071147c +#define ENACC_PR_CTX0_6 0x00711480 +#define ENACC_PR_CTX1_6 0x00711484 +#define ENACC_PR_CTX2_6 0x00711488 +#define ENACC_PR_CTX3_6 0x0071148c +#define ENACC_PR_CTX0_7 0x00711490 +#define ENACC_PR_CTX1_7 0x00711494 +#define ENACC_PR_CTX2_7 0x00711498 +#define ENACC_PR_CTX3_7 0x0071149c +#define ENACC_PR_CTX0_8 0x007114a0 +#define ENACC_PR_CTX1_8 0x007114a4 +#define ENACC_PR_CTX2_8 0x007114a8 +#define ENACC_PR_CTX3_8 0x007114ac +#define ENACC_PR_CTX0_9 0x007114b0 +#define ENACC_PR_CTX1_9 0x007114b4 +#define ENACC_PR_CTX2_9 0x007114b8 +#define ENACC_PR_CTX3_9 0x007114bc +#define ENACC_PR_CTX0_A 0x007114c0 +#define ENACC_PR_CTX1_A 0x007114c4 /* not used */ +#define ENACC_PR_CTX2_A 0x007114c8 +#define ENACC_PR_CTX3_A 0x007114cc +#define ENACC_PR_CTX0_B 0x007114d0 +#define ENACC_PR_CTX1_B 0x007114d4 +#define ENACC_PR_CTX2_B 0x007114d8 +#define ENACC_PR_CTX3_B 0x007114dc +#define ENACC_PR_CTX0_C 0x007114e0 +#define ENACC_PR_CTX1_C 0x007114e4 +#define ENACC_PR_CTX2_C 0x007114e8 +#define ENACC_PR_CTX3_C 0x007114ec +#define ENACC_PR_CTX0_D 0x007114f0 +#define ENACC_PR_CTX1_D 0x007114f4 +#define ENACC_PR_CTX2_D 0x007114f8 +#define ENACC_PR_CTX3_D 0x007114fc +#define ENACC_PR_CTX0_E 0x00711500 +#define ENACC_PR_CTX1_E 0x00711504 +#define ENACC_PR_CTX2_E 0x00711508 +#define ENACC_PR_CTX3_E 0x0071150c /* used RAMHT registers (hash-table(?)) */ -#define NVACC_HT_HANDL_00 0x00710000 -#define NVACC_HT_VALUE_00 0x00710004 -#define NVACC_HT_HANDL_01 0x00710008 -#define NVACC_HT_VALUE_01 0x0071000c -#define NVACC_HT_HANDL_02 0x00710010 -#define NVACC_HT_VALUE_02 0x00710014 -#define NVACC_HT_HANDL_03 0x00710018 -#define NVACC_HT_VALUE_03 0x0071001c -#define NVACC_HT_HANDL_04 0x00710020 -#define NVACC_HT_VALUE_04 0x00710024 -#define NVACC_HT_HANDL_05 0x00710028 -#define NVACC_HT_VALUE_05 0x0071002c -#define NVACC_HT_HANDL_06 0x00710030 -#define NVACC_HT_VALUE_06 0x00710034 -#define NVACC_HT_HANDL_10 0x00710080 -#define NVACC_HT_VALUE_10 0x00710084 -#define NVACC_HT_HANDL_11 0x00710088 -#define NVACC_HT_VALUE_11 0x0071008c -#define NVACC_HT_HANDL_12 0x00710090 -#define NVACC_HT_VALUE_12 0x00710094 -#define NVACC_HT_HANDL_13 0x00710098 -#define NVACC_HT_VALUE_13 0x0071009c -#define NVACC_HT_HANDL_14 0x007100a0 -#define NVACC_HT_VALUE_14 0x007100a4 -#define NVACC_HT_HANDL_15 0x007100a8 -#define NVACC_HT_VALUE_15 0x007100ac -#define NVACC_HT_HANDL_16 0x007100b0 -#define NVACC_HT_VALUE_16 0x007100b4 -#define NVACC_HT_HANDL_17 0x007100b8 -#define NVACC_HT_VALUE_17 0x007100bc +#define ENACC_HT_HANDL_00 0x00710000 +#define ENACC_HT_VALUE_00 0x00710004 +#define ENACC_HT_HANDL_01 0x00710008 +#define ENACC_HT_VALUE_01 0x0071000c +#define ENACC_HT_HANDL_02 0x00710010 +#define ENACC_HT_VALUE_02 0x00710014 +#define ENACC_HT_HANDL_03 0x00710018 +#define ENACC_HT_VALUE_03 0x0071001c +#define ENACC_HT_HANDL_04 0x00710020 +#define ENACC_HT_VALUE_04 0x00710024 +#define ENACC_HT_HANDL_05 0x00710028 +#define ENACC_HT_VALUE_05 0x0071002c +#define ENACC_HT_HANDL_06 0x00710030 +#define ENACC_HT_VALUE_06 0x00710034 +#define ENACC_HT_HANDL_10 0x00710080 +#define ENACC_HT_VALUE_10 0x00710084 +#define ENACC_HT_HANDL_11 0x00710088 +#define ENACC_HT_VALUE_11 0x0071008c +#define ENACC_HT_HANDL_12 0x00710090 +#define ENACC_HT_VALUE_12 0x00710094 +#define ENACC_HT_HANDL_13 0x00710098 +#define ENACC_HT_VALUE_13 0x0071009c +#define ENACC_HT_HANDL_14 0x007100a0 +#define ENACC_HT_VALUE_14 0x007100a4 +#define ENACC_HT_HANDL_15 0x007100a8 +#define ENACC_HT_VALUE_15 0x007100ac +#define ENACC_HT_HANDL_16 0x007100b0 +#define ENACC_HT_VALUE_16 0x007100b4 +#define ENACC_HT_HANDL_17 0x007100b8 +#define ENACC_HT_VALUE_17 0x007100bc /* acc engine fifo setup registers (for function_register 'mappings') */ -#define NVACC_FIFO_00800000 0x00800000 -#define NVACC_FIFO_00802000 0x00802000 -#define NVACC_FIFO_00804000 0x00804000 -#define NVACC_FIFO_00806000 0x00806000 -#define NVACC_FIFO_00808000 0x00808000 -#define NVACC_FIFO_0080a000 0x0080a000 -#define NVACC_FIFO_0080c000 0x0080c000 -#define NVACC_FIFO_0080e000 0x0080e000 +#define ENACC_FIFO_00800000 0x00800000 +#define ENACC_FIFO_00802000 0x00802000 +#define ENACC_FIFO_00804000 0x00804000 +#define ENACC_FIFO_00806000 0x00806000 +#define ENACC_FIFO_00808000 0x00808000 +#define ENACC_FIFO_0080a000 0x0080a000 +#define ENACC_FIFO_0080c000 0x0080c000 +#define ENACC_FIFO_0080e000 0x0080e000 /* ROP3 registers (Raster OPeration) */ -#define NV16_ROP_FIFOFREE 0x00800010 /* little endian */ -#define NVACC_ROP_ROP3 0x00800300 /* 'mapped' from 0x00420300 */ +#define RG16_ROP_FIFOFREE 0x00800010 /* little endian */ +#define ENACC_ROP_ROP3 0x00800300 /* 'mapped' from 0x00420300 */ /* clip registers */ -#define NV16_CLP_FIFOFREE 0x00802010 /* little endian */ -#define NVACC_CLP_TOPLEFT 0x00802300 /* 'mapped' from 0x00450300 */ -#define NVACC_CLP_WIDHEIGHT 0x00802304 /* 'mapped' from 0x00450304 */ +#define RG16_CLP_FIFOFREE 0x00802010 /* little endian */ +#define ENACC_CLP_TOPLEFT 0x00802300 /* 'mapped' from 0x00450300 */ +#define ENACC_CLP_WIDHEIGHT 0x00802304 /* 'mapped' from 0x00450304 */ /* pattern registers */ -#define NV16_PAT_FIFOFREE 0x00804010 /* little endian */ -#define NVACC_PAT_SHAPE 0x00804308 /* 'mapped' from 0x00460308 */ -#define NVACC_PAT_COLOR0 0x00804310 /* 'mapped' from 0x00460310 */ -#define NVACC_PAT_COLOR1 0x00804314 /* 'mapped' from 0x00460314 */ -#define NVACC_PAT_MONO1 0x00804318 /* 'mapped' from 0x00460318 */ -#define NVACC_PAT_MONO2 0x0080431c /* 'mapped' from 0x0046031c */ +#define RG16_PAT_FIFOFREE 0x00804010 /* little endian */ +#define ENACC_PAT_SHAPE 0x00804308 /* 'mapped' from 0x00460308 */ +#define ENACC_PAT_COLOR0 0x00804310 /* 'mapped' from 0x00460310 */ +#define ENACC_PAT_COLOR1 0x00804314 /* 'mapped' from 0x00460314 */ +#define ENACC_PAT_MONO1 0x00804318 /* 'mapped' from 0x00460318 */ +#define ENACC_PAT_MONO2 0x0080431c /* 'mapped' from 0x0046031c */ /* blit registers */ -#define NV16_BLT_FIFOFREE 0x00808010 /* little endian */ -#define NVACC_BLT_TOPLFTSRC 0x00808300 /* 'mapped' from 0x00500300 */ -#define NVACC_BLT_TOPLFTDST 0x00808304 /* 'mapped' from 0x00500304 */ -#define NVACC_BLT_SIZE 0x00808308 /* 'mapped' from 0x00500308 */ +#define RG16_BLT_FIFOFREE 0x00808010 /* little endian */ +#define ENACC_BLT_TOPLFTSRC 0x00808300 /* 'mapped' from 0x00500300 */ +#define ENACC_BLT_TOPLFTDST 0x00808304 /* 'mapped' from 0x00500304 */ +#define ENACC_BLT_SIZE 0x00808308 /* 'mapped' from 0x00500308 */ /* used bitmap registers */ -#define NV16_BMP_FIFOFREE 0x0080a010 /* little endian */ -#define NVACC_BMP_COLOR1A 0x0080a3fc /* 'mapped' from 0x006b03fc */ -#define NVACC_BMP_UCRECTL_0 0x0080a400 /* 'mapped' from 0x006b0400 */ -#define NVACC_BMP_UCRECSZ_0 0x0080a404 /* 'mapped' from 0x006b0404 */ +#define RG16_BMP_FIFOFREE 0x0080a010 /* little endian */ +#define ENACC_BMP_COLOR1A 0x0080a3fc /* 'mapped' from 0x006b03fc */ +#define ENACC_BMP_UCRECTL_0 0x0080a400 /* 'mapped' from 0x006b0400 */ +#define ENACC_BMP_UCRECSZ_0 0x0080a404 /* 'mapped' from 0x006b0404 */ -/* Nvidia PCI direct registers */ -#define NV32_PWRUPCTRL 0x00000200 -#define NV32_DUALHEAD_CTRL 0x000010f0//verify!!! -#define NV8_MISCW 0x000c03c2 -#define NV8_MISCR 0x000c03cc -#define NV8_VSE2 0x000c03c3 -#define NV8_SEQIND 0x000c03c4 -#define NV16_SEQIND 0x000c03c4 -#define NV8_SEQDAT 0x000c03c5 -#define NV8_GRPHIND 0x000c03ce -#define NV16_GRPHIND 0x000c03ce -#define NV8_GRPHDAT 0x000c03cf +/* PCI direct registers */ +#define RG32_PWRUPCTRL 0x00000200 +#define RG32_DUALHEAD_CTRL 0x000010f0//verify!!! +#define RG8_MISCW 0x000c03c2 +#define RG8_MISCR 0x000c03cc +#define RG8_VSE2 0x000c03c3 +#define RG8_SEQIND 0x000c03c4 +#define RG16_SEQIND 0x000c03c4 +#define RG8_SEQDAT 0x000c03c5 +#define RG8_GRPHIND 0x000c03ce +#define RG16_GRPHIND 0x000c03ce +#define RG8_GRPHDAT 0x000c03cf /* bootstrap info registers */ -#define NV32_NV4STRAPINFO 0x00100000 -#define NV32_PFB_CONFIG_0 0x00100200 -#define NV32_PFB_CONFIG_1 0x00100204 -#define NV32_NV10STRAPINFO 0x0010020c -#define NV32_FB_MRS1 0x001002c0 -#define NV32_FB_MRS2 0x001002c8 -#define NV32_NVSTRAPINFO2 0x00101000 +#define RG32_NV4STRAPINFO 0x00100000 +#define RG32_PFB_CONFIG_0 0x00100200 +#define RG32_PFB_CONFIG_1 0x00100204 +#define RG32_NV10STRAPINFO 0x0010020c +#define RG32_FB_MRS1 0x001002c0 +#define RG32_FB_MRS2 0x001002c8 +#define RG32_NVSTRAPINFO2 0x00101000 /* registers needed for 'coldstart' */ -#define NV32_PFB_DEBUG_0 0x00100080 -#define NV32_PFB_REFCTRL 0x00100210 -#define NV32_COREPLL 0x00680500 -#define NV32_MEMPLL 0x00680504 -#define NV32_PLL_CTRL 0x00680510 -#define NV32_COREPLL2 0x00680570 /* NV31, NV36 only */ -#define NV32_MEMPLL2 0x00680574 /* NV31, NV36 only */ -#define NV32_CONFIG 0x00600804 +#define RG32_PFB_DEBUG_0 0x00100080 +#define RG32_PFB_REFCTRL 0x00100210 +#define RG32_COREPLL 0x00680500 +#define RG32_MEMPLL 0x00680504 +#define RG32_PLL_CTRL 0x00680510 +#define RG32_COREPLL2 0x00680570 /* NV31, NV36 only */ +#define RG32_MEMPLL2 0x00680574 /* NV31, NV36 only */ +#define RG32_CONFIG 0x00600804 /* primary head */ -#define NV8_ATTRINDW 0x006013c0 -#define NV8_ATTRDATW 0x006013c0 -#define NV8_ATTRDATR 0x006013c1 -#define NV8_CRTCIND 0x006013d4 -#define NV16_CRTCIND 0x006013d4 -#define NV8_CRTCDAT 0x006013d5 -#define NV8_INSTAT1 0x006013da -#define NV32_NV10FBSTADD32 0x00600800 -#define NV32_RASTER 0x00600808 -#define NV32_NV10CURADD32 0x0060080c -#define NV32_CURCONF 0x00600810 -#define NV32_PANEL_PWR 0x0060081c -#define NV32_FUNCSEL 0x00600860 +#define RG8_ATTRINDW 0x006013c0 +#define RG8_ATTRDATW 0x006013c0 +#define RG8_ATTRDATR 0x006013c1 +#define RG8_CRTCIND 0x006013d4 +#define RG16_CRTCIND 0x006013d4 +#define RG8_CRTCDAT 0x006013d5 +#define RG8_INSTAT1 0x006013da +#define RG32_NV10FBSTADD32 0x00600800 +#define RG32_RASTER 0x00600808 +#define RG32_NV10CURADD32 0x0060080c +#define RG32_CURCONF 0x00600810 +#define RG32_PANEL_PWR 0x0060081c +#define RG32_FUNCSEL 0x00600860 /* secondary head */ -#define NV8_ATTR2INDW 0x006033c0 -#define NV8_ATTR2DATW 0x006033c0 -#define NV8_ATTR2DATR 0x006033c1 -#define NV8_CRTC2IND 0x006033d4 -#define NV16_CRTC2IND 0x006033d4 -#define NV8_CRTC2DAT 0x006033d5 -#define NV8_2INSTAT1 0x006033da//verify!!! -#define NV32_NV10FB2STADD32 0x00602800 -#define NV32_RASTER2 0x00602808 -#define NV32_NV10CUR2ADD32 0x0060280c -#define NV32_2CURCONF 0x00602810 -#define NV32_2PANEL_PWR 0x0060281c//verify!!! -#define NV32_2FUNCSEL 0x00602860 +#define RG8_ATTR2INDW 0x006033c0 +#define RG8_ATTR2DATW 0x006033c0 +#define RG8_ATTR2DATR 0x006033c1 +#define RG8_CRTC2IND 0x006033d4 +#define RG16_CRTC2IND 0x006033d4 +#define RG8_CRTC2DAT 0x006033d5 +#define RG8_2INSTAT1 0x006033da//verify!!! +#define RG32_NV10FB2STADD32 0x00602800 +#define RG32_RASTER2 0x00602808 +#define RG32_NV10CUR2ADD32 0x0060280c +#define RG32_2CURCONF 0x00602810 +#define RG32_2PANEL_PWR 0x0060281c//verify!!! +#define RG32_2FUNCSEL 0x00602860 -/* Nvidia DAC direct registers (standard VGA palette RAM registers) */ +/* DAC direct registers (standard VGA palette RAM registers) */ /* primary head */ -#define NV8_PALMASK 0x006813c6 -#define NV8_PALINDR 0x006813c7 -#define NV8_PALINDW 0x006813c8 -#define NV8_PALDATA 0x006813c9 +#define RG8_PALMASK 0x006813c6 +#define RG8_PALINDR 0x006813c7 +#define RG8_PALINDW 0x006813c8 +#define RG8_PALDATA 0x006813c9 /* secondary head */ -#define NV8_PAL2MASK 0x006833c6 -#define NV8_PAL2INDR 0x006833c7 -#define NV8_PAL2INDW 0x006833c8 -#define NV8_PAL2DATA 0x006833c9 +#define RG8_PAL2MASK 0x006833c6 +#define RG8_PAL2INDR 0x006833c7 +#define RG8_PAL2INDW 0x006833c8 +#define RG8_PAL2DATA 0x006833c9 -/* Nvidia PCI direct DAC registers (32bit) */ +/* PCI direct DAC registers (32bit) */ /* primary head */ -#define NVDAC_CURPOS 0x00680300 -#define NVDAC_PIXPLLC 0x00680508 -#define NVDAC_PLLSEL 0x0068050c -#define NVDAC_OUTPUT 0x0068052c -#define NVDAC_PIXPLLC2 0x00680578 -#define NVDAC_GENCTRL 0x00680600 -#define NVDAC_TSTCTRL 0x00680608 -#define NVDAC_TSTDATA 0x00680610 -#define NVDAC_TV_SETUP 0x00680700 +#define ENDAC_CURPOS 0x00680300 +#define ENDAC_PIXPLLC 0x00680508 +#define ENDAC_PLLSEL 0x0068050c +#define ENDAC_OUTPUT 0x0068052c +#define ENDAC_PIXPLLC2 0x00680578 +#define ENDAC_GENCTRL 0x00680600 +#define ENDAC_TSTCTRL 0x00680608 +#define ENDAC_TSTDATA 0x00680610 +#define ENDAC_TV_SETUP 0x00680700 /* (flatpanel registers: confirmed for TNT2 and up) */ -#define NVDAC_FP_VDISPEND 0x00680800 -#define NVDAC_FP_VTOTAL 0x00680804 -#define NVDAC_FP_VCRTC 0x00680808 -#define NVDAC_FP_VSYNC_S 0x0068080c -#define NVDAC_FP_VSYNC_E 0x00680810 -#define NVDAC_FP_VVALID_S 0x00680814 -#define NVDAC_FP_VVALID_E 0x00680818 -#define NVDAC_FP_HDISPEND 0x00680820 -#define NVDAC_FP_HTOTAL 0x00680824 -#define NVDAC_FP_HCRTC 0x00680828 -#define NVDAC_FP_HSYNC_S 0x0068082c -#define NVDAC_FP_HSYNC_E 0x00680830 -#define NVDAC_FP_HVALID_S 0x00680834 -#define NVDAC_FP_HVALID_E 0x00680838 -#define NVDAC_FP_CHKSUM 0x00680840 -#define NVDAC_FP_TST_CTRL 0x00680844 -#define NVDAC_FP_TG_CTRL 0x00680848 -#define NVDAC_FP_DEBUG0 0x00680880 -#define NVDAC_FP_DEBUG1 0x00680884 -#define NVDAC_FP_DEBUG2 0x00680888 -#define NVDAC_FP_DEBUG3 0x0068088c +#define ENDAC_FP_VDISPEND 0x00680800 +#define ENDAC_FP_VTOTAL 0x00680804 +#define ENDAC_FP_VCRTC 0x00680808 +#define ENDAC_FP_VSYNC_S 0x0068080c +#define ENDAC_FP_VSYNC_E 0x00680810 +#define ENDAC_FP_VVALID_S 0x00680814 +#define ENDAC_FP_VVALID_E 0x00680818 +#define ENDAC_FP_HDISPEND 0x00680820 +#define ENDAC_FP_HTOTAL 0x00680824 +#define ENDAC_FP_HCRTC 0x00680828 +#define ENDAC_FP_HSYNC_S 0x0068082c +#define ENDAC_FP_HSYNC_E 0x00680830 +#define ENDAC_FP_HVALID_S 0x00680834 +#define ENDAC_FP_HVALID_E 0x00680838 +#define ENDAC_FP_CHKSUM 0x00680840 +#define ENDAC_FP_TST_CTRL 0x00680844 +#define ENDAC_FP_TG_CTRL 0x00680848 +#define ENDAC_FP_DEBUG0 0x00680880 +#define ENDAC_FP_DEBUG1 0x00680884 +#define ENDAC_FP_DEBUG2 0x00680888 +#define ENDAC_FP_DEBUG3 0x0068088c /* secondary head */ -#define NVDAC2_CURPOS 0x00682300 -#define NVDAC2_PIXPLLC 0x00680520 -#define NVDAC2_OUTPUT 0x0068252c -#define NVDAC2_PIXPLLC2 0x0068057c -#define NVDAC2_GENCTRL 0x00682600 -#define NVDAC2_TSTCTRL 0x00682608 -#define NVDAC2_TV_SETUP 0x00682700 //verify!!! +#define ENDAC2_CURPOS 0x00682300 +#define ENDAC2_PIXPLLC 0x00680520 +#define ENDAC2_OUTPUT 0x0068252c +#define ENDAC2_PIXPLLC2 0x0068057c +#define ENDAC2_GENCTRL 0x00682600 +#define ENDAC2_TSTCTRL 0x00682608 +#define ENDAC2_TV_SETUP 0x00682700 //verify!!! /* (flatpanel registers) */ -#define NVDAC2_FP_VDISPEND 0x00682800 -#define NVDAC2_FP_VTOTAL 0x00682804 -#define NVDAC2_FP_VCRTC 0x00682808 -#define NVDAC2_FP_VSYNC_S 0x0068280c -#define NVDAC2_FP_VSYNC_E 0x00682810 -#define NVDAC2_FP_VVALID_S 0x00682814 -#define NVDAC2_FP_VVALID_E 0x00682818 -#define NVDAC2_FP_HDISPEND 0x00682820 -#define NVDAC2_FP_HTOTAL 0x00682824 -#define NVDAC2_FP_HCRTC 0x00682828 -#define NVDAC2_FP_HSYNC_S 0x0068282c -#define NVDAC2_FP_HSYNC_E 0x00682830 -#define NVDAC2_FP_HVALID_S 0x00682834 -#define NVDAC2_FP_HVALID_E 0x00682838 -#define NVDAC2_FP_CHKSUM 0x00682840 -#define NVDAC2_FP_TST_CTRL 0x00682844 -#define NVDAC2_FP_TG_CTRL 0x00682848 -#define NVDAC2_FP_DEBUG0 0x00682880 -#define NVDAC2_FP_DEBUG1 0x00682884 -#define NVDAC2_FP_DEBUG2 0x00682888 -#define NVDAC2_FP_DEBUG3 0x0068288c +#define ENDAC2_FP_VDISPEND 0x00682800 +#define ENDAC2_FP_VTOTAL 0x00682804 +#define ENDAC2_FP_VCRTC 0x00682808 +#define ENDAC2_FP_VSYNC_S 0x0068280c +#define ENDAC2_FP_VSYNC_E 0x00682810 +#define ENDAC2_FP_VVALID_S 0x00682814 +#define ENDAC2_FP_VVALID_E 0x00682818 +#define ENDAC2_FP_HDISPEND 0x00682820 +#define ENDAC2_FP_HTOTAL 0x00682824 +#define ENDAC2_FP_HCRTC 0x00682828 +#define ENDAC2_FP_HSYNC_S 0x0068282c +#define ENDAC2_FP_HSYNC_E 0x00682830 +#define ENDAC2_FP_HVALID_S 0x00682834 +#define ENDAC2_FP_HVALID_E 0x00682838 +#define ENDAC2_FP_CHKSUM 0x00682840 +#define ENDAC2_FP_TST_CTRL 0x00682844 +#define ENDAC2_FP_TG_CTRL 0x00682848 +#define ENDAC2_FP_DEBUG0 0x00682880 +#define ENDAC2_FP_DEBUG1 0x00682884 +#define ENDAC2_FP_DEBUG2 0x00682888 +#define ENDAC2_FP_DEBUG3 0x0068288c /* Nvidia CRTC indexed registers */ /* VGA standard registers: */ -#define NVCRTCX_HTOTAL 0x00 -#define NVCRTCX_HDISPE 0x01 -#define NVCRTCX_HBLANKS 0x02 -#define NVCRTCX_HBLANKE 0x03 -#define NVCRTCX_HSYNCS 0x04 -#define NVCRTCX_HSYNCE 0x05 -#define NVCRTCX_VTOTAL 0x06 -#define NVCRTCX_OVERFLOW 0x07 -#define NVCRTCX_PRROWSCN 0x08 -#define NVCRTCX_MAXSCLIN 0x09 -#define NVCRTCX_VGACURCTRL 0x0a -#define NVCRTCX_FBSTADDH 0x0c -#define NVCRTCX_FBSTADDL 0x0d -#define NVCRTCX_VSYNCS 0x10 -#define NVCRTCX_VSYNCE 0x11 -#define NVCRTCX_VDISPE 0x12 -#define NVCRTCX_PITCHL 0x13 -#define NVCRTCX_VBLANKS 0x15 -#define NVCRTCX_VBLANKE 0x16 -#define NVCRTCX_MODECTL 0x17 -#define NVCRTCX_LINECOMP 0x18 +#define ENCRTCX_HTOTAL 0x00 +#define ENCRTCX_HDISPE 0x01 +#define ENCRTCX_HBLANKS 0x02 +#define ENCRTCX_HBLANKE 0x03 +#define ENCRTCX_HSYNCS 0x04 +#define ENCRTCX_HSYNCE 0x05 +#define ENCRTCX_VTOTAL 0x06 +#define ENCRTCX_OVERFLOW 0x07 +#define ENCRTCX_PRROWSCN 0x08 +#define ENCRTCX_MAXSCLIN 0x09 +#define ENCRTCX_VGACURCTRL 0x0a +#define ENCRTCX_FBSTADDH 0x0c +#define ENCRTCX_FBSTADDL 0x0d +#define ENCRTCX_VSYNCS 0x10 +#define ENCRTCX_VSYNCE 0x11 +#define ENCRTCX_VDISPE 0x12 +#define ENCRTCX_PITCHL 0x13 +#define ENCRTCX_VBLANKS 0x15 +#define ENCRTCX_VBLANKE 0x16 +#define ENCRTCX_MODECTL 0x17 +#define ENCRTCX_LINECOMP 0x18 /* Nvidia specific registers: */ -#define NVCRTCX_REPAINT0 0x19 -#define NVCRTCX_REPAINT1 0x1a -#define NVCRTCX_FIFO 0x1b -#define NVCRTCX_LOCK 0x1f -#define NVCRTCX_FIFO_LWM 0x20 -#define NVCRTCX_BUFFER 0x21 -#define NVCRTCX_LSR 0x25 -#define NVCRTCX_PIXEL 0x28 -#define NVCRTCX_HEB 0x2d -#define NVCRTCX_CURCTL2 0x2f -#define NVCRTCX_CURCTL1 0x30 -#define NVCRTCX_CURCTL0 0x31 -#define NVCRTCX_LCD 0x33 -#define NVCRTCX_RMA 0x38 -#define NVCRTCX_INTERLACE 0x39 -#define NVCRTCX_TREG 0x3d -#define NVCRTCX_EXTRA 0x41 -#define NVCRTCX_OWNER 0x44 -#define NVCRTCX_FP_HTIMING 0x53 -#define NVCRTCX_FP_VTIMING 0x54 -#define NVCRTCX_0x59 0x59 -#define NVCRTCX_0x9f 0x9f +#define ENCRTCX_REPAINT0 0x19 +#define ENCRTCX_REPAINT1 0x1a +#define ENCRTCX_FIFO 0x1b +#define ENCRTCX_LOCK 0x1f +#define ENCRTCX_FIFO_LWM 0x20 +#define ENCRTCX_BUFFER 0x21 +#define ENCRTCX_LSR 0x25 +#define ENCRTCX_PIXEL 0x28 +#define ENCRTCX_HEB 0x2d +#define ENCRTCX_CURCTL2 0x2f +#define ENCRTCX_CURCTL1 0x30 +#define ENCRTCX_CURCTL0 0x31 +#define ENCRTCX_LCD 0x33 +#define ENCRTCX_RMA 0x38 +#define ENCRTCX_INTERLACE 0x39 +#define ENCRTCX_TREG 0x3d +#define ENCRTCX_EXTRA 0x41 +#define ENCRTCX_OWNER 0x44 +#define ENCRTCX_FP_HTIMING 0x53 +#define ENCRTCX_FP_VTIMING 0x54 +#define ENCRTCX_0x59 0x59 +#define ENCRTCX_0x9f 0x9f /* Nvidia ATTRIBUTE indexed registers */ /* VGA standard registers: */ -#define NVATBX_MODECTL 0x10 -#define NVATBX_OSCANCOLOR 0x11 -#define NVATBX_COLPLANE_EN 0x12 -#define NVATBX_HORPIXPAN 0x13 -#define NVATBX_COLSEL 0x14 +#define ENATBX_MODECTL 0x10 +#define ENATBX_OSCANCOLOR 0x11 +#define ENATBX_COLPLANE_EN 0x12 +#define ENATBX_HORPIXPAN 0x13 +#define ENATBX_COLSEL 0x14 /* Nvidia SEQUENCER indexed registers */ /* VGA standard registers: */ -#define NVSEQX_RESET 0x00 -#define NVSEQX_CLKMODE 0x01 -#define NVSEQX_MEMMODE 0x04 +#define ENSEQX_RESET 0x00 +#define ENSEQX_CLKMODE 0x01 +#define ENSEQX_MEMMODE 0x04 /* Nvidia GRAPHICS indexed registers */ /* VGA standard registers: */ -#define NVGRPHX_ENSETRESET 0x01 -#define NVGRPHX_DATAROTATE 0x03 -#define NVGRPHX_READMAPSEL 0x04 -#define NVGRPHX_MODE 0x05 -#define NVGRPHX_MISC 0x06 -#define NVGRPHX_BITMASK 0x08 +#define ENGRPHX_ENSETRESET 0x01 +#define ENGRPHX_DATAROTATE 0x03 +#define ENGRPHX_READMAPSEL 0x04 +#define ENGRPHX_MODE 0x05 +#define ENGRPHX_MISC 0x06 +#define ENGRPHX_BITMASK 0x08 /* Nvidia BES (Back End Scaler) registers (< NV10, including NV03, so RIVA128(ZX)) */ -#define NVBES_NV04_INTE 0x00680140 -#define NVBES_NV04_ISCALVH 0x00680200 -#define NVBES_NV04_CTRL_V 0x00680204 -#define NVBES_NV04_CTRL_H 0x00680208 -#define NVBES_NV04_OE_STATE 0x00680224 -#define NVBES_NV04_SU_STATE 0x00680228 -#define NVBES_NV04_RM_STATE 0x0068022c -#define NVBES_NV04_DSTREF 0x00680230 -#define NVBES_NV04_DSTSIZE 0x00680234 -#define NVBES_NV04_FIFOTHRS 0x00680238 -#define NVBES_NV04_FIFOBURL 0x0068023c -#define NVBES_NV04_COLKEY 0x00680240 -#define NVBES_NV04_GENCTRL 0x00680244 -#define NVBES_NV04_RED_AMP 0x00680280 -#define NVBES_NV04_GRN_AMP 0x00680284 -#define NVBES_NV04_BLU_AMP 0x00680288 -#define NVBES_NV04_SAT 0x0068028c +#define ENBES_NV04_INTE 0x00680140 +#define ENBES_NV04_ISCALVH 0x00680200 +#define ENBES_NV04_CTRL_V 0x00680204 +#define ENBES_NV04_CTRL_H 0x00680208 +#define ENBES_NV04_OE_STATE 0x00680224 +#define ENBES_NV04_SU_STATE 0x00680228 +#define ENBES_NV04_RM_STATE 0x0068022c +#define ENBES_NV04_DSTREF 0x00680230 +#define ENBES_NV04_DSTSIZE 0x00680234 +#define ENBES_NV04_FIFOTHRS 0x00680238 +#define ENBES_NV04_FIFOBURL 0x0068023c +#define ENBES_NV04_COLKEY 0x00680240 +#define ENBES_NV04_GENCTRL 0x00680244 +#define ENBES_NV04_RED_AMP 0x00680280 +#define ENBES_NV04_GRN_AMP 0x00680284 +#define ENBES_NV04_BLU_AMP 0x00680288 +#define ENBES_NV04_SAT 0x0068028c /* buffer 0 */ -#define NVBES_NV04_0BUFADR 0x0068020c -#define NVBES_NV04_0SRCPTCH 0x00680214 -#define NVBES_NV04_0OFFSET 0x0068021c +#define ENBES_NV04_0BUFADR 0x0068020c +#define ENBES_NV04_0SRCPTCH 0x00680214 +#define ENBES_NV04_0OFFSET 0x0068021c /* buffer 1 */ -#define NVBES_NV04_1BUFADR 0x00680210 -#define NVBES_NV04_1SRCPTCH 0x00680218 -#define NVBES_NV04_1OFFSET 0x00680220 +#define ENBES_NV04_1BUFADR 0x00680210 +#define ENBES_NV04_1SRCPTCH 0x00680218 +#define ENBES_NV04_1OFFSET 0x00680220 /* Nvidia BES (Back End Scaler) registers (>= NV10) */ -#define NVBES_NV10_INTE 0x00008140 -#define NVBES_NV10_BUFSEL 0x00008700 -#define NVBES_NV10_GENCTRL 0x00008704 -#define NVBES_NV10_COLKEY 0x00008b00 +#define ENBES_NV10_INTE 0x00008140 +#define ENBES_NV10_BUFSEL 0x00008700 +#define ENBES_NV10_GENCTRL 0x00008704 +#define ENBES_NV10_COLKEY 0x00008b00 /* buffer 0 */ -#define NVBES_NV10_0BUFADR 0x00008900 -#define NVBES_NV10_0MEMMASK 0x00008908 -#define NVBES_NV10_0BRICON 0x00008910 -#define NVBES_NV10_0SAT 0x00008918 -#define NVBES_NV10_0OFFSET 0x00008920 -#define NVBES_NV10_0SRCSIZE 0x00008928 -#define NVBES_NV10_0SRCREF 0x00008930 -#define NVBES_NV10_0ISCALH 0x00008938 -#define NVBES_NV10_0ISCALV 0x00008940 -#define NVBES_NV10_0DSTREF 0x00008948 -#define NVBES_NV10_0DSTSIZE 0x00008950 -#define NVBES_NV10_0SRCPTCH 0x00008958 +#define ENBES_NV10_0BUFADR 0x00008900 +#define ENBES_NV10_0MEMMASK 0x00008908 +#define ENBES_NV10_0BRICON 0x00008910 +#define ENBES_NV10_0SAT 0x00008918 +#define ENBES_NV10_0OFFSET 0x00008920 +#define ENBES_NV10_0SRCSIZE 0x00008928 +#define ENBES_NV10_0SRCREF 0x00008930 +#define ENBES_NV10_0ISCALH 0x00008938 +#define ENBES_NV10_0ISCALV 0x00008940 +#define ENBES_NV10_0DSTREF 0x00008948 +#define ENBES_NV10_0DSTSIZE 0x00008950 +#define ENBES_NV10_0SRCPTCH 0x00008958 /* buffer 1 */ -#define NVBES_NV10_1BUFADR 0x00008904 -#define NVBES_NV10_1MEMMASK 0x0000890c -#define NVBES_NV10_1BRICON 0x00008914 -#define NVBES_NV10_1SAT 0x0000891c -#define NVBES_NV10_1OFFSET 0x00008924 -#define NVBES_NV10_1SRCSIZE 0x0000892c -#define NVBES_NV10_1SRCREF 0x00008934 -#define NVBES_NV10_1ISCALH 0x0000893c -#define NVBES_NV10_1ISCALV 0x00008944 -#define NVBES_NV10_1DSTREF 0x0000894c -#define NVBES_NV10_1DSTSIZE 0x00008954 -#define NVBES_NV10_1SRCPTCH 0x0000895c +#define ENBES_NV10_1BUFADR 0x00008904 +#define ENBES_NV10_1MEMMASK 0x0000890c +#define ENBES_NV10_1BRICON 0x00008914 +#define ENBES_NV10_1SAT 0x0000891c +#define ENBES_NV10_1OFFSET 0x00008924 +#define ENBES_NV10_1SRCSIZE 0x0000892c +#define ENBES_NV10_1SRCREF 0x00008934 +#define ENBES_NV10_1ISCALH 0x0000893c +#define ENBES_NV10_1ISCALV 0x00008944 +#define ENBES_NV10_1DSTREF 0x0000894c +#define ENBES_NV10_1DSTSIZE 0x00008954 +#define ENBES_NV10_1SRCPTCH 0x0000895c /* Nvidia MPEG2 hardware decoder (GeForce4MX only) */ -#define NVBES_DEC_GENCTRL 0x00001588 +#define ENBES_DEC_GENCTRL 0x00001588 //old: /*MAVEN registers (<= G400) */ -#define NVMAV_PGM 0x3E -#define NVMAV_PIXPLLM 0x80 -#define NVMAV_PIXPLLN 0x81 -#define NVMAV_PIXPLLP 0x82 -#define NVMAV_GAMMA1 0x83 -#define NVMAV_GAMMA2 0x84 -#define NVMAV_GAMMA3 0x85 -#define NVMAV_GAMMA4 0x86 -#define NVMAV_GAMMA5 0x87 -#define NVMAV_GAMMA6 0x88 -#define NVMAV_GAMMA7 0x89 -#define NVMAV_GAMMA8 0x8A -#define NVMAV_GAMMA9 0x8B -#define NVMAV_MONSET 0x8C -#define NVMAV_TEST 0x8D -#define NVMAV_WREG_0X8E_L 0x8E -#define NVMAV_WREG_0X8E_H 0x8F -#define NVMAV_HSCALETV 0x90 -#define NVMAV_TSCALETVL 0x91 -#define NVMAV_TSCALETVH 0x92 -#define NVMAV_FFILTER 0x93 -#define NVMAV_MONEN 0x94 -#define NVMAV_RESYNC 0x95 -#define NVMAV_LASTLINEL 0x96 -#define NVMAV_LASTLINEH 0x97 -#define NVMAV_WREG_0X98_L 0x98 -#define NVMAV_WREG_0X98_H 0x99 -#define NVMAV_HSYNCLENL 0x9A -#define NVMAV_HSYNCLENH 0x9B -#define NVMAV_HSYNCSTRL 0x9C -#define NVMAV_HSYNCSTRH 0x9D -#define NVMAV_HDISPLAYL 0x9E -#define NVMAV_HDISPLAYH 0x9F -#define NVMAV_HTOTALL 0xA0 -#define NVMAV_HTOTALH 0xA1 -#define NVMAV_VSYNCLENL 0xA2 -#define NVMAV_VSYNCLENH 0xA3 -#define NVMAV_VSYNCSTRL 0xA4 -#define NVMAV_VSYNCSTRH 0xA5 -#define NVMAV_VDISPLAYL 0xA6 -#define NVMAV_VDISPLAYH 0xA7 -#define NVMAV_VTOTALL 0xA8 -#define NVMAV_VTOTALH 0xA9 -#define NVMAV_HVIDRSTL 0xAA -#define NVMAV_HVIDRSTH 0xAB -#define NVMAV_VVIDRSTL 0xAC -#define NVMAV_VVIDRSTH 0xAD -#define NVMAV_VSOMETHINGL 0xAE -#define NVMAV_VSOMETHINGH 0xAF -#define NVMAV_OUTMODE 0xB0 -#define NVMAV_LOCK 0xB3 -#define NVMAV_LUMA 0xB9 -#define NVMAV_VDISPLAYTV 0xBE -#define NVMAV_STABLE 0xBF -#define NVMAV_HDISPLAYTV 0xC2 -#define NVMAV_BREG_0XC6 0xC6 +#define ENMAV_PGM 0x3E +#define ENMAV_PIXPLLM 0x80 +#define ENMAV_PIXPLLN 0x81 +#define ENMAV_PIXPLLP 0x82 +#define ENMAV_GAMMA1 0x83 +#define ENMAV_GAMMA2 0x84 +#define ENMAV_GAMMA3 0x85 +#define ENMAV_GAMMA4 0x86 +#define ENMAV_GAMMA5 0x87 +#define ENMAV_GAMMA6 0x88 +#define ENMAV_GAMMA7 0x89 +#define ENMAV_GAMMA8 0x8A +#define ENMAV_GAMMA9 0x8B +#define ENMAV_MONSET 0x8C +#define ENMAV_TEST 0x8D +#define ENMAV_WREG_0X8E_L 0x8E +#define ENMAV_WREG_0X8E_H 0x8F +#define ENMAV_HSCALETV 0x90 +#define ENMAV_TSCALETVL 0x91 +#define ENMAV_TSCALETVH 0x92 +#define ENMAV_FFILTER 0x93 +#define ENMAV_MONEN 0x94 +#define ENMAV_RESYNC 0x95 +#define ENMAV_LASTLINEL 0x96 +#define ENMAV_LASTLINEH 0x97 +#define ENMAV_WREG_0X98_L 0x98 +#define ENMAV_WREG_0X98_H 0x99 +#define ENMAV_HSYNCLENL 0x9A +#define ENMAV_HSYNCLENH 0x9B +#define ENMAV_HSYNCSTRL 0x9C +#define ENMAV_HSYNCSTRH 0x9D +#define ENMAV_HDISPLAYL 0x9E +#define ENMAV_HDISPLAYH 0x9F +#define ENMAV_HTOTALL 0xA0 +#define ENMAV_HTOTALH 0xA1 +#define ENMAV_VSYNCLENL 0xA2 +#define ENMAV_VSYNCLENH 0xA3 +#define ENMAV_VSYNCSTRL 0xA4 +#define ENMAV_VSYNCSTRH 0xA5 +#define ENMAV_VDISPLAYL 0xA6 +#define ENMAV_VDISPLAYH 0xA7 +#define ENMAV_VTOTALL 0xA8 +#define ENMAV_VTOTALH 0xA9 +#define ENMAV_HVIDRSTL 0xAA +#define ENMAV_HVIDRSTH 0xAB +#define ENMAV_VVIDRSTL 0xAC +#define ENMAV_VVIDRSTH 0xAD +#define ENMAV_VSOMETHINGL 0xAE +#define ENMAV_VSOMETHINGH 0xAF +#define ENMAV_OUTMODE 0xB0 +#define ENMAV_LOCK 0xB3 +#define ENMAV_LUMA 0xB9 +#define ENMAV_VDISPLAYTV 0xBE +#define ENMAV_STABLE 0xBF +#define ENMAV_HDISPLAYTV 0xC2 +#define ENMAV_BREG_0XC6 0xC6 //end old. /* Macros for convenient accesses to the NV chips */ -#define NV_REG8(r_) ((vuint8 *)regs)[(r_)] -#define NV_REG16(r_) ((vuint16 *)regs)[(r_) >> 1] -#define NV_REG32(r_) ((vuint32 *)regs)[(r_) >> 2] +#define ENG_REG8(r_) ((vuint8 *)regs)[(r_)] +#define ENG_REG16(r_) ((vuint16 *)regs)[(r_) >> 1] +#define ENG_RG32(r_) ((vuint32 *)regs)[(r_) >> 2] /* read and write to PCI config space */ -#define CFGR(A) (eng_pci_access.offset=NVCFG_##A, ioctl(fd,NV_GET_PCI, &eng_pci_access,sizeof(eng_pci_access)), eng_pci_access.value) -#define CFGW(A,B) (eng_pci_access.offset=NVCFG_##A, eng_pci_access.value = B, ioctl(fd,NV_SET_PCI,&eng_pci_access,sizeof(eng_pci_access))) +#define CFGR(A) (eng_pci_access.offset=ENCFG_##A, ioctl(fd,ENG_GET_PCI, &eng_pci_access,sizeof(eng_pci_access)), eng_pci_access.value) +#define CFGW(A,B) (eng_pci_access.offset=ENCFG_##A, eng_pci_access.value = B, ioctl(fd,ENG_SET_PCI,&eng_pci_access,sizeof(eng_pci_access))) /* read and write from ISA I/O space */ -#define ISAWB(A,B)(eng_isa_access.adress=A, eng_isa_access.data = (uint8)B, eng_isa_access.size = 1, ioctl(fd,NV_ISA_OUT, &eng_isa_access,sizeof(eng_isa_access))) -#define ISAWW(A,B)(eng_isa_access.adress=A, eng_isa_access.data = B, eng_isa_access.size = 2, ioctl(fd,NV_ISA_OUT, &eng_isa_access,sizeof(eng_isa_access))) -#define ISARB(A) (eng_isa_access.adress=A, ioctl(fd,NV_ISA_IN, &eng_isa_access,sizeof(eng_isa_access)), (uint8)eng_isa_access.data) -#define ISARW(A) (eng_isa_access.adress=A, ioctl(fd,NV_ISA_IN, &eng_isa_access,sizeof(eng_isa_access)), eng_isa_access.data) +#define ISAWB(A,B)(eng_isa_access.adress=A, eng_isa_access.data = (uint8)B, eng_isa_access.size = 1, ioctl(fd,ENG_ISA_OUT, &eng_isa_access,sizeof(eng_isa_access))) +#define ISAWW(A,B)(eng_isa_access.adress=A, eng_isa_access.data = B, eng_isa_access.size = 2, ioctl(fd,ENG_ISA_OUT, &eng_isa_access,sizeof(eng_isa_access))) +#define ISARB(A) (eng_isa_access.adress=A, ioctl(fd,ENG_ISA_IN, &eng_isa_access,sizeof(eng_isa_access)), (uint8)eng_isa_access.data) +#define ISARW(A) (eng_isa_access.adress=A, ioctl(fd,ENG_ISA_IN, &eng_isa_access,sizeof(eng_isa_access)), eng_isa_access.data) /* read and write from the dac registers */ -#define DACR(A) (NV_REG32(NVDAC_##A)) -#define DACW(A,B) (NV_REG32(NVDAC_##A)=B) +#define DACR(A) (ENG_RG32(ENDAC_##A)) +#define DACW(A,B) (ENG_RG32(ENDAC_##A)=B) /* read and write from the secondary dac registers */ -#define DAC2R(A) (NV_REG32(NVDAC2_##A)) -#define DAC2W(A,B) (NV_REG32(NVDAC2_##A)=B) +#define DAC2R(A) (ENG_RG32(ENDAC2_##A)) +#define DAC2W(A,B) (ENG_RG32(ENDAC2_##A)=B) /* read and write from the backend scaler registers */ -#define BESR(A) (NV_REG32(NVBES_##A)) -#define BESW(A,B) (NV_REG32(NVBES_##A)=B) +#define BESR(A) (ENG_RG32(ENBES_##A)) +#define BESW(A,B) (ENG_RG32(ENBES_##A)=B) /* read and write from CRTC indexed registers */ -#define CRTCW(A,B)(NV_REG16(NV16_CRTCIND) = ((NVCRTCX_##A) | ((B) << 8))) -#define CRTCR(A) (NV_REG8(NV8_CRTCIND) = (NVCRTCX_##A), NV_REG8(NV8_CRTCDAT)) +#define CRTCW(A,B)(ENG_REG16(RG16_CRTCIND) = ((ENCRTCX_##A) | ((B) << 8))) +#define CRTCR(A) (ENG_REG8(RG8_CRTCIND) = (ENCRTCX_##A), ENG_REG8(RG8_CRTCDAT)) /* read and write from second CRTC indexed registers */ -#define CRTC2W(A,B)(NV_REG16(NV16_CRTC2IND) = ((NVCRTCX_##A) | ((B) << 8))) -#define CRTC2R(A) (NV_REG8(NV8_CRTC2IND) = (NVCRTCX_##A), NV_REG8(NV8_CRTC2DAT)) +#define CRTC2W(A,B)(ENG_REG16(RG16_CRTC2IND) = ((ENCRTCX_##A) | ((B) << 8))) +#define CRTC2R(A) (ENG_REG8(RG8_CRTC2IND) = (ENCRTCX_##A), ENG_REG8(RG8_CRTC2DAT)) /* read and write from ATTRIBUTE indexed registers */ -#define ATBW(A,B)(NV_REG8(NV8_INSTAT1), NV_REG8(NV8_ATTRINDW) = ((NVATBX_##A) | 0x20), NV_REG8(NV8_ATTRDATW) = (B)) -#define ATBR(A) (NV_REG8(NV8_INSTAT1), NV_REG8(NV8_ATTRINDW) = ((NVATBX_##A) | 0x20), NV_REG8(NV8_ATTRDATR)) +#define ATBW(A,B)(ENG_REG8(RG8_INSTAT1), ENG_REG8(RG8_ATTRINDW) = ((ENATBX_##A) | 0x20), ENG_REG8(RG8_ATTRDATW) = (B)) +#define ATBR(A) (ENG_REG8(RG8_INSTAT1), ENG_REG8(RG8_ATTRINDW) = ((ENATBX_##A) | 0x20), ENG_REG8(RG8_ATTRDATR)) /* read and write from ATTRIBUTE indexed registers */ -#define ATB2W(A,B)(NV_REG8(NV8_INSTAT1), NV_REG8(NV8_ATTR2INDW) = ((NVATBX_##A) | 0x20), NV_REG8(NV8_ATTR2DATW) = (B)) -#define ATB2R(A) (NV_REG8(NV8_INSTAT1), NV_REG8(NV8_ATTR2INDW) = ((NVATBX_##A) | 0x20), NV_REG8(NV8_ATTR2DATR)) +#define ATB2W(A,B)(ENG_REG8(RG8_INSTAT1), ENG_REG8(RG8_ATTR2INDW) = ((ENATBX_##A) | 0x20), ENG_REG8(RG8_ATTR2DATW) = (B)) +#define ATB2R(A) (ENG_REG8(RG8_INSTAT1), ENG_REG8(RG8_ATTR2INDW) = ((ENATBX_##A) | 0x20), ENG_REG8(RG8_ATTR2DATR)) /* read and write from SEQUENCER indexed registers */ -#define SEQW(A,B)(NV_REG16(NV16_SEQIND) = ((NVSEQX_##A) | ((B) << 8))) -#define SEQR(A) (NV_REG8(NV8_SEQIND) = (NVSEQX_##A), NV_REG8(NV8_SEQDAT)) +#define SEQW(A,B)(ENG_REG16(RG16_SEQIND) = ((ENSEQX_##A) | ((B) << 8))) +#define SEQR(A) (ENG_REG8(RG8_SEQIND) = (ENSEQX_##A), ENG_REG8(RG8_SEQDAT)) /* read and write from PCI GRAPHICS indexed registers */ -#define GRPHW(A,B)(NV_REG16(NV16_GRPHIND) = ((NVGRPHX_##A) | ((B) << 8))) -#define GRPHR(A) (NV_REG8(NV8_GRPHIND) = (NVGRPHX_##A), NV_REG8(NV8_GRPHDAT)) +#define GRPHW(A,B)(ENG_REG16(RG16_GRPHIND) = ((ENGRPHX_##A) | ((B) << 8))) +#define GRPHR(A) (ENG_REG8(RG8_GRPHIND) = (ENGRPHX_##A), ENG_REG8(RG8_GRPHDAT)) /* read and write from the acceleration engine registers */ -#define ACCR(A) (NV_REG32(NVACC_##A)) -#define ACCW(A,B) (NV_REG32(NVACC_##A)=B) +#define ACCR(A) (ENG_RG32(ENACC_##A)) +#define ACCW(A,B) (ENG_RG32(ENACC_##A)=B) //old: /* read and write from maven (<= G400) */ -#define MAVR(A) (i2c_maven_read (NVMAV_##A )) -#define MAVW(A,B) (i2c_maven_write(NVMAV_##A ,B)) -#define MAVRW(A) (i2c_maven_read (NVMAV_##A )|(i2c_maven_read(NVMAV_##A +1)<<8)) -#define MAVWW(A,B) (i2c_maven_write(NVMAV_##A ,B &0xFF),i2c_maven_write(NVMAV_##A +1,B >>8)) +#define MAVR(A) (i2c_maven_read (ENMAV_##A )) +#define MAVW(A,B) (i2c_maven_write(ENMAV_##A ,B)) +#define MAVRW(A) (i2c_maven_read (ENMAV_##A )|(i2c_maven_read(ENMAV_##A +1)<<8)) +#define MAVWW(A,B) (i2c_maven_write(ENMAV_##A ,B &0xFF),i2c_maven_write(ENMAV_##A +1,B >>8)) diff --git a/src/add-ons/accelerants/skeleton/InitAccelerant.c b/src/add-ons/accelerants/skeleton/InitAccelerant.c index 1782e9cf3d..6c87b83931 100644 --- a/src/add-ons/accelerants/skeleton/InitAccelerant.c +++ b/src/add-ons/accelerants/skeleton/InitAccelerant.c @@ -25,9 +25,9 @@ static status_t init_common(int the_fd) { /* memorize the file descriptor */ fd = the_fd; /* set the magic number so the driver knows we're for real */ - gpd.magic = NV_PRIVATE_DATA_MAGIC; + gpd.magic = SKEL_PRIVATE_DATA_MAGIC; /* contact driver and get a pointer to the registers and shared data */ - result = ioctl(fd, NV_GET_PRIVATE_DATA, &gpd, sizeof(gpd)); + result = ioctl(fd, ENG_GET_PRIVATE_DATA, &gpd, sizeof(gpd)); if (result != B_OK) goto error0; /* clone the shared area for our use */ @@ -211,7 +211,7 @@ ssize_t ACCELERANT_CLONE_INFO_SIZE(void) { Since we're passing the name of the device as the only required info, return the size of the name buffer */ - return B_OS_NAME_LENGTH; // apsed, was MAX_NV_DEVICE_NAME_LENGTH; + return B_OS_NAME_LENGTH; // apsed, was MAX_ENG_DEVICE_NAME_LENGTH; } @@ -224,10 +224,10 @@ void GET_ACCELERANT_CLONE_INFO(void *data) { status_t result; /* call the kernel driver to get the device name */ - dn.magic = NV_PRIVATE_DATA_MAGIC; + dn.magic = SKEL_PRIVATE_DATA_MAGIC; /* store the returned info directly into the passed buffer */ dn.name = (char *)data; - result = ioctl(fd, NV_DEVICE_NAME, &dn, sizeof(dn)); + result = ioctl(fd, ENG_DEVICE_NAME, &dn, sizeof(dn)); } /* diff --git a/src/add-ons/accelerants/skeleton/SetDisplayMode.c b/src/add-ons/accelerants/skeleton/SetDisplayMode.c index 307d57e582..6475db0e93 100644 --- a/src/add-ons/accelerants/skeleton/SetDisplayMode.c +++ b/src/add-ons/accelerants/skeleton/SetDisplayMode.c @@ -22,10 +22,10 @@ static void interrupt_enable(bool flag) { eng_set_bool_state sbs; /* set the magic number so the driver knows we're for real */ - sbs.magic = NV_PRIVATE_DATA_MAGIC; + sbs.magic = SKEL_PRIVATE_DATA_MAGIC; sbs.do_it = flag; /* contact driver and get a pointer to the registers and shared data */ - result = ioctl(fd, NV_RUN_INTERRUPTS, &sbs, sizeof(sbs)); + result = ioctl(fd, ENG_RUN_INTERRUPTS, &sbs, sizeof(sbs)); } /* First validate the mode, then call lots of bit banging stuff to set the mode(s)! */ diff --git a/src/add-ons/accelerants/skeleton/engine/acc.c b/src/add-ons/accelerants/skeleton/engine/acc.c index cb0671b944..40dd0377bc 100644 --- a/src/add-ons/accelerants/skeleton/engine/acc.c +++ b/src/add-ons/accelerants/skeleton/engine/acc.c @@ -52,7 +52,7 @@ status_t eng_acc_init() if (si->ps.card_arch == NV04A) { /* set framebuffer config: type = notiling, PRAMIN write access enabled */ - NV_REG32(NV32_PFB_CONFIG_0) = 0x00001114; + ENG_RG32(RG32_PFB_CONFIG_0) = 0x00001114; } /*** PFIFO ***/ @@ -685,7 +685,7 @@ status_t eng_acc_init() * setup clipping region (workspace size) to 32768 x 32768 pixels: * wait for room in fifo for clipping cmd if needed. * (fifo holds 256 32bit words: count those, not bytes) */ - while (((NV_REG16(NV16_CLP_FIFOFREE)) >> 2) < 2) + while (((ENG_REG16(RG16_CLP_FIFOFREE)) >> 2) < 2) { /* snooze a bit so I do not hammer the bus */ snooze (10); @@ -703,7 +703,7 @@ status_t eng_acc_setup_blit() /* setup solid pattern: * wait for room in fifo for pattern cmd if needed. * (fifo holds 256 32bit words: count those, not bytes) */ - while (((NV_REG16(NV16_PAT_FIFOFREE)) >> 2) < 5) + while (((ENG_REG16(RG16_PAT_FIFOFREE)) >> 2) < 5) { /* snooze a bit so I do not hammer the bus */ snooze (10); @@ -718,7 +718,7 @@ status_t eng_acc_setup_blit() /* ROP3 registers (Raster OPeration): * wait for room in fifo for ROP cmd if needed. * (fifo holds 256 32bit words: count those, not bytes) */ - while (((NV_REG16(NV16_ROP_FIFOFREE)) >> 2) < 1) + while (((ENG_REG16(RG16_ROP_FIFOFREE)) >> 2) < 1) { /* snooze a bit so I do not hammer the bus */ snooze (10); @@ -736,7 +736,7 @@ status_t eng_acc_blit(uint16 xs,uint16 ys,uint16 xd,uint16 yd,uint16 w,uint16 h) /* instruct engine what to blit: * wait for room in fifo for blit cmd if needed. * (fifo holds 256 32bit words: count those, not bytes) */ - while (((NV_REG16(NV16_BLT_FIFOFREE)) >> 2) < 3) + while (((ENG_REG16(RG16_BLT_FIFOFREE)) >> 2) < 3) { /* snooze a bit so I do not hammer the bus */ snooze (10); @@ -756,7 +756,7 @@ status_t eng_acc_setup_rectangle(uint32 color) /* setup solid pattern: * wait for room in fifo for pattern cmd if needed. * (fifo holds 256 32bit words: count those, not bytes) */ - while (((NV_REG16(NV16_PAT_FIFOFREE)) >> 2) < 5) + while (((ENG_REG16(RG16_PAT_FIFOFREE)) >> 2) < 5) { /* snooze a bit so I do not hammer the bus */ snooze (10); @@ -771,7 +771,7 @@ status_t eng_acc_setup_rectangle(uint32 color) /* ROP3 registers (Raster OPeration): * wait for room in fifo for ROP cmd if needed. * (fifo holds 256 32bit words: count those, not bytes) */ - while (((NV_REG16(NV16_ROP_FIFOFREE)) >> 2) < 1) + while (((ENG_REG16(RG16_ROP_FIFOFREE)) >> 2) < 1) { /* snooze a bit so I do not hammer the bus */ snooze (10); @@ -782,7 +782,7 @@ status_t eng_acc_setup_rectangle(uint32 color) /* setup fill color: * wait for room in fifo for bitmap cmd if needed. * (fifo holds 256 32bit words: count those, not bytes) */ - while (((NV_REG16(NV16_BMP_FIFOFREE)) >> 2) < 1) + while (((ENG_REG16(RG16_BMP_FIFOFREE)) >> 2) < 1) { /* snooze a bit so I do not hammer the bus */ snooze (10); @@ -798,7 +798,7 @@ status_t eng_acc_rectangle(uint32 xs,uint32 xe,uint32 ys,uint32 yl) /* instruct engine what to fill: * wait for room in fifo for bitmap cmd if needed. * (fifo holds 256 32bit words: count those, not bytes) */ - while (((NV_REG16(NV16_BMP_FIFOFREE)) >> 2) < 2) + while (((ENG_REG16(RG16_BMP_FIFOFREE)) >> 2) < 2) { /* snooze a bit so I do not hammer the bus */ snooze (10); @@ -816,7 +816,7 @@ status_t eng_acc_setup_rect_invert() /* setup solid pattern: * wait for room in fifo for pattern cmd if needed. * (fifo holds 256 32bit words: count those, not bytes) */ - while (((NV_REG16(NV16_PAT_FIFOFREE)) >> 2) < 5) + while (((ENG_REG16(RG16_PAT_FIFOFREE)) >> 2) < 5) { /* snooze a bit so I do not hammer the bus */ snooze (10); @@ -831,7 +831,7 @@ status_t eng_acc_setup_rect_invert() /* ROP3 registers (Raster OPeration): * wait for room in fifo for ROP cmd if needed. * (fifo holds 256 32bit words: count those, not bytes) */ - while (((NV_REG16(NV16_ROP_FIFOFREE)) >> 2) < 1) + while (((ENG_REG16(RG16_ROP_FIFOFREE)) >> 2) < 1) { /* snooze a bit so I do not hammer the bus */ snooze (10); @@ -842,7 +842,7 @@ status_t eng_acc_setup_rect_invert() /* reset fill color: * wait for room in fifo for bitmap cmd if needed. * (fifo holds 256 32bit words: count those, not bytes) */ - while (((NV_REG16(NV16_BMP_FIFOFREE)) >> 2) < 1) + while (((ENG_REG16(RG16_BMP_FIFOFREE)) >> 2) < 1) { /* snooze a bit so I do not hammer the bus */ snooze (10); @@ -858,7 +858,7 @@ status_t eng_acc_rectangle_invert(uint32 xs,uint32 xe,uint32 ys,uint32 yl) /* instruct engine what to invert: * wait for room in fifo for bitmap cmd if needed. * (fifo holds 256 32bit words: count those, not bytes) */ - while (((NV_REG16(NV16_BMP_FIFOFREE)) >> 2) < 2) + while (((ENG_REG16(RG16_BMP_FIFOFREE)) >> 2) < 2) { /* snooze a bit so I do not hammer the bus */ snooze (10); diff --git a/src/add-ons/accelerants/skeleton/engine/agp.c b/src/add-ons/accelerants/skeleton/engine/agp.c index a580d5f133..adce533bac 100644 --- a/src/add-ons/accelerants/skeleton/engine/agp.c +++ b/src/add-ons/accelerants/skeleton/engine/agp.c @@ -25,26 +25,26 @@ status_t eng_agp_setup(void) { uint32 reg; - LOG(4, ("AGP: STRAPINFO2 contains $%08x\n", NV_REG32(NV32_NVSTRAPINFO2))); + LOG(4, ("AGP: STRAPINFO2 contains $%08x\n", ENG_RG32(RG32_NVSTRAPINFO2))); LOG(4, ("AGP: attempting to enable fastwrite support..\n")); /* 'force' FW support */ - reg = (NV_REG32(NV32_NVSTRAPINFO2) & ~0x00000800); + reg = (ENG_RG32(RG32_NVSTRAPINFO2) & ~0x00000800); /* enable strapinfo overwrite */ - NV_REG32(NV32_NVSTRAPINFO2) = (reg | 0x80000000); + ENG_RG32(RG32_NVSTRAPINFO2) = (reg | 0x80000000); - LOG(4, ("AGP: STRAPINFO2 now contains $%08x\n", NV_REG32(NV32_NVSTRAPINFO2))); + LOG(4, ("AGP: STRAPINFO2 now contains $%08x\n", ENG_RG32(RG32_NVSTRAPINFO2))); } /* set the magic number so the skeleton kerneldriver knows we're for real */ - nca.magic = nai.magic = NV_PRIVATE_DATA_MAGIC; + nca.magic = nai.magic = SKEL_PRIVATE_DATA_MAGIC; /* contact driver and get a pointer to the registers and shared data */ for (index = 0; index < 8; index++) { /* get nth AGP device info */ nai.index = index; - ioctl(fd, NV_GET_NTH_AGP_INFO, &nai, sizeof(nai)); + ioctl(fd, ENG_GET_NTH_AGP_INFO, &nai, sizeof(nai)); /* abort if no agp busmanager found */ if (!nai.agp_bus) @@ -88,8 +88,8 @@ status_t eng_agp_setup(void) /* if our card is not an AGP type, abort here */ /* Note: * We have to iterate through the capability list as specified in the PCI spec - * one way or the other, otherwise we cannot distinquish between nVidia PCI and - * AGP type cards as nVidia PCI cards still have AGP registers that pretend to + * one way or the other, otherwise we cannot distinquish between PCI and + * AGP type cards as PCI cards still might have AGP registers that pretend to * support AGP. * We rely on the AGP busmanager to iterate trough this list for us. */ if (!agp) @@ -110,7 +110,7 @@ status_t eng_agp_setup(void) /* let the AGP busmanager setup PCI mode. * (the AGP speed scheme is of no consequence now) */ nca.cmd = 0x00000000; - ioctl(fd, NV_ENABLE_AGP, &nca, sizeof(nca)); + ioctl(fd, ENG_ENABLE_AGP, &nca, sizeof(nca)); } else { @@ -121,7 +121,7 @@ status_t eng_agp_setup(void) nca.cmd = 0xfffffff7; /* ..but we do need to select the right speed scheme fetched from our card */ if (eng_ai.interface.agp_stat & AGP_rate_rev) nca.cmd |= AGP_rate_rev; - ioctl(fd, NV_ENABLE_AGP, &nca, sizeof(nca)); + ioctl(fd, ENG_ENABLE_AGP, &nca, sizeof(nca)); } /* list mode now activated, diff --git a/src/add-ons/accelerants/skeleton/engine/bes.c b/src/add-ons/accelerants/skeleton/engine/bes.c index 43bac1a566..7ee404aadc 100644 --- a/src/add-ons/accelerants/skeleton/engine/bes.c +++ b/src/add-ons/accelerants/skeleton/engine/bes.c @@ -357,16 +357,16 @@ status_t eng_bes_to_crtc(bool crtc) { LOG(4,("Overlay: switching overlay to CRTC2\n")); /* switch overlay engine to CRTC2 */ - NV_REG32(NV32_FUNCSEL) &= ~0x00001000; - NV_REG32(NV32_2FUNCSEL) |= 0x00001000; + ENG_RG32(RG32_FUNCSEL) &= ~0x00001000; + ENG_RG32(RG32_2FUNCSEL) |= 0x00001000; si->overlay.crtc = !si->crtc_switch_mode; } else { LOG(4,("Overlay: switching overlay to CRTC1\n")); /* switch overlay engine to CRTC1 */ - NV_REG32(NV32_2FUNCSEL) &= ~0x00001000; - NV_REG32(NV32_FUNCSEL) |= 0x00001000; + ENG_RG32(RG32_2FUNCSEL) &= ~0x00001000; + ENG_RG32(RG32_FUNCSEL) |= 0x00001000; si->overlay.crtc = si->crtc_switch_mode; } return B_OK; diff --git a/src/add-ons/accelerants/skeleton/engine/crtc.c b/src/add-ons/accelerants/skeleton/engine/crtc.c index 5de1227c8f..70bb632ac8 100644 --- a/src/add-ons/accelerants/skeleton/engine/crtc.c +++ b/src/add-ons/accelerants/skeleton/engine/crtc.c @@ -280,7 +280,7 @@ status_t eng_crtc_set_timing(display_mode target) /* setup HSYNC & VSYNC polarity */ LOG(2,("CRTC: sync polarity: ")); - temp = NV_REG8(NV8_MISCR); + temp = ENG_REG8(RG8_MISCR); if (target.timing.flags & B_POSITIVE_HSYNC) { LOG(2,("H:pos ")); @@ -301,9 +301,9 @@ status_t eng_crtc_set_timing(display_mode target) LOG(2,("V:neg ")); temp |= 0x80; } - NV_REG8(NV8_MISCW) = temp; + ENG_REG8(RG8_MISCW) = temp; - LOG(2,(", MISC reg readback: $%02x\n", NV_REG8(NV8_MISCR))); + LOG(2,(", MISC reg readback: $%02x\n", ENG_REG8(RG8_MISCR))); } /* always disable interlaced operation */ @@ -610,7 +610,7 @@ status_t eng_crtc_set_display_start(uint32 startadd,uint8 bpp) /* we might have no retraces during setmode! */ /* wait 25mS max. for retrace to occur (refresh > 40Hz) */ - while (((NV_REG32(NV32_RASTER) & 0x000007ff) < si->dm.timing.v_display) && + while (((ENG_RG32(RG32_RASTER) & 0x000007ff) < si->dm.timing.v_display) && (timeout < (25000/10))) { /* don't snooze much longer or retrace might get missed! */ @@ -646,7 +646,7 @@ status_t eng_crtc_set_display_start(uint32 startadd,uint8 bpp) * wrap-around at 16Mb boundaries!! */ /* 30bit adress in 32bit words */ - NV_REG32(NV32_NV10FBSTADD32) = (startadd & 0xfffffffc); + ENG_RG32(RG32_NV10FBSTADD32) = (startadd & 0xfffffffc); } /* set NV4/NV10 byte adress: (b0 - 1) */ @@ -686,7 +686,7 @@ status_t eng_crtc_cursor_init() * This register does not exist on pre-NV10 and 'Go' cards. */ /* cursorbitmap must still start on 2Kbyte boundary: */ - NV_REG32(NV32_NV10CURADD32) = (curadd & 0xfffff800); + ENG_RG32(RG32_NV10CURADD32) = (curadd & 0xfffff800); } /* set cursor colour: not needed because of direct nature of cursor bitmap. */ @@ -699,7 +699,7 @@ status_t eng_crtc_cursor_init() } /* select 32x32 pixel, 16bit color cursorbitmap, no doublescan */ - NV_REG32(NV32_CURCONF) = 0x02000100; + ENG_RG32(RG32_CURCONF) = 0x02000100; /* activate hardware cursor */ eng_crtc_cursor_show(); @@ -807,7 +807,7 @@ status_t eng_crtc_cursor_position(uint16 x, uint16 y) { /* we have vertical lines below old and new cursorposition to spare. So we * update the cursor postion 'mid-screen', but below that area. */ - while (((uint16)(NV_REG32(NV32_RASTER) & 0x000007ff)) < (yhigh + 16)) + while (((uint16)(ENG_RG32(RG32_RASTER) & 0x000007ff)) < (yhigh + 16)) { snooze(10); } @@ -815,7 +815,7 @@ status_t eng_crtc_cursor_position(uint16 x, uint16 y) else { /* no room to spare, just wait for retrace (is relatively slow) */ - while ((NV_REG32(NV32_RASTER) & 0x000007ff) < si->dm.timing.v_display) + while ((ENG_RG32(RG32_RASTER) & 0x000007ff) < si->dm.timing.v_display) { /* don't snooze much longer or retrace might get missed! */ snooze(10); diff --git a/src/add-ons/accelerants/skeleton/engine/crtc2.c b/src/add-ons/accelerants/skeleton/engine/crtc2.c index 162df1dcd8..fa1c181259 100644 --- a/src/add-ons/accelerants/skeleton/engine/crtc2.c +++ b/src/add-ons/accelerants/skeleton/engine/crtc2.c @@ -263,7 +263,7 @@ status_t eng_crtc2_set_timing(display_mode target) /* setup HSYNC & VSYNC polarity */ LOG(2,("CRTC2: sync polarity: ")); - temp = NV_REG8(NV8_MISCR); + temp = ENG_REG8(RG8_MISCR); if (target.timing.flags & B_POSITIVE_HSYNC) { LOG(2,("H:pos ")); @@ -284,9 +284,9 @@ status_t eng_crtc2_set_timing(display_mode target) LOG(2,("V:neg ")); temp |= 0x80; } - NV_REG8(NV8_MISCW) = temp; + ENG_REG8(RG8_MISCW) = temp; - LOG(2,(", MISC reg readback: $%02x\n", NV_REG8(NV8_MISCR))); + LOG(2,(", MISC reg readback: $%02x\n", ENG_REG8(RG8_MISCR))); } /* always disable interlaced operation */ @@ -592,7 +592,7 @@ status_t eng_crtc2_set_display_start(uint32 startadd,uint8 bpp) /* we might have no retraces during setmode! */ /* wait 25mS max. for retrace to occur (refresh > 40Hz) */ - while (((NV_REG32(NV32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) && + while (((ENG_RG32(RG32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) && (timeout < (25000/10))) { /* don't snooze much longer or retrace might get missed! */ @@ -609,7 +609,7 @@ status_t eng_crtc2_set_display_start(uint32 startadd,uint8 bpp) * wrap-around at 16Mb boundaries!! */ /* 30bit adress in 32bit words */ - NV_REG32(NV32_NV10FB2STADD32) = (startadd & 0xfffffffc); + ENG_RG32(RG32_NV10FB2STADD32) = (startadd & 0xfffffffc); /* set byte adress: (b0 - 1) */ ATB2W(HORPIXPAN, ((startadd & 0x00000003) << 1)); @@ -648,7 +648,7 @@ status_t eng_crtc2_cursor_init() * This register does not exist on pre-NV10 and 'Go' cards. */ /* cursorbitmap must still start on 2Kbyte boundary: */ - NV_REG32(NV32_NV10CUR2ADD32) = (curadd & 0xfffff800); + ENG_RG32(RG32_NV10CUR2ADD32) = (curadd & 0xfffff800); } /* set cursor colour: not needed because of direct nature of cursor bitmap. */ @@ -661,7 +661,7 @@ status_t eng_crtc2_cursor_init() } /* select 32x32 pixel, 16bit color cursorbitmap, no doublescan */ - NV_REG32(NV32_2CURCONF) = 0x02000100; + ENG_RG32(RG32_2CURCONF) = 0x02000100; /* activate hardware cursor */ eng_crtc2_cursor_show(); @@ -769,7 +769,7 @@ status_t eng_crtc2_cursor_position(uint16 x, uint16 y) { /* we have vertical lines below old and new cursorposition to spare. So we * update the cursor postion 'mid-screen', but below that area. */ - while (((uint16)(NV_REG32(NV32_RASTER2) & 0x000007ff)) < (yhigh + 16)) + while (((uint16)(ENG_RG32(RG32_RASTER2) & 0x000007ff)) < (yhigh + 16)) { snooze(10); } @@ -777,7 +777,7 @@ status_t eng_crtc2_cursor_position(uint16 x, uint16 y) else { /* no room to spare, just wait for retrace (is relatively slow) */ - while ((NV_REG32(NV32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) + while ((ENG_RG32(RG32_RASTER2) & 0x000007ff) < si->dm.timing.v_display) { /* don't snooze much longer or retrace might get missed! */ snooze(10); diff --git a/src/add-ons/accelerants/skeleton/engine/dac.c b/src/add-ons/accelerants/skeleton/engine/dac.c index 205e578858..bc02be69fa 100644 --- a/src/add-ons/accelerants/skeleton/engine/dac.c +++ b/src/add-ons/accelerants/skeleton/engine/dac.c @@ -84,8 +84,8 @@ status_t eng_dac_mode(int mode,float brightness) if (eng_dac_palette(r,g,b) != B_OK) return B_ERROR; /* disable palette RAM adressing mask */ - NV_REG8(NV8_PALMASK) = 0xff; - LOG(2,("DAC: PAL pixrdmsk readback $%02x\n", NV_REG8(NV8_PALMASK))); + ENG_REG8(RG8_PALMASK) = 0xff; + LOG(2,("DAC: PAL pixrdmsk readback $%02x\n", ENG_REG8(RG8_PALMASK))); return B_OK; } @@ -98,17 +98,17 @@ status_t eng_dac_palette(uint8 r[256],uint8 g[256],uint8 b[256]) LOG(4,("DAC: setting palette\n")); /* select first PAL adress before starting programming */ - NV_REG8(NV8_PALINDW) = 0x00; + ENG_REG8(RG8_PALINDW) = 0x00; /* loop through all 256 to program DAC */ for (i = 0; i < 256; i++) { /* the 6 implemented bits are on b0-b5 of the bus */ - NV_REG8(NV8_PALDATA) = r[i]; - NV_REG8(NV8_PALDATA) = g[i]; - NV_REG8(NV8_PALDATA) = b[i]; + ENG_REG8(RG8_PALDATA) = r[i]; + ENG_REG8(RG8_PALDATA) = g[i]; + ENG_REG8(RG8_PALDATA) = b[i]; } - if (NV_REG8(NV8_PALINDW) != 0x00) + if (ENG_REG8(RG8_PALINDW) != 0x00) { LOG(8,("DAC: PAL write index incorrect after programming\n")); return B_ERROR; @@ -118,12 +118,12 @@ if (1) uint8 R, G, B; /* select first PAL adress to read (modulo 3 counter) */ - NV_REG8(NV8_PALINDR) = 0x00; + ENG_REG8(RG8_PALINDR) = 0x00; for (i = 0; i < 256; i++) { - R = NV_REG8(NV8_PALDATA); - G = NV_REG8(NV8_PALDATA); - B = NV_REG8(NV8_PALDATA); + R = ENG_REG8(RG8_PALDATA); + G = ENG_REG8(RG8_PALDATA); + B = ENG_REG8(RG8_PALDATA); if ((r[i] != R) || (g[i] != G) || (b[i] != B)) LOG(1,("DAC palette %d: w %x %x %x, r %x %x %x\n", i, r[i], g[i], b[i], R, G, B)); // apsed } diff --git a/src/add-ons/accelerants/skeleton/engine/dac2.c b/src/add-ons/accelerants/skeleton/engine/dac2.c index b7b1458905..2cacc28ff3 100644 --- a/src/add-ons/accelerants/skeleton/engine/dac2.c +++ b/src/add-ons/accelerants/skeleton/engine/dac2.c @@ -92,8 +92,8 @@ status_t eng_dac2_mode(int mode,float brightness) if (eng_dac2_palette(r,g,b) != B_OK) return B_ERROR; /* disable palette RAM adressing mask */ - NV_REG8(NV8_PAL2MASK) = 0xff; - LOG(2,("DAC2: PAL pixrdmsk readback $%02x\n", NV_REG8(NV8_PAL2MASK))); + ENG_REG8(RG8_PAL2MASK) = 0xff; + LOG(2,("DAC2: PAL pixrdmsk readback $%02x\n", ENG_REG8(RG8_PAL2MASK))); return B_OK; } @@ -106,17 +106,17 @@ status_t eng_dac2_palette(uint8 r[256],uint8 g[256],uint8 b[256]) LOG(4,("DAC2: setting palette\n")); /* select first PAL adress before starting programming */ - NV_REG8(NV8_PAL2INDW) = 0x00; + ENG_REG8(RG8_PAL2INDW) = 0x00; /* loop through all 256 to program DAC */ for (i = 0; i < 256; i++) { /* the 6 implemented bits are on b0-b5 of the bus */ - NV_REG8(NV8_PAL2DATA) = r[i]; - NV_REG8(NV8_PAL2DATA) = g[i]; - NV_REG8(NV8_PAL2DATA) = b[i]; + ENG_REG8(RG8_PAL2DATA) = r[i]; + ENG_REG8(RG8_PAL2DATA) = g[i]; + ENG_REG8(RG8_PAL2DATA) = b[i]; } - if (NV_REG8(NV8_PAL2INDW) != 0x00) + if (ENG_REG8(RG8_PAL2INDW) != 0x00) { LOG(8,("DAC2: PAL write index incorrect after programming\n")); return B_ERROR; @@ -126,12 +126,12 @@ if (1) uint8 R, G, B; /* select first PAL adress to read (modulo 3 counter) */ - NV_REG8(NV8_PAL2INDR) = 0x00; + ENG_REG8(RG8_PAL2INDR) = 0x00; for (i = 0; i < 256; i++) { - R = NV_REG8(NV8_PAL2DATA); - G = NV_REG8(NV8_PAL2DATA); - B = NV_REG8(NV8_PAL2DATA); + R = ENG_REG8(RG8_PAL2DATA); + G = ENG_REG8(RG8_PAL2DATA); + B = ENG_REG8(RG8_PAL2DATA); if ((r[i] != R) || (g[i] != G) || (b[i] != B)) LOG(1,("DAC2 palette %d: w %x %x %x, r %x %x %x\n", i, r[i], g[i], b[i], R, G, B)); // apsed } diff --git a/src/add-ons/accelerants/skeleton/engine/general.c b/src/add-ons/accelerants/skeleton/engine/general.c index 9fe6728cc8..78bd8fa883 100644 --- a/src/add-ons/accelerants/skeleton/engine/general.c +++ b/src/add-ons/accelerants/skeleton/engine/general.c @@ -17,7 +17,7 @@ static void eng_dump_configuration_space (void) #define DUMP_CFG(reg, type) if (si->ps.card_type >= type) do { \ uint32 value = CFGR(reg); \ MSG(("configuration_space 0x%02x %20s 0x%08x\n", \ - NVCFG_##reg, #reg, value)); \ + ENCFG_##reg, #reg, value)); \ } while (0) DUMP_CFG (DEVID, 0); DUMP_CFG (DEVCTRL, 0); @@ -406,7 +406,7 @@ status_t eng_general_head_select(bool cross) static status_t eng_general_bios_to_powergraphics() { /* let acc engine make power off/power on cycle to start 'fresh' */ - NV_REG32(NV32_PWRUPCTRL) = 0x13110011; + ENG_RG32(RG32_PWRUPCTRL) = 0x13110011; snooze(1000); /* power-up all hardware function blocks */ @@ -419,10 +419,10 @@ static status_t eng_general_bios_to_powergraphics() * bit 8: PFIFO, * bit 4: PMEDIA, * bit 0: TVOUT. (> NV04A) */ - NV_REG32(NV32_PWRUPCTRL) = 0x13111111; + ENG_RG32(RG32_PWRUPCTRL) = 0x13111111; /* select colormode CRTC registers base adresses */ - NV_REG8(NV8_MISCW) = 0xcb; + ENG_REG8(RG8_MISCW) = 0xcb; /* enable access to primary head */ set_crtc_owner(0); @@ -456,8 +456,8 @@ static status_t eng_general_bios_to_powergraphics() * bit 9: TVout chip #2 (confirmed on NV18, NV25, NV28), * bit 8: TVout chip #1 (all cards), * bit 4: both I2C busses (all cards) */ - NV_REG32(NV32_2FUNCSEL) &= ~0x00001000; - NV_REG32(NV32_FUNCSEL) |= 0x00001000; + ENG_RG32(RG32_2FUNCSEL) &= ~0x00001000; + ENG_RG32(RG32_FUNCSEL) |= 0x00001000; } si->overlay.crtc = false; @@ -497,7 +497,7 @@ static status_t eng_general_bios_to_powergraphics() /* enable access to secondary head */ set_crtc_owner(1); /* select colormode CRTC2 registers base adresses */ - NV_REG8(NV8_MISCW) = 0xcb; + ENG_REG8(RG8_MISCW) = 0xcb; /* note: 'BUFFER' is a non-standard register in behaviour(!) on most * NV11's like the GeForce2 MX200, while the MX400 and non-NV11 cards * behave normally. diff --git a/src/add-ons/accelerants/skeleton/engine/globals.c b/src/add-ons/accelerants/skeleton/engine/globals.c index ed9d7674a4..90ce4f3575 100644 --- a/src/add-ons/accelerants/skeleton/engine/globals.c +++ b/src/add-ons/accelerants/skeleton/engine/globals.c @@ -20,7 +20,7 @@ int accelerantIsClone; eng_get_set_pci eng_pci_access= { - NV_PRIVATE_DATA_MAGIC, + SKEL_PRIVATE_DATA_MAGIC, 0, 4, 0 @@ -28,7 +28,7 @@ eng_get_set_pci eng_pci_access= eng_in_out_isa eng_isa_access= { - NV_PRIVATE_DATA_MAGIC, + SKEL_PRIVATE_DATA_MAGIC, 0, 1, 0 diff --git a/src/add-ons/accelerants/skeleton/engine/info.c b/src/add-ons/accelerants/skeleton/engine/info.c index 83e20f1a45..3efc3be0d8 100644 --- a/src/add-ons/accelerants/skeleton/engine/info.c +++ b/src/add-ons/accelerants/skeleton/engine/info.c @@ -238,10 +238,10 @@ static status_t coldstart_card(uint8* rom, uint16 init1, uint16 init2, uint16 in LOG(8,("INFO: now executing coldstart...\n")); /* select colormode CRTC registers base adresses */ - NV_REG8(NV8_MISCW) = 0xcb; + ENG_REG8(RG8_MISCW) = 0xcb; /* unknown.. */ - NV_REG8(NV8_VSE2) = 0x01; + ENG_REG8(RG8_VSE2) = 0x01; /* enable access to primary head */ set_crtc_owner(0); @@ -311,15 +311,15 @@ static status_t coldstart_card_516_up(uint8* rom, PinsTables tabs, uint16 ram_ta //fixme?: works on at least one NV28... how about other cards? if (si->ps.card_type == NV28) { - fb_mrs2 = NV_REG32(NV32_FB_MRS2); - fb_mrs1 = NV_REG32(NV32_FB_MRS1); + fb_mrs2 = ENG_RG32(RG32_FB_MRS2); + fb_mrs1 = ENG_RG32(RG32_FB_MRS1); } /* select colormode CRTC registers base adresses */ - NV_REG8(NV8_MISCW) = 0xcb; + ENG_REG8(RG8_MISCW) = 0xcb; /* unknown.. */ - NV_REG8(NV8_VSE2) = 0x01; + ENG_REG8(RG8_VSE2) = 0x01; /* enable access to primary head */ set_crtc_owner(0); @@ -381,8 +381,8 @@ static status_t coldstart_card_516_up(uint8* rom, PinsTables tabs, uint16 ram_ta /* get NV28 RAM access up and running */ //fixme?: works on at least one NV28... how about other cards? - NV_REG32(NV32_FB_MRS2) = fb_mrs2; - NV_REG32(NV32_FB_MRS1) = fb_mrs1; + ENG_RG32(RG32_FB_MRS2) = fb_mrs2; + ENG_RG32(RG32_FB_MRS1) = fb_mrs1; } /* now enable ROM shadow or the card will remain shut-off! */ @@ -448,7 +448,7 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16 float calced_clk; uint8 m, n, p; eng_dac_sys_pll_find(((float)data2), &calced_clk, &m, &n, &p, 0); - NV_REG32(reg) = ((p << 16) | (n << 8) | m); + ENG_RG32(reg) = ((p << 16) | (n << 8) | m); } log_pll(reg, data2); break; @@ -470,7 +470,7 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16 adress += 2; data2 = *((uint32*)(&(rom[data]))); LOG(8,("cmd 'WR indirect 32bit reg' $%08x = $%08x\n", reg, data2)); - if (exec) NV_REG32(reg) = data2; + if (exec) ENG_RG32(reg) = data2; break; case 0x63: *size -= 1; @@ -509,8 +509,8 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16 LOG(8,("cmd 'WR 32bit reg $%08x = $%08x, then = $%08x' (always done)\n", reg, data, data2)); /* always done */ - NV_REG32(reg) = data; - NV_REG32(reg) = data2; + ENG_RG32(reg) = data; + ENG_RG32(reg) = data2; CFGW(ROMSHADOW, (CFGR(ROMSHADOW) & 0xfffffffe)); break; case 0x69: @@ -536,10 +536,10 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16 if (exec) { translate_ISA_PCI(®); - byte = NV_REG8(reg); + byte = ENG_REG8(reg); byte &= (uint8)and_out; byte |= (uint8)or_in; - NV_REG8(reg) = byte; + ENG_REG8(reg) = byte; } break; case 0x6d: @@ -554,7 +554,7 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16 /* execute */ adress += 1; - data = NV_REG32(NV32_NV4STRAPINFO); + data = ENG_RG32(RG32_NV4STRAPINFO); and_out = *((uint8*)(&(rom[adress]))); adress += 1; byte = *((uint8*)(&(rom[adress]))); @@ -594,10 +594,10 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16 reg, and_out, or_in)); if (exec) { - data = NV_REG32(reg); + data = ENG_RG32(reg); data &= and_out; data |= or_in; - NV_REG32(reg) = data; + ENG_RG32(reg) = data; } break; case 0x71: @@ -637,7 +637,7 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16 /* execute */ adress += 1; - data = NV_REG32(NV32_NVSTRAPINFO2); + data = ENG_RG32(RG32_NVSTRAPINFO2); and_out = *((uint32*)(&(rom[adress]))); adress += 4; data2 = *((uint32*)(&(rom[adress]))); @@ -691,7 +691,7 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16 adress += 2; LOG(8,("cmd 'WR 32bit reg' $%08x = $%08x (b31-16 = '0', b15-0 = data)\n", reg, data)); - if (exec) NV_REG32(reg) = data; + if (exec) ENG_RG32(reg) = data; break; case 0x78: *size -= 6; @@ -718,11 +718,11 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16 if (exec) { translate_ISA_PCI(®); - NV_REG8(reg) = index; - byte = NV_REG8(reg + 1); + ENG_REG8(reg) = index; + byte = ENG_REG8(reg + 1); byte &= (uint8)and_out; byte |= (uint8)or_in; - NV_REG8(reg + 1) = byte; + ENG_REG8(reg + 1) = byte; } break; case 0x79: @@ -747,7 +747,7 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16 float calced_clk; uint8 m, n, p; eng_dac_sys_pll_find((data / 100.0), &calced_clk, &m, &n, &p, 0); - NV_REG32(reg) = ((p << 16) | (n << 8) | m); + ENG_RG32(reg) = ((p << 16) | (n << 8) | m); } log_pll(reg, (data / 100)); break; @@ -768,7 +768,7 @@ static status_t exec_type1_script(uint8* rom, uint16 adress, int16* size, uint16 data = *((uint32*)(&(rom[adress]))); adress += 4; LOG(8,("cmd 'WR 32bit reg' $%08x = $%08x\n", reg, data)); - if (exec) NV_REG32(reg) = data; + if (exec) ENG_RG32(reg) = data; break; default: LOG(8,("unknown cmd, aborting!\n\n")); @@ -787,33 +787,33 @@ static void log_pll(uint32 reg, uint32 freq) LOG(8,("INFO: ---WARNING: check/update PLL programming script code!!!\n")); switch (reg) { - case NV32_MEMPLL: + case RG32_MEMPLL: LOG(8,("INFO: ---Memory PLL accessed.\n")); /* update the card's specs */ si->ps.std_memory_clock = freq; break; - case NV32_COREPLL: + case RG32_COREPLL: LOG(8,("INFO: ---Core PLL accessed.\n")); /* update the card's specs */ si->ps.std_engine_clock = freq; break; - case NVDAC_PIXPLLC: + case ENDAC_PIXPLLC: LOG(8,("INFO: ---DAC1 PLL accessed.\n")); break; - case NVDAC2_PIXPLLC: + case ENDAC2_PIXPLLC: LOG(8,("INFO: ---DAC2 PLL accessed.\n")); break; /* unexpected cases, here for learning goals... */ - case NV32_MEMPLL2: + case RG32_MEMPLL2: LOG(8,("INFO: ---NV31/NV36 extension to memory PLL accessed only!\n")); break; - case NV32_COREPLL2: + case RG32_COREPLL2: LOG(8,("INFO: ---NV31/NV36 extension to core PLL accessed only!\n")); break; - case NVDAC_PIXPLLC2: + case ENDAC_PIXPLLC2: LOG(8,("INFO: ---NV31/NV36 extension to DAC1 PLL accessed only!\n")); break; - case NVDAC2_PIXPLLC2: + case ENDAC2_PIXPLLC2: LOG(8,("INFO: ---NV31/NV36 extension to DAC2 PLL accessed only!\n")); break; default: @@ -828,9 +828,9 @@ static void setup_ram_config(uint8* rom, uint16 ram_tab) uint8 cnt; /* set MRS = 256 */ - NV_REG32(NV32_PFB_DEBUG_0) &= 0xffffffef; + ENG_RG32(RG32_PFB_DEBUG_0) &= 0xffffffef; /* read RAM config hardware(?) strap */ - ram_cfg = ((NV_REG32(NV32_NVSTRAPINFO2) >> 2) & 0x0000000f); + ram_cfg = ((ENG_RG32(RG32_NVSTRAPINFO2) >> 2) & 0x0000000f); LOG(8,("INFO: ---RAM config strap is $%01x\n", ram_cfg)); /* use it as a pointer in a BIOS table for prerecorded RAM configurations */ ram_cfg = *((uint16*)(&(rom[(ram_tab + (ram_cfg * 2))]))); @@ -876,15 +876,15 @@ static void setup_ram_config(uint8* rom, uint16 ram_tab) break; } /* set RAM amount, width and type */ - data = (NV_REG32(NV32_NV4STRAPINFO) & 0xffffffc0); - NV_REG32(NV32_NV4STRAPINFO) = (data | (ram_cfg & 0x0000003f)); + data = (ENG_RG32(RG32_NV4STRAPINFO) & 0xffffffc0); + ENG_RG32(RG32_NV4STRAPINFO) = (data | (ram_cfg & 0x0000003f)); /* setup write to read delay (?) */ - data = (NV_REG32(NV32_PFB_CONFIG_1) & 0xff8ffffe); + data = (ENG_RG32(RG32_PFB_CONFIG_1) & 0xff8ffffe); data |= ((ram_cfg & 0x00000700) << 12); /* force update via b0 = 0... */ - NV_REG32(NV32_PFB_CONFIG_1) = data; + ENG_RG32(RG32_PFB_CONFIG_1) = data; /* ... followed by b0 = 1(?) */ - NV_REG32(NV32_PFB_CONFIG_1) = (data | 0x00000001); + ENG_RG32(RG32_PFB_CONFIG_1) = (data | 0x00000001); /* do RAM width test to confirm RAM width set to be correct */ /* write testpattern to first 128 bits of graphics memory... */ @@ -896,7 +896,7 @@ static void setup_ram_config(uint8* rom, uint16 ram_tab) if (((uint32 *)si->framebuffer)[3] != data) { LOG(8,("INFO: ---RAM width tested: width is 64bits, correcting settings.\n")); - NV_REG32(NV32_NV4STRAPINFO) &= ~0x00000004; + ENG_RG32(RG32_NV4STRAPINFO) &= ~0x00000004; } else { @@ -963,11 +963,11 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size, LOG(8,("INFO: (cont.) then WR result data to 32bit reg $%08x'\n", reg2)); if (*exec && reg2) { - data = NV_REG32(reg); + data = ENG_RG32(reg); data &= and_out; data >>= shift; data2 = *((uint32*)(&(rom[(*adress + (data << 2))]))); - NV_REG32(reg2) = data2; + ENG_RG32(reg2) = data2; } *adress += size32; break; @@ -1003,13 +1003,13 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size, if (*exec && reg2) { translate_ISA_PCI(®); - NV_REG8(reg) = index; - byte = NV_REG8(reg + 1); + ENG_REG8(reg) = index; + byte = ENG_REG8(reg + 1); byte &= (uint8)and_out; byte >>= byte2; offset32 = (byte << 2); data = *((uint32*)(&(rom[(*adress + offset32)]))); - NV_REG32(reg2) = data; + ENG_RG32(reg2) = data; } *adress += size32; break; @@ -1075,8 +1075,8 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size, LOG(8,("INFO: (cont.) RD table-index ($%02x) for cmd $39'\n", offset32)); translate_ISA_PCI(®); - NV_REG8(reg) = index; - byte = NV_REG8(reg + 1); + ENG_REG8(reg) = index; + byte = ENG_REG8(reg + 1); byte &= (uint8)and_out; data = (byte >> shift); data <<= 1; @@ -1102,10 +1102,10 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size, uint8 m, n, p; eng_dac_sys_pll_find((data2 / 100.0), &calced_clk, &m, &n, &p, 0); /* programming the PLL needs to be done in steps! (confirmed NV28) */ - data = NV_REG32(reg2); - NV_REG32(reg2) = ((data & 0xffff0000) | (n << 8) | m); - data = NV_REG32(reg2); - NV_REG32(reg2) = ((p << 16) | (n << 8) | m); + data = ENG_RG32(reg2); + ENG_RG32(reg2) = ((data & 0xffff0000) | (n << 8) | m); + data = ENG_RG32(reg2); + ENG_RG32(reg2) = ((p << 16) | (n << 8) | m); //fixme? /* program 2nd set N and M scalers if they exist (b31=1 enables them) */ // if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) @@ -1178,7 +1178,7 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size, index, reg2, and_out2)); if (*exec) { - data = NV_REG32(reg); + data = ENG_RG32(reg); if (byte2 < 0x80) { data >>= byte2; @@ -1189,11 +1189,11 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size, } data &= and_out; translate_ISA_PCI(®2); - NV_REG8(reg2) = index; - byte = NV_REG8(reg2 + 1); + ENG_REG8(reg2) = index; + byte = ENG_REG8(reg2 + 1); byte &= (uint8)and_out2; byte |= (uint8)data; - NV_REG8(reg2 + 1) = byte; + ENG_REG8(reg2 + 1) = byte; } break; case 0x38: /* new */ @@ -1274,12 +1274,12 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size, *adress += 1; data2 = *((uint8*)(&(rom[*adress]))); *adress += 1; - NV_REG32(reg2) = data2; - data = NV_REG32(reg); + ENG_RG32(reg2) = data2; + data = ENG_RG32(reg); data &= and_out; data |= or_in; data |= or_in2; - NV_REG32(reg) = data; + ENG_RG32(reg) = data; } } else @@ -1307,7 +1307,7 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size, if (*exec) { translate_ISA_PCI(®); - NV_REG8(reg) = byte; + ENG_REG8(reg) = byte; } break; case 0x62: /* new */ @@ -1332,7 +1332,7 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size, if (*exec) { translate_ISA_PCI(®); - NV_REG16(reg) = ((((uint16)byte) << 8) | index); + ENG_REG16(reg) = ((((uint16)byte) << 8) | index); } break; case 0x63: /* new setup compared to pre-NV10 version */ @@ -1380,8 +1380,8 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size, LOG(8,("cmd 'WR 32bit reg $%08x = $%08x, then = $%08x' (always done)\n", reg, data, data2)); /* always done */ - NV_REG32(reg) = data; - NV_REG32(reg) = data2; + ENG_RG32(reg) = data; + ENG_RG32(reg) = data2; CFGW(ROMSHADOW, (CFGR(ROMSHADOW) & 0xfffffffe)); break; case 0x69: /* identical to type1 */ @@ -1407,10 +1407,10 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size, if (*exec) { translate_ISA_PCI(®); - byte = NV_REG8(reg); + byte = ENG_REG8(reg); byte &= (uint8)and_out; byte |= (uint8)or_in; - NV_REG8(reg) = byte; + ENG_REG8(reg) = byte; } break; case 0x6a: /* new */ @@ -1479,10 +1479,10 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size, reg, and_out, or_in)); if (*exec) { - data = NV_REG32(reg); + data = ENG_RG32(reg); data &= and_out; data |= or_in; - NV_REG32(reg) = data; + ENG_RG32(reg) = data; } break; case 0x6f: /* new */ @@ -1522,7 +1522,7 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size, { reg2 = *((uint32*)(&(rom[(offset32 + (safe32 << 3))]))); data2 = *((uint32*)(&(rom[(offset32 + (safe32 << 3) + 4)]))); - NV_REG32(reg2) = data2; + ENG_RG32(reg2) = data2; safe32++; } } @@ -1598,7 +1598,7 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size, reg = *((uint32*)(&(rom[data]))); and_out = *((uint32*)(&(rom[(data + 4)]))); data2 = *((uint32*)(&(rom[(data + 8)]))); - data = NV_REG32(reg); + data = ENG_RG32(reg); data &= and_out; LOG(8,("cmd 'CHK bits AND-out $%08x reg $%08x for $%08x'\n", and_out, reg, data2)); @@ -1633,8 +1633,8 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size, LOG(8,("cmd 'CHK bits AND-out $%02x idx ISA reg $%02x via $%04x for $%02x'\n", and_out, index, reg, byte2)); translate_ISA_PCI(®); - NV_REG8(reg) = index; - byte = NV_REG8(reg + 1); + ENG_REG8(reg) = index; + byte = ENG_REG8(reg + 1); byte &= (uint8)and_out; if (byte != byte2) { @@ -1671,11 +1671,11 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size, if (*exec) { translate_ISA_PCI(®); - NV_REG8(reg) = index; - byte = NV_REG8(reg + 1); + ENG_REG8(reg) = index; + byte = ENG_REG8(reg + 1); byte &= (uint8)and_out; byte |= (uint8)or_in; - NV_REG8(reg + 1) = byte; + ENG_REG8(reg + 1) = byte; } break; case 0x79: @@ -1701,10 +1701,10 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size, uint8 m, n, p; eng_dac_sys_pll_find((data / 100.0), &calced_clk, &m, &n, &p, 0); /* programming the PLL needs to be done in steps! (confirmed NV28) */ - data2 = NV_REG32(reg); - NV_REG32(reg) = ((data2 & 0xffff0000) | (n << 8) | m); - data2 = NV_REG32(reg); - NV_REG32(reg) = ((p << 16) | (n << 8) | m); + data2 = ENG_RG32(reg); + ENG_RG32(reg) = ((data2 & 0xffff0000) | (n << 8) | m); + data2 = ENG_RG32(reg); + ENG_RG32(reg) = ((p << 16) | (n << 8) | m); //fixme? /* program 2nd set N and M scalers if they exist (b31=1 enables them) */ // if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) @@ -1729,7 +1729,7 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size, data = *((uint32*)(&(rom[*adress]))); *adress += 4; LOG(8,("cmd 'WR 32bit reg' $%08x = $%08x\n", reg, data)); - if (*exec) NV_REG32(reg) = data; + if (*exec) ENG_RG32(reg) = data; break; default: LOG(8,("unknown cmd, aborting!\n\n")); @@ -1759,8 +1759,8 @@ static void exec_cmd_39_type2(uint8* rom, uint32 data, PinsTables tabs, bool* ex LOG(8,("cmd 'AND-out bits $%02x idx ISA reg $%02x via $%04x, shift-right = $%02x,\n", and_out, index, reg, shift)); translate_ISA_PCI(®); - NV_REG8(reg) = index; - byte = NV_REG8(reg + 1); + ENG_REG8(reg) = index; + byte = ENG_REG8(reg + 1); byte &= (uint8)and_out; offset32 += (byte >> shift); safe = byte = *((uint8*)(&(rom[offset32]))); @@ -1787,7 +1787,7 @@ static void setup_ram_config_nv10_up(uint8* rom) status_t stat = B_ERROR; /* set 'refctrl is valid' */ - NV_REG32(NV32_PFB_REFCTRL) = 0x80000000; + ENG_RG32(RG32_PFB_REFCTRL) = 0x80000000; /* check RAM for 256bits buswidth(?) */ while ((cnt < 4) && (stat != B_OK)) @@ -1810,7 +1810,7 @@ static void setup_ram_config_nv10_up(uint8* rom) if (stat != B_OK) { LOG(8,("INFO: ---RAM test #1 done: access errors, modified setup.\n")); - data = NV_REG32(NV32_PFB_CONFIG_0); + data = ENG_RG32(RG32_PFB_CONFIG_0); if (data & 0x00000010) { data &= 0xffffffcf; @@ -1820,7 +1820,7 @@ static void setup_ram_config_nv10_up(uint8* rom) data &= 0xffffffcf; data |= 0x00000020; } - NV_REG32(NV32_PFB_CONFIG_0) = data; + ENG_RG32(RG32_PFB_CONFIG_0) = data; } else { @@ -1833,7 +1833,7 @@ static void setup_ram_config_nv10_up(uint8* rom) while ((cnt < 4) && (stat != B_OK)) { /* read RAM size */ - data = NV_REG32(NV32_NV10STRAPINFO); + data = ENG_RG32(RG32_NV10STRAPINFO); /* subtract 1MB */ data -= 0x00100000; /* write testpattern at generated RAM adress */ @@ -1854,7 +1854,7 @@ static void setup_ram_config_nv10_up(uint8* rom) if (stat != B_OK) { LOG(8,("INFO: ---RAM test #2 done: access errors, modified setup.\n")); - NV_REG32(NV32_PFB_CONFIG_0) &= 0xffffefff; + ENG_RG32(RG32_PFB_CONFIG_0) &= 0xffffefff; } else { @@ -1871,13 +1871,13 @@ static void setup_ram_config_nv28(uint8* rom) status_t stat = B_ERROR; /* set 'refctrl is valid' */ - NV_REG32(NV32_PFB_REFCTRL) = 0x80000000; + ENG_RG32(RG32_PFB_REFCTRL) = 0x80000000; /* check RAM */ while ((cnt < 4) && (stat != B_OK)) { /* set bit 11: 'pulse' something into a new setting? */ - NV_REG32(NV32_PFB_CONFIG_0) |= 0x00000800; + ENG_RG32(RG32_PFB_CONFIG_0) |= 0x00000800; /* write testpattern to RAM adress 127Mb */ ((uint32 *)si->framebuffer)[0x01fc0000] = 0x4e564441; /* reset first RAM adress */ @@ -1897,7 +1897,7 @@ static void setup_ram_config_nv28(uint8* rom) } /* clear bit 11: set normal mode */ - NV_REG32(NV32_PFB_CONFIG_0) &= ~0x00000800; + ENG_RG32(RG32_PFB_CONFIG_0) &= ~0x00000800; if (stat == B_OK) LOG(8,("INFO: ---RAM test done: access was OK within %d iteration(s).\n", cnt)); @@ -1910,49 +1910,49 @@ static status_t translate_ISA_PCI(uint32* reg) switch (*reg) { case 0x03c0: - *reg = NV8_ATTRDATW; + *reg = RG8_ATTRDATW; break; case 0x03c1: - *reg = NV8_ATTRDATR; + *reg = RG8_ATTRDATR; break; case 0x03c2: - *reg = NV8_MISCW; + *reg = RG8_MISCW; break; case 0x03c4: - *reg = NV8_SEQIND; + *reg = RG8_SEQIND; break; case 0x03c5: - *reg = NV8_SEQDAT; + *reg = RG8_SEQDAT; break; case 0x03c6: - *reg = NV8_PALMASK; + *reg = RG8_PALMASK; break; case 0x03c7: - *reg = NV8_PALINDR; + *reg = RG8_PALINDR; break; case 0x03c8: - *reg = NV8_PALINDW; + *reg = RG8_PALINDW; break; case 0x03c9: - *reg = NV8_PALDATA; + *reg = RG8_PALDATA; break; case 0x03cc: - *reg = NV8_MISCR; + *reg = RG8_MISCR; break; case 0x03ce: - *reg = NV8_GRPHIND; + *reg = RG8_GRPHIND; break; case 0x03cf: - *reg = NV8_GRPHDAT; + *reg = RG8_GRPHDAT; break; case 0x03d4: - *reg = NV8_CRTCIND; + *reg = RG8_CRTCIND; break; case 0x03d5: - *reg = NV8_CRTCDAT; + *reg = RG8_CRTCDAT; break; case 0x03da: - *reg = NV8_INSTAT1; + *reg = RG8_INSTAT1; break; default: LOG(8,("\n\nINFO: WARNING: ISA->PCI register adress translation failed!\n\n")); @@ -2334,7 +2334,7 @@ static void detect_panels() /* dump some panel configuration registers... */ LOG(2,("INFO: Dumping flatpanel registers:\n")); - LOG(2,("DUALHEAD_CTRL: $%08x\n", NV_REG32(NV32_DUALHEAD_CTRL))); + LOG(2,("DUALHEAD_CTRL: $%08x\n", ENG_RG32(RG32_DUALHEAD_CTRL))); LOG(2,("DAC1: FP_HDISPEND: %d\n", DACR(FP_HDISPEND))); LOG(2,("DAC1: FP_HTOTAL: %d\n", DACR(FP_HTOTAL))); LOG(2,("DAC1: FP_HCRTC: %d\n", DACR(FP_HCRTC))); @@ -2359,8 +2359,8 @@ static void detect_panels() LOG(2,("DAC1: FP_DEBUG2: $%08x\n", DACR(FP_DEBUG2))); LOG(2,("DAC1: FP_DEBUG3: $%08x\n", DACR(FP_DEBUG3))); - LOG(2,("DAC1: FUNCSEL: $%08x\n", NV_REG32(NV32_FUNCSEL))); - LOG(2,("DAC1: PANEL_PWR: $%08x\n", NV_REG32(NV32_PANEL_PWR))); + LOG(2,("DAC1: FUNCSEL: $%08x\n", ENG_RG32(RG32_FUNCSEL))); + LOG(2,("DAC1: PANEL_PWR: $%08x\n", ENG_RG32(RG32_PANEL_PWR))); if(si->ps.secondary_head) { @@ -2388,8 +2388,8 @@ static void detect_panels() LOG(2,("DAC2: FP_DEBUG2: $%08x\n", DAC2R(FP_DEBUG2))); LOG(2,("DAC2: FP_DEBUG3: $%08x\n", DAC2R(FP_DEBUG3))); - LOG(2,("DAC2: FUNCSEL: $%08x\n", NV_REG32(NV32_2FUNCSEL))); - LOG(2,("DAC2: PANEL_PWR: $%08x\n", NV_REG32(NV32_2PANEL_PWR))); + LOG(2,("DAC2: FUNCSEL: $%08x\n", ENG_RG32(RG32_2FUNCSEL))); + LOG(2,("DAC2: PANEL_PWR: $%08x\n", ENG_RG32(RG32_2PANEL_PWR))); } LOG(2,("INFO: End flatpanel registers dump.\n")); } @@ -2850,7 +2850,7 @@ static void pinsnv30_arch_fake(void) static void getRAMsize_arch_nv4(void) { - uint32 strapinfo = NV_REG32(NV32_NV4STRAPINFO); + uint32 strapinfo = ENG_RG32(RG32_NV4STRAPINFO); if (strapinfo & 0x00000100) { @@ -2883,7 +2883,7 @@ static void getRAMsize_arch_nv4(void) static void getstrap_arch_nv4(void) { - uint32 strapinfo = NV_REG32(NV32_NVSTRAPINFO2); + uint32 strapinfo = ENG_RG32(RG32_NVSTRAPINFO2); /* determine PLL reference crystal frequency */ if (strapinfo & 0x00000040) @@ -2898,7 +2898,7 @@ static void getstrap_arch_nv4(void) static void getRAMsize_arch_nv10_20_30_40(void) { uint32 dev_manID = CFGR(DEVID); - uint32 strapinfo = NV_REG32(NV32_NV10STRAPINFO); + uint32 strapinfo = ENG_RG32(RG32_NV10STRAPINFO); switch (dev_manID) { @@ -2950,7 +2950,7 @@ static void getRAMsize_arch_nv10_20_30_40(void) static void getstrap_arch_nv10_20_30_40(void) { uint32 dev_manID = CFGR(DEVID); - uint32 strapinfo = NV_REG32(NV32_NVSTRAPINFO2); + uint32 strapinfo = ENG_RG32(RG32_NVSTRAPINFO2); /* determine PLL reference crystal frequency: three types are used... */ if (strapinfo & 0x00000040) diff --git a/src/add-ons/accelerants/skeleton/engine/tvout.c b/src/add-ons/accelerants/skeleton/engine/tvout.c index f1e6b7131b..577f1328b9 100644 --- a/src/add-ons/accelerants/skeleton/engine/tvout.c +++ b/src/add-ons/accelerants/skeleton/engine/tvout.c @@ -681,7 +681,7 @@ int maventv_init(display_mode target) // if (si->ps.card_type <= G400MAX) MAVW(PGM, 0x01); // else // { -// DXIW(TVO_IDX, NVMAV_PGM); +// DXIW(TVO_IDX, ENMAV_PGM); // DXIW(TVO_DATA, 0x01); // } @@ -917,7 +917,7 @@ int maventv_init(display_mode target) // MAVW(GAMMA9, 0xC8); /* 200 */ /* set flickerfilter */ - /* OFF: is dependant on MAVEN chip version(?): NV_TVO_B = $40, else $00. + /* OFF: is dependant on MAVEN chip version(?): ENG_TVO_B = $40, else $00. * ON : always set $a2. */ // MAVW(FFILTER, 0xa2); @@ -1197,7 +1197,7 @@ int maventv_init(display_mode target) // if (si->ps.card_type <= G400MAX) MAVW(PGM, 0x00); // else // { -// DXIW(TVO_IDX, NVMAV_PGM); +// DXIW(TVO_IDX, ENMAV_PGM); // DXIW(TVO_DATA, 0x00); /* Select 2.0 Volt MAVEN DAC ref. so we have enough contrast/brightness range */ diff --git a/src/add-ons/kernel/drivers/graphics/skeleton/driver.c b/src/add-ons/kernel/drivers/graphics/skeleton/driver.c index 3879c9ef5b..a36fd48b67 100644 --- a/src/add-ons/kernel/drivers/graphics/skeleton/driver.c +++ b/src/add-ons/kernel/drivers/graphics/skeleton/driver.c @@ -143,33 +143,33 @@ static void dumprom (void *rom, uint32 size) /* return 1 if vblank interrupt has occured */ static int caused_vbi(vuint32 * regs) { - return (NV_REG32(NV32_CRTC_INTS) & 0x00000001); + return (ENG_RG32(RG32_CRTC_INTS) & 0x00000001); } /* clear the vblank interrupt */ static void clear_vbi(vuint32 * regs) { - NV_REG32(NV32_CRTC_INTS) = 0x00000001; + ENG_RG32(RG32_CRTC_INTS) = 0x00000001; } static void enable_vbi(vuint32 * regs) { /* clear the vblank interrupt */ - NV_REG32(NV32_CRTC_INTS) = 0x00000001; + ENG_RG32(RG32_CRTC_INTS) = 0x00000001; /* enable nVidia interrupt source vblank */ - NV_REG32(NV32_CRTC_INTE) |= 0x00000001; + ENG_RG32(RG32_CRTC_INTE) |= 0x00000001; /* enable nVidia interrupt system hardware (b0-1) */ - NV_REG32(NV32_MAIN_INTE) = 0x00000001; + ENG_RG32(RG32_MAIN_INTE) = 0x00000001; } static void disable_vbi(vuint32 * regs) { /* disable nVidia interrupt source vblank */ - NV_REG32(NV32_CRTC_INTE) &= 0xfffffffe; + ENG_RG32(RG32_CRTC_INTE) &= 0xfffffffe; /* clear the vblank interrupt */ - NV_REG32(NV32_CRTC_INTS) = 0x00000001; + ENG_RG32(RG32_CRTC_INTS) = 0x00000001; /* disable nVidia interrupt system hardware (b0-1) */ - NV_REG32(NV32_MAIN_INTE) = 0x00000000; + ENG_RG32(RG32_MAIN_INTE) = 0x00000000; } /* @@ -394,7 +394,7 @@ static status_t map_device(device_info *di) * NV18, NV28 and NV34 keep working. * confirmed NV28 and NV34 to use upper part of shadowed ROM for scratch purposes, * however the actual ROM content (so the used part) is intact (confirmed). */ - //set_pci(NVCFG_ROMSHADOW, 4, 0); + //set_pci(ENCFG_ROMSHADOW, 4, 0); /* get ROM memory mapped base adress - this is defined in the PCI standard */ tmpUlong = get_pci(PCI_rom_base, 4); @@ -851,39 +851,39 @@ control_hook (void* dev, uint32 msg, void *buf, size_t len) { } break; /* PRIVATE ioctl from here on */ - case NV_GET_PRIVATE_DATA: { + case ENG_GET_PRIVATE_DATA: { eng_get_private_data *gpd = (eng_get_private_data *)buf; - if (gpd->magic == NV_PRIVATE_DATA_MAGIC) { + if (gpd->magic == SKEL_PRIVATE_DATA_MAGIC) { gpd->shared_info_area = di->shared_area; result = B_OK; } } break; - case NV_GET_PCI: { + case ENG_GET_PCI: { eng_get_set_pci *gsp = (eng_get_set_pci *)buf; - if (gsp->magic == NV_PRIVATE_DATA_MAGIC) { + if (gsp->magic == SKEL_PRIVATE_DATA_MAGIC) { pci_info *pcii = &(di->pcii); gsp->value = get_pci(gsp->offset, gsp->size); result = B_OK; } } break; - case NV_SET_PCI: { + case ENG_SET_PCI: { eng_get_set_pci *gsp = (eng_get_set_pci *)buf; - if (gsp->magic == NV_PRIVATE_DATA_MAGIC) { + if (gsp->magic == SKEL_PRIVATE_DATA_MAGIC) { pci_info *pcii = &(di->pcii); set_pci(gsp->offset, gsp->size, gsp->value); result = B_OK; } } break; - case NV_DEVICE_NAME: { // apsed + case ENG_DEVICE_NAME: { // apsed eng_device_name *dn = (eng_device_name *)buf; - if (dn->magic == NV_PRIVATE_DATA_MAGIC) { + if (dn->magic == SKEL_PRIVATE_DATA_MAGIC) { strcpy(dn->name, di->name); result = B_OK; } } break; - case NV_RUN_INTERRUPTS: { + case ENG_RUN_INTERRUPTS: { eng_set_bool_state *ri = (eng_set_bool_state *)buf; - if (ri->magic == NV_PRIVATE_DATA_MAGIC) { + if (ri->magic == SKEL_PRIVATE_DATA_MAGIC) { vuint32 *regs = di->regs; if (ri->do_it) { enable_vbi(regs); @@ -893,9 +893,9 @@ control_hook (void* dev, uint32 msg, void *buf, size_t len) { result = B_OK; } } break; - case NV_GET_NTH_AGP_INFO: { + case ENG_GET_NTH_AGP_INFO: { eng_nth_agp_info *nai = (eng_nth_agp_info *)buf; - if (nai->magic == NV_PRIVATE_DATA_MAGIC) { + if (nai->magic == SKEL_PRIVATE_DATA_MAGIC) { nai->exist = false; nai->agp_bus = false; if (agp_bus) { @@ -907,9 +907,9 @@ control_hook (void* dev, uint32 msg, void *buf, size_t len) { result = B_OK; } } break; - case NV_ENABLE_AGP: { + case ENG_ENABLE_AGP: { eng_cmd_agp *nca = (eng_cmd_agp *)buf; - if (nca->magic == NV_PRIVATE_DATA_MAGIC) { + if (nca->magic == SKEL_PRIVATE_DATA_MAGIC) { if (agp_bus) { nca->agp_bus = true; (*agp_bus->enable_agp)(&(nca->cmd)); @@ -920,9 +920,9 @@ control_hook (void* dev, uint32 msg, void *buf, size_t len) { result = B_OK; } } break; - case NV_ISA_OUT: { + case ENG_ISA_OUT: { eng_in_out_isa *io_isa = (eng_in_out_isa *)buf; - if (io_isa->magic == NV_PRIVATE_DATA_MAGIC) { + if (io_isa->magic == SKEL_PRIVATE_DATA_MAGIC) { pci_info *pcii = &(di->pcii); /* lock the driver: @@ -949,9 +949,9 @@ control_hook (void* dev, uint32 msg, void *buf, size_t len) { RELEASE_BEN(pd->kernel); } } break; - case NV_ISA_IN: { + case ENG_ISA_IN: { eng_in_out_isa *io_isa = (eng_in_out_isa *)buf; - if (io_isa->magic == NV_PRIVATE_DATA_MAGIC) { + if (io_isa->magic == SKEL_PRIVATE_DATA_MAGIC) { pci_info *pcii = &(di->pcii); /* lock the driver: