* Work in progress commit of a reworked ATA bus_manager. It's now object based,
but doesn't really do anything more than before. * It also replaces everything IDE with ATA counterparts and cleans up a lot of the definitions. * Cleaning up the old ATA bus_manager as well as some license headers missing. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@30049 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Michael Lotz
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/*
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* Copyright 2002/03, Thomas Kurschel. All rights reserved.
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* Distributed under the terms of the MIT License.
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*/
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#ifndef __ATA_TYPES_H__
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#define __ATA_TYPES_H__
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#include <iovec.h>
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#include <lendian_bitfield.h>
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// ATA task file.
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// contains the command block interpreted under different conditions with
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// first byte being first command register, second byte second command register
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// etc.; for lba48, registers must be written twice, therefore there
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// are twice as many bytes as registers - the first eight bytes are those
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// that must be written first, the second eight bytes are those that
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// must be written second.
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union ata_task_file {
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struct {
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uint8 features;
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uint8 sector_count;
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uint8 sector_number;
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uint8 cylinder_0_7;
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uint8 cylinder_8_15;
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LBITFIELD8_3(
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head : 4,
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device : 1,
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mode : 3
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);
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uint8 command;
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} chs;
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struct {
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uint8 features;
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uint8 sector_count;
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uint8 lba_0_7;
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uint8 lba_8_15;
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uint8 lba_16_23;
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LBITFIELD8_3(
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lba_24_27 : 4,
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device : 1,
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mode : 3
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);
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uint8 command;
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} lba;
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struct {
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LBITFIELD8_3(
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dma : 1,
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ovl : 1,
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_0_res2 : 6
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);
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LBITFIELD8_2(
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_1_res0 : 3,
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tag : 5
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);
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uint8 _2_res;
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uint8 byte_count_0_7;
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uint8 byte_count_8_15;
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LBITFIELD8_6(
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lun : 3,
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_5_res3 : 1,
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device : 1,
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_5_one5 : 1,
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_5_res6 : 1,
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_5_one7 : 1
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);
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uint8 command;
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} packet;
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struct {
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LBITFIELD8_5(
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ili : 1,
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eom : 1,
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abrt : 1,
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_0_res3 : 1,
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sense_key : 4
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);
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LBITFIELD8_4(
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cmd_or_data : 1, // 1 - cmd, 0 - data
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input_or_output : 1, // 0 - input (to device), 1 - output
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release : 1,
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tag : 5
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);
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uint8 _2_res;
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uint8 byte_count_0_7;
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uint8 byte_count_8_15;
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LBITFIELD8_5(
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_4_res0 : 4,
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device : 1,
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_4_obs5 : 1,
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_4_res6 : 1,
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_4_obs7 : 1
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);
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LBITFIELD8_7(
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chk : 1,
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_7_res1 : 2,
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drq : 1,
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serv : 1,
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dmrd : 1,
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drdy : 1,
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bsy : 1
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);
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} packet_res;
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struct {
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uint8 sector_count;
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LBITFIELD8_4( // only <tag> is defined for write
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cmd_or_data : 1, // 1 - cmd, 0 - data
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input_or_output : 1, // 0 - input (to device), 1 - output
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release : 1,
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tag : 5
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);
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uint8 lba_0_7;
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uint8 lba_8_15;
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uint8 lba_16_23;
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LBITFIELD8_3(
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lba_24_27 : 4,
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device : 1,
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mode : 3
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);
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uint8 command;
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} queued;
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struct {
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// low order bytes
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uint8 features;
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uint8 sector_count_0_7;
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uint8 lba_0_7;
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uint8 lba_8_15;
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uint8 lba_16_23;
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LBITFIELD8_3(
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_5low_res0 : 4,
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device : 1,
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mode : 3
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);
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uint8 command;
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// high order bytes
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uint8 _0high_res;
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uint8 sector_count_8_15;
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uint8 lba_24_31;
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uint8 lba_32_39;
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uint8 lba_40_47;
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} lba48;
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struct {
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// low order bytes
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uint8 sector_count_0_7;
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LBITFIELD8_4(
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cmd_or_data : 1, // 1 - cmd, 0 - data
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input_or_output : 1, // 0 - input (to device), 1 - output
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release : 1,
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tag : 5
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);
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uint8 lba_0_7;
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uint8 lba_8_15;
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uint8 lba_16_23;
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LBITFIELD8_3(
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_5low_res0 : 4,
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device : 1,
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mode : 3
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);
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uint8 command;
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// high order bytes
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uint8 sector_count_8_15;
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uint8 _1high_res;
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uint8 lba_24_31;
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uint8 lba_32_39;
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uint8 lba_40_47;
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} queued48;
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struct {
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uint8 r[7+5];
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} raw;
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struct {
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uint8 features;
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uint8 sector_count;
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uint8 sector_number;
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uint8 cylinder_low;
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uint8 cylinder_high;
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uint8 device_head;
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uint8 command;
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} write;
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struct {
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uint8 error;
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uint8 sector_count;
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uint8 sector_number;
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uint8 cylinder_low;
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uint8 cylinder_high;
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uint8 device_head;
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uint8 status;
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} read;
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};
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typedef union ata_task_file ata_task_file;
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// content of "mode" field
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enum {
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ATA_MODE_CHS = 5,
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ATA_MODE_LBA = 7
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};
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// mask for ata_task_file fields to be written
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enum {
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ATA_MASK_FEATURES = 0x01,
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ATA_MASK_SECTOR_COUNT = 0x02,
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// CHS
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ATA_MASK_SECTOR_NUMBER = 0x04,
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ATA_MASK_CYLINDER_LOW = 0x08,
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ATA_MASK_CYLINDER_HIGH = 0x10,
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// LBA
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ATA_MASK_LBA_LOW = 0x04,
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ATA_MASK_LBA_MID = 0x08,
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ATA_MASK_LBA_HIGH = 0x10,
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// packet
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ATA_MASK_BYTE_COUNT = 0x18,
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// packet and dma queued result
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ATA_MASK_ERROR = 0x01,
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ATA_MASK_IREASON = 0x02,
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ATA_MASK_DEVICE_HEAD = 0x20,
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ATA_MASK_COMMAND = 0x40,
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ATA_MASK_STATUS = 0x40,
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// for 48 bits, the following flags tell which registers to load twice
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ATA_MASK_FEATURES_48 = 0x80 | ATA_MASK_FEATURES,
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ATA_MASK_SECTOR_COUNT_48 = 0x100 | ATA_MASK_SECTOR_COUNT,
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ATA_MASK_LBA_LOW_48 = 0x200 | ATA_MASK_LBA_LOW,
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ATA_MASK_LBA_MID_48 = 0x400 | ATA_MASK_LBA_MID,
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ATA_MASK_LBA_HIGH_48 = 0x800 | ATA_MASK_LBA_HIGH,
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ATA_MASK_HOB = 0xf80
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};
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// status register
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enum {
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ATA_STATUS_ERROR = 0x01, // error
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ATA_STATUS_INDEX = 0x02, // obsolete
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ATA_STATUS_CORR = 0x04, // obsolete
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ATA_STATUS_DATA_REQUEST = 0x08, // data request
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ATA_STATUS_DSC = 0x10, // reserved
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ATA_STATUS_SERVICE = 0x10, // ready to service device
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ATA_STATUS_DWF = 0x20, // reserved
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ATA_STATUS_DMA = 0x20, // reserved
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ATA_STATUS_DMA_READY = 0x20, // packet: DMA ready
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ATA_STATUS_DISK_FAILURE = 0x20, // packet: disk failure
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ATA_STATUS_DEVICE_READY = 0x40, // device ready
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ATA_STATUS_BUSY = 0x80 // busy
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};
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// device control register
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enum {
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// bit 0 must be zero
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ATA_DEVICE_CONTROL_DISABLE_INTS = 0x02, // disable INTRQ
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ATA_DEVICE_CONTROL_SOFT_RESET = 0x04, // software device reset
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ATA_DEVICE_CONTROL_BIT3 = 0x08, // don't know, but must be set
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// bits inbetween are reserved
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ATA_DEVICE_CONTROL_HIGH_ORDER_BYTE = 0x80 // read high order byte
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// (for 48-bit lba)
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};
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// error register - most bits are command specific
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enum {
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// always used
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ATA_ERROR_ABORTED = 0x04, // command aborted
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// used for Ultra DMA modes
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ATA_ERROR_INTERFACE_CRC = 0x80, // interface CRC error
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// used by reading data transfers
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ATA_ERROR_UNCORRECTABLE = 0x40, // uncorrectable data error
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// used by writing data transfers
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ATA_ERROR_WRITE_PROTECTED = 0x40, // media write protect
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// used by all data transfer commands
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ATA_ERROR_MEDIUM_CHANGED = 0x20, // medium changed
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ATA_ERROR_INVALID_ADDRESS = 0x10, // invalid CHS address
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ATA_ERROR_MEDIA_CHANGE_REQUESTED = 0x08, // media change requested
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ATA_ERROR_NO_MEDIA = 0x02, // no media
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};
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typedef struct ata_channel_info *ata_channel_cookie;
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#endif /* __ATA_TYPES_H__ */
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