From c657da60853ab3841dcc58abd62b28550d47cd8f Mon Sep 17 00:00:00 2001 From: Rudolf Cornelissen Date: Mon, 13 Sep 2004 11:41:12 +0000 Subject: [PATCH] minor PLL code modifications git-svn-id: file:///srv/svn/repos/haiku/trunk/current@8926 a95241bf-73f2-0310-859d-f6bbb57e9c96 --- .../accelerants/nvidia/engine/nv_dac.c | 11 +++---- .../accelerants/nvidia/engine/nv_dac2.c | 11 +++---- .../accelerants/nvidia/engine/nv_general.c | 4 +-- .../accelerants/nvidia/engine/nv_info.c | 33 ++++++++++++++++++- 4 files changed, 44 insertions(+), 15 deletions(-) diff --git a/src/add-ons/accelerants/nvidia/engine/nv_dac.c b/src/add-ons/accelerants/nvidia/engine/nv_dac.c index 8af9409bc3..12f8e97534 100644 --- a/src/add-ons/accelerants/nvidia/engine/nv_dac.c +++ b/src/add-ons/accelerants/nvidia/engine/nv_dac.c @@ -1,6 +1,6 @@ /* program the DAC */ /* Author: - Rudolf Cornelissen 12/2003-7/2004 + Rudolf Cornelissen 12/2003-9/2004 */ #define MODULE_BIT 0x00010000 @@ -183,8 +183,7 @@ status_t nv_dac_set_pix_pll(display_mode target) DACW(PIXPLLC, ((p << 16) | (n << 8) | m)); /* program 2nd set N and M scalers if they exist (b31=1 enables them) */ - if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) - DACW(PIXPLLC2, 0x80000401); + if (si->ps.ext_pll) DACW(PIXPLLC2, 0x80000401); /* Wait for the PIXPLL frequency to lock until timeout occurs */ //fixme: do NV cards have a LOCK indication bit?? @@ -300,7 +299,7 @@ static status_t nv4_nv10_nv20_dac_pix_pll_find( if ((f_vco >= si->ps.min_pixel_vco) && (f_vco <= si->ps.max_pixel_vco)) { /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ - if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) f_vco /= 4; + if (si->ps.ext_pll) f_vco /= 4; /* iterate trough all valid reference-frequency postscaler settings */ for (m = 7; m <= 14; m++) @@ -323,7 +322,7 @@ static status_t nv4_nv10_nv20_dac_pix_pll_find( if ((n < 1) || (n > 255)) continue; /* find error in frequency this setting gives */ - if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) + if (si->ps.ext_pll) { /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ error = fabs((req_pclk / 4) - (((si->ps.f_ref / m) * n) / p)); @@ -351,7 +350,7 @@ static status_t nv4_nv10_nv20_dac_pix_pll_find( /* log the VCO frequency found */ f_vco = ((si->ps.f_ref / m) * n); /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ - if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) f_vco *= 4; + if (si->ps.ext_pll) f_vco *= 4; LOG(2,("DAC: pix VCO frequency found %fMhz\n", f_vco)); diff --git a/src/add-ons/accelerants/nvidia/engine/nv_dac2.c b/src/add-ons/accelerants/nvidia/engine/nv_dac2.c index 07d7f421bf..cd6f457df1 100644 --- a/src/add-ons/accelerants/nvidia/engine/nv_dac2.c +++ b/src/add-ons/accelerants/nvidia/engine/nv_dac2.c @@ -1,6 +1,6 @@ /* program the secondary DAC */ /* Author: - Rudolf Cornelissen 12/2003-7/2004 + Rudolf Cornelissen 12/2003-9/2004 */ #define MODULE_BIT 0x00001000 @@ -189,8 +189,7 @@ status_t nv_dac2_set_pix_pll(display_mode target) DAC2W(PIXPLLC, ((p << 16) | (n << 8) | m)); /* program 2nd set N and M scalers if they exist (b31=1 enables them) */ - if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) - DAC2W(PIXPLLC2, 0x80000401); + if (si->ps.ext_pll) DAC2W(PIXPLLC2, 0x80000401); /* Wait for the PIXPLL frequency to lock until timeout occurs */ //fixme: do NV cards have a LOCK indication bit?? @@ -306,7 +305,7 @@ static status_t nv10_nv20_dac2_pix_pll_find( if ((f_vco >= si->ps.min_video_vco) && (f_vco <= si->ps.max_video_vco)) { /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ - if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) f_vco /= 4; + if (si->ps.ext_pll) f_vco /= 4; /* iterate trough all valid reference-frequency postscaler settings */ for (m = 7; m <= 14; m++) @@ -328,7 +327,7 @@ static status_t nv10_nv20_dac2_pix_pll_find( if ((n < 1) || (n > 255)) continue; /* find error in frequency this setting gives */ - if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) + if (si->ps.ext_pll) { /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ error = fabs((req_pclk / 4) - (((si->ps.f_ref / m) * n) / p)); @@ -356,7 +355,7 @@ static status_t nv10_nv20_dac2_pix_pll_find( /* log the VCO frequency found */ f_vco = ((si->ps.f_ref / m) * n); /* FX5600 and FX5700 tweak for 2nd set N and M scalers */ - if ((si->ps.card_type == NV31) || (si->ps.card_type == NV36)) f_vco *= 4; + if (si->ps.ext_pll) f_vco *= 4; LOG(2,("DAC2: pix VCO frequency found %fMhz\n", f_vco)); diff --git a/src/add-ons/accelerants/nvidia/engine/nv_general.c b/src/add-ons/accelerants/nvidia/engine/nv_general.c index a07df79f2c..804d82caad 100644 --- a/src/add-ons/accelerants/nvidia/engine/nv_general.c +++ b/src/add-ons/accelerants/nvidia/engine/nv_general.c @@ -1,7 +1,7 @@ /* Authors: Mark Watson 12/1999, Apsed, - Rudolf Cornelissen 10/2002-8/2004 + Rudolf Cornelissen 10/2002-9/2004 */ #define MODULE_BIT 0x00008000 @@ -80,7 +80,7 @@ status_t nv_general_powerup() { status_t status; - LOG(1,("POWERUP: nVidia (open)BeOS Accelerant 0.25 running.\n")); + LOG(1,("POWERUP: nVidia (open)BeOS Accelerant 0.26 running.\n")); /* preset no laptop */ si->ps.laptop = false; diff --git a/src/add-ons/accelerants/nvidia/engine/nv_info.c b/src/add-ons/accelerants/nvidia/engine/nv_info.c index 26d6a0f438..7f632d94ab 100644 --- a/src/add-ons/accelerants/nvidia/engine/nv_info.c +++ b/src/add-ons/accelerants/nvidia/engine/nv_info.c @@ -1,7 +1,7 @@ /* Read initialisation information from card */ /* some bits are hacks, where PINS is not known */ /* Author: - Rudolf Cornelissen 7/2003-8/2004 + Rudolf Cornelissen 7/2003-9/2004 */ #define MODULE_BIT 0x00002000 @@ -160,6 +160,10 @@ static status_t pins3_6_read(uint8 *rom, uint32 offset) LOG(8,("INFO: PLL VCO range is %dkHz - %dkHz\n", fvco_min, fvco_max)); + /* modify presets to reflect card capability */ +// si->ps.min_video_vco = fvco_min / 1000; +// si->ps.max_video_vco = fvco_max / 1000; + /* only pins 5 contains this info */ //fixme: not finished.. /* if ((rom[offset + 5]) == 5) @@ -1428,6 +1432,8 @@ void get_panel_modes(display_mode *p1, display_mode *p2, bool *pan1, bool *pan2) static void pinsnv4_fake(void) { + /* we have a standard PLL */ + si->ps.ext_pll = false; /* carefull not to take to high limits, and high should be >= 2x low. */ si->ps.max_system_vco = 256; si->ps.min_system_vco = 128; @@ -1460,6 +1466,8 @@ static void pinsnv4_fake(void) static void pinsnv5_nv5m64_fake(void) { + /* we have a standard PLL */ + si->ps.ext_pll = false; /* carefull not to take to high limits, and high should be >= 2x low. */ si->ps.max_system_vco = 300; si->ps.min_system_vco = 128; @@ -1492,6 +1500,8 @@ static void pinsnv5_nv5m64_fake(void) static void pinsnv6_fake(void) { + /* we have a standard PLL */ + si->ps.ext_pll = false; /* carefull not to take to high limits, and high should be >= 2x low. */ si->ps.max_system_vco = 300; si->ps.min_system_vco = 128; @@ -1524,6 +1534,8 @@ static void pinsnv6_fake(void) static void pinsnv10_arch_fake(void) { + /* we have a standard PLL */ + si->ps.ext_pll = false; /* carefull not to take to high limits, and high should be >= 2x low. */ si->ps.max_system_vco = 350; si->ps.min_system_vco = 128; @@ -1574,6 +1586,8 @@ static void pinsnv10_arch_fake(void) static void pinsnv20_arch_fake(void) { + /* we have a standard PLL */ + si->ps.ext_pll = false; /* carefull not to take to high limits, and high should be >= 2x low. */ si->ps.max_system_vco = 350; si->ps.min_system_vco = 128; @@ -1608,6 +1622,21 @@ static void pinsnv20_arch_fake(void) static void pinsnv30_arch_fake(void) { + /* determine PLL type */ + LOG(8,("INFO: NV30 architecture chip, PIXPLLC2 DAC1 = $%08x, DAC2 = $%08x\n", + DACR(PIXPLLC2), DAC2R(PIXPLLC2))); + switch (si->ps.card_type) + { + case NV31: + case NV36: + /* we have a extended PLL */ + si->ps.ext_pll = true; + break; + default: + /* we have a standard PLL */ + si->ps.ext_pll = false; + break; + } /* carefull not to take to high limits, and high should be >= 2x low. */ si->ps.max_system_vco = 350; si->ps.min_system_vco = 128; @@ -1794,6 +1823,8 @@ void dump_pins(void) char *msg = ""; LOG(2,("INFO: pinsdump follows:\n")); + LOG(2,("PLL type: ")); + if (si->ps.ext_pll) LOG(2,("extended\n")); else LOG(2,("standard\n")); LOG(2,("f_ref: %fMhz\n", si->ps.f_ref)); LOG(2,("max_system_vco: %dMhz\n", si->ps.max_system_vco)); LOG(2,("min_system_vco: %dMhz\n", si->ps.min_system_vco));