From c6799d8ae170044c80d5bd9284cf43d42f7ef394 Mon Sep 17 00:00:00 2001 From: Alexander von Gluck IV Date: Tue, 3 Apr 2012 09:07:06 -0500 Subject: [PATCH] dp_raw: Continued cleanup of DisplayPort common header * Reduce number of common DP registers in radeon_hd * Move to bitwise shifts as they will make more sense to more people in the long-run --- headers/private/graphics/common/dp_raw.h | 184 ++++++++++-------- .../graphics/radeon_hd/displayport_reg.h | 31 --- .../accelerants/radeon_hd/displayport.cpp | 56 +++--- .../accelerants/radeon_hd/displayport.h | 4 + 4 files changed, 134 insertions(+), 141 deletions(-) diff --git a/headers/private/graphics/common/dp_raw.h b/headers/private/graphics/common/dp_raw.h index 2d717553de..03501cb1ad 100644 --- a/headers/private/graphics/common/dp_raw.h +++ b/headers/private/graphics/common/dp_raw.h @@ -12,21 +12,21 @@ /* ****************************************************** */ /* *** AUX Channel Communications *** */ // Native AUX Communications -#define AUX_NATIVE_WRITE 0x8 -#define AUX_NATIVE_READ 0x9 -#define AUX_NATIVE_REPLY_ACK (0x0 << 4) -#define AUX_NATIVE_REPLY_NACK (0x1 << 4) -#define AUX_NATIVE_REPLY_DEFER (0x2 << 4) -#define AUX_NATIVE_REPLY_MASK (0x3 << 4) +#define AUX_NATIVE_WRITE (8 << 0) +#define AUX_NATIVE_READ (9 << 0) +#define AUX_NATIVE_REPLY_ACK (0 << 4) +#define AUX_NATIVE_REPLY_NACK (1 << 4) +#define AUX_NATIVE_REPLY_DEFER (2 << 4) +#define AUX_NATIVE_REPLY_MASK (3 << 4) // AUX i2c Communications -#define AUX_I2C_WRITE 0x0 -#define AUX_I2C_READ 0x1 -#define AUX_I2C_STATUS 0x2 -#define AUX_I2C_MOT 0x4 -#define AUX_I2C_REPLY_ACK (0x0 << 6) -#define AUX_I2C_REPLY_NACK (0x1 << 6) -#define AUX_I2C_REPLY_DEFER (0x2 << 6) -#define AUX_I2C_REPLY_MASK (0x3 << 6) +#define AUX_I2C_WRITE (0 << 0) +#define AUX_I2C_READ (1 << 0) +#define AUX_I2C_STATUS (2 << 0) +#define AUX_I2C_MOT (4 << 0) +#define AUX_I2C_REPLY_ACK (0 << 6) +#define AUX_I2C_REPLY_NACK (1 << 6) +#define AUX_I2C_REPLY_DEFER (2 << 6) +#define AUX_I2C_REPLY_MASK (3 << 6) /* ****************************************************** */ @@ -36,93 +36,115 @@ /* *** DPCD Receiver Compatibility Field (0x0000) *** */ /* *** VESA DisplayPort Standard, rev 1.1, p112 *** */ // DPCD Version (0x0) -#define DP_DPCD_REV 0x0000 // Reg -#define DP_DPCD_REV_MINOR_MASK 0x000F // Int -#define DP_DPCD_REV_MAJOR_MASK 0x00F0 // Int +#define DP_DPCD_REV 0x0000 // Reg +#define DP_DPCD_REV_MINOR_MASK (15 << 0) // Int +#define DP_DPCD_REV_MAJOR_MASK (15 << 4) // Int +#define DP_DPCD_REV_10 0x0010 // Value +#define DP_DPCD_REV_11 0x0011 // Value // DP Maximum Link Rate (0x1) -#define DP_MAX_LINK_RATE 0x0001 // Reg -#define DP_MAX_LINK_RATE_162 0x0006 // 1.62Ghz -#define DP_MAX_LINK_RATE_270 0x000A // 2.70Ghz -#define DP_MAX_LINK_RATE_540 0x0014 // 5.40Ghz +#define DP_MAX_LINK_RATE 0x0001 // Reg +// Use DP_LINK_RATE_* for speed. // DP Maximum Lane Count (0x2) -#define DP_MAX_LANE_COUNT 0x0002 // Reg -#define DP_MAX_LANE_COUNT_MASK 0x001F // Count -#define DP_ENHANCED_FRAME_CAP_MASK 0x0080 // Bool, Rev 1.1+ +#define DP_MAX_LANE_COUNT 0x0002 // Reg +#define DP_MAX_LANE_COUNT_MASK (31 << 0) // Count +#define DP_MAX_LANE_COUNT_1 (1 << 0) // Value +#define DP_MAX_LANE_COUNT_2 (2 << 0) // Value +#define DP_MAX_LANE_COUNT_4 (4 << 0) // Value +#define DP_ENHANCED_FRAME_CAP_EN (1 << 7) // Bool, Rev 1.1 // DP Maximum Downspread (0x3) -#define DP_MAX_DOWNSPREAD 0x0003 // Reg -#define DP_MAX_DOWNSPREAD_EN_MASK 0x0001 // Bool -#define DP_MAX_DOWNSPREAD_EN_AUX_TRAIN_MASK 0x0040 // Bool +#define DP_MAX_DOWNSPREAD 0x0003 // Reg +#define DP_MAX_DOWNSPREAD_EN (1 << 0) // Bool +#define DP_MAX_DOWNSPREAD_REQ_NO_HANDSHAKE (1 << 6) // Bool // DP Number of Receiver Ports (0x4) -#define DP_NORP 0x0004 // Reg -#define DP_NORP_MASK 0x0001 // Count +#define DP_NORP 0x0004 // Reg +#define DP_NORP_MASK (1 << 0) // Count // DP Downstream Port Present (0x5) -#define DP_DOWNSTREAMPORT 0x0005 // Reg -#define DP_DOWNSTREAMPORT_EN_MASK 0x0001 // Bool -#define DP_DOWNSTREAMPORT_TYPE_MASK 0x0006 // Type -#define DP_DOWNSTREAMPORT_EN_FORMAT_MASK 0x0008 // Bool +#define DP_DOWNSTREAMPORT 0x0005 // Reg +#define DP_DOWNSTREAMPORT_EN (1 << 0) // Bool +#define DP_DOWNSTREAMPORT_TYPE_MASK (3 << 1) // Mask +#define DP_DOWNSTREAMPORT_TYPE_DP (0 << 1) // Value +#define DP_DOWNSTREAMPORT_TYPE_ANALOG (1 << 1) // Value +#define DP_DOWNSTREAMPORT_TYPE_DIGITAL (2 << 1) // Value +#define DP_DOWNSTREAMPORT_TYPE_OTHER (3 << 1) // Value +#define DP_DOWNSTREAMPORT_FORMAT_EN (1 << 3) // Bool // DP Main Link Channel Coding (0x6) -#define DP_CURR_MAIN_CHAN_CODE 0x0006 // Reg -#define DP_CURR_MAIN_CHAN_CODE_EN_ANSI_MASK 0x0001 // Bool +#define DP_CURR_MAIN_CHAN_CODE 0x0006 // Reg +#define DP_CURR_MAIN_CHAN_CODE_ANSIX3_EN (1 << 0) // Bool // DP Downstream Port Count (0x7) (Only 1.1+) -#define DP_DOWNSTREAMPORT_COUNT 0x0007 // Reg -#define DP_DOWNSTREAMPORT_COUNT_MASK 0x000F // Count -#define DP_DOWNSTREAMPORT_COUNT_EN_OUI_MASK 0x0080 // Bool +#define DP_DOWNSTREAMPORT_COUNT 0x0007 // Reg +#define DP_DOWNSTREAMPORT_COUNT_MASK (15 << 0) // Count +#define DP_DOWNSTREAMPORT_COUNT_OUI_EN (1 << 7) // Bool // DP Port Capability 0 -#define DP_PORT0_CAPABILITY0 0x0008 // Reg -#define DP_PORT1_CAPABILITY0 0x000A // Reg -#define DP_PORT_CAPABILITY0_EN_EDID_MASK 0x0002 // Bool -#define DP_PORT_CAPABILITY0_EN_SECOND_MASK 0x0004 // Bool +#define DP_PORT0_CAPABILITY0 0x0008 // Reg +#define DP_PORT1_CAPABILITY0 0x000A // Reg +#define DP_PORT_CAPABILITY0_EDID_EN (1 << 1) // Bool +#define DP_PORT_CAPABILITY0_SECOND_EN (1 << 2) // Bool // DP Port Capability 1 -#define DP_PORT0_CAPABILITY1 0x0009 // Reg -#define DP_PORT1_CAPABILITY1 0x000B // Reg -#define DP_PORT_CAPABILITY1_BUF_SIZE_MASK 0x00FF // Size +#define DP_PORT0_CAPABILITY1 0x0009 // Reg +#define DP_PORT1_CAPABILITY1 0x000B // Reg +#define DP_PORT_CAPABILITY1_BUF_SIZE_MASK (255 << 0) // Size // (value + 1) * 32 bytes per lane /* *** DPCD Link Configuration Field (0x0100) *** */ /* *** VESA DisplayPort Standard, rev 1.1, p117 *** */ // DP Set Link Rate Per Lane (0x0100) -#define DP_LINK_RATE 0x0100 // Reg -#define DP_LINK_RATE_162 0x0006 // 1.62Ghz -#define DP_LINK_RATE_270 0x000A // 2.70Ghz -#define DP_LINK_RATE_540 0x0014 // 5.40Ghz +#define DP_LINK_RATE 0x0100 // Reg +#define DP_LINK_RATE_162 0x0006 // 1.62Ghz +#define DP_LINK_RATE_270 0x000A // 2.70Ghz +#define DP_LINK_RATE_540 0x0014 // 5.40Ghz // DP Set Lane Count (0x0101) -#define DP_LANE_COUNT 0x0101 // Reg -#define DP_LANE_COUNT_MASK 0x001F // Count -#define DP_ENHANCED_FRAME_EN_MASK 0x0080 // Bool, Rev 1.1+ +#define DP_LANE_COUNT 0x0101 // Reg +#define DP_LANE_COUNT_MASK (31 << 0) // Count +#define DP_ENHANCED_FRAME_EN (1 << 7) // Bool, Rev 1.1 // DP Training Pattern (0x0102) -#define DP_LINK_TRAIN 0x0102 // Reg -#define DP_LINK_TRAIN_PATTERN_MASK 0x0003 // Mask -#define DP_LINK_TRAIN_PATTERN_DISABLED 0x0000 // Value -#define DP_LINK_TRAIN_PATTERN_1 0x0001 // Value -#define DP_LINK_TRAIN_PATTERN_2 0x0002 // Value -#define DP_LINK_TRAIN_PATTERN_3 0x0003 // Value -#define DP_LINK_TRAIN_QUAL_MASK 0x000C // Mask -#define DP_LINK_TRAIN_QUAL_NONE 0x0000 // Value -#define DP_LINK_TRAIN_QUAL_D102 0x0004 // Value -#define DP_LINK_TRAIN_QUAL_SYMB_ERR 0x0008 // Value -#define DP_LINK_TRAIN_QUAL_PRBS7 0x000C // Value -#define DP_LINK_TRAIN_CLOCK_RECOVER_EN_MASK 0x0010 // Bool -#define DP_LINK_TRAIN_SCRAMBLE_DI_MASK 0x0020 // Bool (rev) -#define DP_LINK_TRAIN_SYMBL_ERR_SEL_MASK 0x00C0 // Mask +#define DP_TRAIN 0x0102 // Reg +#define DP_TRAIN_PATTERN_MASK (3 << 0) // Mask +#define DP_TRAIN_PATTERN_DISABLED (0 << 0) // Value +#define DP_TRAIN_PATTERN_1 (1 << 0) // Value +#define DP_TRAIN_PATTERN_2 (2 << 0) // Value +#define DP_TRAIN_PATTERN_3 (3 << 0) // Value + +#define DP_TRAIN_QUAL_MASK (3 << 2) // Mask +#define DP_TRAIN_QUAL_NONE (0 << 2) // Value +#define DP_TRAIN_QUAL_D102 (1 << 2) // Value +#define DP_TRAIN_QUAL_SYMB_ERR (2 << 2) // Value +#define DP_TRAIN_QUAL_PRBS7 (3 << 2) // Value + +#define DP_TRAIN_CLOCK_RECOVER_EN (1 << 4) // Bool +#define DP_TRAIN_SCRAMBLE_DI (1 << 5) // Bool (rev) +#define DP_TRAIN_SYMBL_ERR_SEL_MASK (3 << 6) // Mask +#define DP_TRAIN_SYMBL_ERR_SEL_BOTH (0 << 6) // Value +#define DP_TRAIN_SYMBL_ERR_SEL_DISPARITY (1 << 6) // Value +#define DP_TRAIN_SYMBL_ERR_SEL_SYMBOL (2 << 6) // Value // DP Training Lane n (0x0103 - 0x0106) -#define DP_LINK_TRAIN_LANE0 0x0103 // Reg -#define DP_LINK_TRAIN_LANE1 0x0104 // Reg -#define DP_LINK_TRAIN_LANE2 0x0105 // Reg -#define DP_LINK_TRAIN_LANE3 0x0106 // Reg -#define DP_LINK_TRAIN_LANE_VCCSWING_SHIFT 0x0000 // Shift -#define DP_LINK_TRAIN_LANE_VCCSWING_MASK 0x0003 // Mask -#define DP_LINK_TRAIN_LANE_MAXSWING_MASK 0x0004 // Mask -#define DP_LINK_TRAIN_LANE_PREE_MASK 0x0018 // Mask -#define DP_LINK_TRAIN_LANE_PREE_SHIFT 0x0003 // Shift -#define DP_LINK_TRAIN_LANE_MAXPREE_MASK 0x0020 // Mask +#define DP_TRAIN_LANE0 0x0103 // Reg +#define DP_TRAIN_LANE1 0x0104 // Reg +#define DP_TRAIN_LANE2 0x0105 // Reg +#define DP_TRAIN_LANE3 0x0106 // Reg + +#define DP_TRAIN_VCC_SWING_SHIFT (0 << 0) // Shift +#define DP_TRAIN_VCC_SWING_MASK (3 << 0) // Mask +#define DP_TRAIN_VCC_SWING_400 (0 << 0) // Value +#define DP_TRAIN_VCC_SWING_600 (1 << 0) // Value +#define DP_TRAIN_VCC_SWING_800 (2 << 0) // Value +#define DP_TRAIN_VCC_SWING_1200 (3 << 0) // Value +#define DP_TRAIN_MAX_SWING_EN (1 << 2) // Bool + +#define DP_TRAIN_PRE_EMPHASIS_SHIFT (3 << 0) // Shift +#define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) // Mask +#define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3) // Value +#define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3) // Value +#define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3) // Value +#define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3) // Value +#define DP_TRAIN_MAX_EMPHASIS_EN (1 << 5) // Bool // DP Down-spread Control (0x0107) -#define DP_DOWNSPREAD_CTRL 0x0107 // Reg -#define DP_DOWNSPREAD_CTRL_FREQ_MASK 0x0001 // Int -#define DP_DOWNSPREAD_CTRL_AMP_EN 0x0010 // Int +#define DP_DOWNSPREAD_CTRL 0x0107 // Reg +#define DP_DOWNSPREAD_CTRL_FREQ_MASK (1 << 0) // Int +#define DP_DOWNSPREAD_CTRL_AMP_EN (1 << 4) // Int // DP Main Link Channel Coding (0x0108) -#define DP_MAIN_CHAN_CODE 0x0108 // Reg -#define DP_MAIN_CHAN_CODE_EN_ANSI_MASK 0x0001 // Bool +#define DP_MAIN_CHAN_CODE 0x0108 // Reg +#define DP_MAIN_CHAN_CODE_ANSIX3_EN (1 << 0) // Bool /* *** DPCD Link / Sink Status Field (0x0200) *** */ /* *** VESA DisplayPort Standard, rev 1.1, p120 *** */ diff --git a/headers/private/graphics/radeon_hd/displayport_reg.h b/headers/private/graphics/radeon_hd/displayport_reg.h index e7b5024ae2..c0b8b97117 100644 --- a/headers/private/graphics/radeon_hd/displayport_reg.h +++ b/headers/private/graphics/radeon_hd/displayport_reg.h @@ -18,37 +18,6 @@ #define DP_TPS3_SUPPORTED (1 << 6) -#define DP_FORMAT_CONVERSION (1 << 3) - -#define DP_TRAINING_AUX_RD_INTERVAL 0x00e - -#define DP_LINK_QUAL_PATTERN_DISABLE (0 << 2) -#define DP_LINK_QUAL_PATTERN_D10_2 (1 << 2) -#define DP_LINK_QUAL_PATTERN_ERROR_RATE (2 << 2) -#define DP_LINK_QUAL_PATTERN_PRBS7 (3 << 2) -#define DP_LINK_QUAL_PATTERN_MASK (3 << 2) - -#define DP_SYMBOL_ERROR_COUNT_BOTH (0 << 6) -#define DP_SYMBOL_ERROR_COUNT_DISPARITY (1 << 6) -#define DP_SYMBOL_ERROR_COUNT_SYMBOL (2 << 6) -#define DP_SYMBOL_ERROR_COUNT_MASK (3 << 6) - -#define DP_TRAIN_VOLTAGE_SWING_MASK 0x3 -#define DP_TRAIN_VOLTAGE_SWING_SHIFT 0 -#define DP_TRAIN_MAX_SWING_REACHED (1 << 2) -#define DP_TRAIN_VOLTAGE_SWING_400 (0 << 0) -#define DP_TRAIN_VOLTAGE_SWING_600 (1 << 0) -#define DP_TRAIN_VOLTAGE_SWING_800 (2 << 0) -#define DP_TRAIN_VOLTAGE_SWING_1200 (3 << 0) - -#define DP_TRAIN_PRE_EMPHASIS_MASK (3 << 3) -#define DP_TRAIN_PRE_EMPHASIS_0 (0 << 3) -#define DP_TRAIN_PRE_EMPHASIS_3_5 (1 << 3) -#define DP_TRAIN_PRE_EMPHASIS_6 (2 << 3) -#define DP_TRAIN_PRE_EMPHASIS_9_5 (3 << 3) - -#define DP_TRAIN_MAX_PRE_EMPHASIS_REACHED (1 << 5) - #define DP_LANE0_1_STATUS 0x202 #define DP_LANE2_3_STATUS 0x203 #define DP_LANE_CR_DONE (1 << 0) diff --git a/src/add-ons/accelerants/radeon_hd/displayport.cpp b/src/add-ons/accelerants/radeon_hd/displayport.cpp index 8840989af2..0a75deb471 100644 --- a/src/add-ons/accelerants/radeon_hd/displayport.cpp +++ b/src/add-ons/accelerants/radeon_hd/displayport.cpp @@ -470,7 +470,7 @@ dp_update_vs_emph(dp_info* dp) ATOM_TRANSMITTER_ACTION_SETUP_VSEMPH); // Set vs and emph on the sink - dp_aux_write(dp->auxPin, DP_LINK_TRAIN_LANE0, + dp_aux_write(dp->auxPin, DP_TRAIN_LANE0, dp->trainingSet, dp->laneCount, 0); } @@ -483,7 +483,7 @@ dp_get_adjust_request_voltage(dp_info* dp, int lane) : DP_ADJUST_VOLTAGE_SWING_LANE0_SHIFT); uint8 l = dp->linkStatus[i - DP_LANE0_1_STATUS]; - return ((l >> s) & 0x3) << DP_LINK_TRAIN_LANE_VCCSWING_SHIFT; + return ((l >> s) & 0x3) << DP_TRAIN_VCC_SWING_SHIFT; } @@ -495,14 +495,10 @@ dp_get_adjust_request_pre_emphasis(dp_info* dp, int lane) : DP_ADJUST_PRE_EMPHASIS_LANE0_SHIFT); uint8 l = dp->linkStatus[i - DP_LANE0_1_STATUS]; - return ((l >> s) & 0x3) << DP_LINK_TRAIN_LANE_PREE_SHIFT; + return ((l >> s) & 0x3) << DP_TRAIN_PRE_EMPHASIS_SHIFT; } -#define DP_VOLTAGE_MAX DP_TRAIN_VOLTAGE_SWING_1200 -#define DP_PRE_EMPHASIS_MAX DP_TRAIN_PRE_EMPHASIS_9_5 - - static void dp_get_adjust_train(dp_info* dp) { @@ -524,8 +520,8 @@ dp_get_adjust_train(dp_info* dp) uint8 lanePreEmphasis = dp_get_adjust_request_pre_emphasis(dp, lane); TRACE("%s: Requested %s at %s for lane %d\n", __func__, - preEmphasisNames[lanePreEmphasis >> DP_LINK_TRAIN_LANE_PREE_SHIFT], - voltageNames[laneVoltage >> DP_LINK_TRAIN_LANE_VCCSWING_SHIFT], + preEmphasisNames[lanePreEmphasis >> DP_TRAIN_PRE_EMPHASIS_SHIFT], + voltageNames[laneVoltage >> DP_TRAIN_VCC_SWING_SHIFT], lane); if (laneVoltage > voltage) @@ -534,11 +530,13 @@ dp_get_adjust_train(dp_info* dp) preEmphasis = lanePreEmphasis; } - if (voltage >= DP_VOLTAGE_MAX) - voltage |= DP_TRAIN_MAX_SWING_REACHED; + // Check for maximum voltage and toggle max if reached + if (voltage >= DP_TRAIN_VCC_SWING_1200) + voltage |= DP_TRAIN_MAX_SWING_EN; - if (preEmphasis >= DP_PRE_EMPHASIS_MAX) - preEmphasis |= DP_TRAIN_MAX_PRE_EMPHASIS_REACHED; + // Check for maximum pre-emphasis and toggle max if reached + if (preEmphasis >= DP_TRAIN_PRE_EMPHASIS_9_5) + preEmphasis |= DP_TRAIN_MAX_EMPHASIS_EN; for (lane = 0; lane < 4; lane++) dp->trainingSet[lane] = voltage | preEmphasis; @@ -557,13 +555,13 @@ dp_set_tp(dp_info* dp, int trainingPattern) /* set training pattern on the source */ if (info.dceMajor >= 4 || !dp->trainingUseEncoder) { switch (trainingPattern) { - case DP_LINK_TRAIN_PATTERN_1: + case DP_TRAIN_PATTERN_1: rawTrainingPattern = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN1; break; - case DP_LINK_TRAIN_PATTERN_2: + case DP_TRAIN_PATTERN_2: rawTrainingPattern = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN2; break; - case DP_LINK_TRAIN_PATTERN_3: + case DP_TRAIN_PATTERN_3: rawTrainingPattern = ATOM_ENCODER_CMD_DP_LINK_TRAINING_PATTERN3; break; } @@ -588,7 +586,7 @@ dp_set_tp(dp_info* dp, int trainingPattern) } // Enable training pattern on the sink - dpcd_reg_write(dp->auxPin, DP_LINK_TRAIN, trainingPattern); + dpcd_reg_write(dp->auxPin, DP_TRAIN, trainingPattern); } @@ -603,7 +601,7 @@ dp_link_train_cr(dp_info* dp) uint8 voltage = 0xff; int lane; - dp_set_tp(dp, DP_LINK_TRAIN_PATTERN_1); + dp_set_tp(dp, DP_TRAIN_PATTERN_1); memset(dp->trainingSet, 0, 4); dp_update_vs_emph(dp); @@ -622,7 +620,7 @@ dp_link_train_cr(dp_info* dp) } for (lane = 0; lane < dp->laneCount; lane++) { - if ((dp->trainingSet[lane] & DP_TRAIN_MAX_SWING_REACHED) == 0) + if ((dp->trainingSet[lane] & DP_TRAIN_MAX_SWING_EN) == 0) break; } @@ -631,7 +629,7 @@ dp_link_train_cr(dp_info* dp) break; } - if ((dp->trainingSet[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { + if ((dp->trainingSet[0] & DP_TRAIN_VCC_SWING_MASK) == voltage) { dp->trainingAttempts++; if (dp->trainingAttempts >= 5) { ERROR("%s: clock recovery tried 5 times\n", __func__); @@ -640,7 +638,7 @@ dp_link_train_cr(dp_info* dp) } else dp->trainingAttempts = 0; - voltage = dp->trainingSet[0] & DP_TRAIN_VOLTAGE_SWING_MASK; + voltage = dp->trainingSet[0] & DP_TRAIN_VCC_SWING_MASK; // Compute new trainingSet as requested by sink dp_get_adjust_train(dp); @@ -654,9 +652,9 @@ dp_link_train_cr(dp_info* dp) } TRACE("%s: clock recovery at voltage %d pre-emphasis %d\n", - __func__, dp->trainingSet[0] & DP_TRAIN_VOLTAGE_SWING_MASK, - (dp->trainingSet[0] & DP_LINK_TRAIN_LANE_PREE_MASK) - >> DP_LINK_TRAIN_LANE_PREE_SHIFT); + __func__, dp->trainingSet[0] & DP_TRAIN_VCC_SWING_MASK, + (dp->trainingSet[0] & DP_TRAIN_PRE_EMPHASIS_MASK) + >> DP_TRAIN_PRE_EMPHASIS_SHIFT); return B_OK; } @@ -718,7 +716,7 @@ dp_link_train(uint8 crtcID, display_mode* mode) // *** DisplayPort link training initialization // Power up the DP sink - if (dp->config[0] >= 0x11) + if (dp->config[0] >= DP_DPCD_REV_11) dpcd_reg_write(hwPin, DP_SET_POWER, DP_SET_POWER_D0); // Possibly enable downspread on the sink @@ -730,8 +728,8 @@ dp_link_train(uint8 crtcID, display_mode* mode) encoder_dig_setup(connectorIndex, mode->timing.pixel_clock, ATOM_ENCODER_CMD_SETUP_PANEL_MODE); - if (dp->config[0] >= 0x11) - sandbox |= DP_ENHANCED_FRAME_EN_MASK; + if (dp->config[0] >= DP_DPCD_REV_11) + sandbox |= DP_ENHANCED_FRAME_EN; dpcd_reg_write(hwPin, DP_LANE_COUNT, sandbox); // Set the link rate on the DP sink @@ -748,7 +746,7 @@ dp_link_train(uint8 crtcID, display_mode* mode) } // Disable the training pattern on the sink - dpcd_reg_write(hwPin, DP_LINK_TRAIN, DP_LINK_TRAIN_PATTERN_DISABLED); + dpcd_reg_write(hwPin, DP_TRAIN, DP_TRAIN_PATTERN_DISABLED); dp_link_train_cr(dp); // TODO: dp_link_train_ce @@ -758,7 +756,7 @@ dp_link_train(uint8 crtcID, display_mode* mode) snooze(400); // Disable the training pattern on the sink - dpcd_reg_write(hwPin, DP_LINK_TRAIN, DP_LINK_TRAIN_PATTERN_DISABLED); + dpcd_reg_write(hwPin, DP_TRAIN, DP_TRAIN_PATTERN_DISABLED); // Disable the training pattern on the source if (info.dceMajor >= 4 || !dp->trainingUseEncoder) { diff --git a/src/add-ons/accelerants/radeon_hd/displayport.h b/src/add-ons/accelerants/radeon_hd/displayport.h index dff3f36b58..c5fb60492f 100644 --- a/src/add-ons/accelerants/radeon_hd/displayport.h +++ b/src/add-ons/accelerants/radeon_hd/displayport.h @@ -17,6 +17,10 @@ #include "displayport_reg.h" +// Radeon HD specific DisplayPort Configuration Data +#define DP_TRAINING_AUX_RD_INTERVAL 0x000e + + int dp_aux_write(uint32 hwPin, uint16 address, uint8* send, uint8 sendBytes, uint8 delay); int dp_aux_read(uint32 hwPin, uint16 address, uint8* recv,