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kernel/x86_64: on context switch, load defaults in fpu control and mxcsr

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after a0131eaae2884fdced27158c3d34732d1656aca9 mxcsr was possibly also incorrect.
fpu control and mxcsr will be restored with fxrstor/xrstor.
no need to clear pending exceptions on #MF
fix #18656 (and #18624 after reverting).

Change-Id: I7dd5e2e4610747c5b82abd6c67e302d264b4be92
Reviewed-on: https://review.haiku-os.org/c/haiku/+/7104
Tested-by: Commit checker robot <[email protected]>
Reviewed-by: waddlesplash <[email protected]>
This commit is contained in:
Jérôme Duval
2023-11-14 21:31:01 +00:00
committed by waddlesplash
parent 345265c3d6
commit c7360f4b02
3 changed files with 10 additions and 11 deletions
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headers/private/kernel/arch/x86/64/cpu.h
+6 -8
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@@ -9,6 +9,10 @@
#include <arch_thread_types.h>
extern uint16 gFPUControlDefault;
extern uint32 gFPUMXCSRDefault;
static inline uint64_t
x86_read_msr(uint32_t msr)
{
@@ -28,10 +32,6 @@ x86_write_msr(uint32_t msr, uint64_t value)
static inline void
x86_context_switch(arch_thread* oldState, arch_thread* newState)
{
uint16_t fpuControl;
asm volatile("fnstcw %0" : "=m" (fpuControl));
uint32_t sseControl;
asm volatile("stmxcsr %0" : "=m" (sseControl));
asm volatile(
"pushq %%rbp;"
"movq $1f, %c[rip](%0);"
@@ -48,10 +48,8 @@ x86_context_switch(arch_thread* oldState, arch_thread* newState)
"r14", "r15", "xmm0", "xmm1", "xmm2", "xmm3", "xmm4", "xmm5",
"xmm6", "xmm7", "xmm8", "xmm9", "xmm10", "xmm11", "xmm12", "xmm13",
"xmm14", "xmm15", "memory");
// so that x87 FPU floating-point instructions can be executed
asm volatile("emms");
asm volatile("ldmxcsr %0" : : "m" (sseControl));
asm volatile("fldcw %0" : : "m" (fpuControl));
asm volatile("ldmxcsr %0" : : "m" (gFPUMXCSRDefault));
asm volatile("fldcw %0" : : "m" (gFPUControlDefault));
}