From c788baed28e28960c17306fe9f5b40382b07cb1d Mon Sep 17 00:00:00 2001 From: Michael Lotz Date: Sun, 16 Oct 2011 15:15:03 +0000 Subject: [PATCH] Style cleanups only, no functional change. * Make the pointer style consistent accross all components, which should make it easier when working all over the place. * 80 char limits. git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@42863 a95241bf-73f2-0310-859d-f6bbb57e9c96 --- .../graphics/intel_extreme/intel_extreme.h | 3 +- .../accelerants/intel_extreme/accelerant.cpp | 28 +++--- .../accelerants/intel_extreme/accelerant.h | 18 ++-- .../intel_extreme/accelerant_protos.h | 75 ++++++++-------- .../accelerants/intel_extreme/commands.h | 2 +- .../accelerants/intel_extreme/cursor.cpp | 16 ++-- .../accelerants/intel_extreme/dpms.cpp | 60 ++++++++----- .../accelerants/intel_extreme/engine.cpp | 24 +++--- .../accelerants/intel_extreme/hooks.cpp | 4 +- .../accelerants/intel_extreme/memory.cpp | 2 +- .../accelerants/intel_extreme/mode.cpp | 74 +++++++++------- .../accelerants/intel_extreme/overlay.cpp | 85 ++++++++++--------- .../kernel/busses/agp_gart/intel_gart.cpp | 61 ++++++------- .../drivers/graphics/intel_extreme/device.cpp | 53 ++++++------ .../drivers/graphics/intel_extreme/driver.cpp | 10 +-- .../drivers/graphics/intel_extreme/driver.h | 8 +- .../graphics/intel_extreme/intel_extreme.cpp | 40 ++++----- 17 files changed, 314 insertions(+), 249 deletions(-) diff --git a/headers/private/graphics/intel_extreme/intel_extreme.h b/headers/private/graphics/intel_extreme/intel_extreme.h index a5e8f86bf0..d4828d13ab 100644 --- a/headers/private/graphics/intel_extreme/intel_extreme.h +++ b/headers/private/graphics/intel_extreme/intel_extreme.h @@ -227,7 +227,8 @@ struct intel_free_graphics_memory { // Register definitions, taken from X driver // PCI bridge memory management -#define INTEL_GRAPHICS_MEMORY_CONTROL 0x52 // GGC - (G)MCH Graphics Control Register +#define INTEL_GRAPHICS_MEMORY_CONTROL 0x52 + // GGC - (G)MCH Graphics Control Register #define MEMORY_CONTROL_ENABLED 0x0004 #define MEMORY_MASK 0x0001 #define STOLEN_MEMORY_MASK 0x00f0 diff --git a/src/add-ons/accelerants/intel_extreme/accelerant.cpp b/src/add-ons/accelerants/intel_extreme/accelerant.cpp index 3d9b0023cf..465f9b6fde 100644 --- a/src/add-ons/accelerants/intel_extreme/accelerant.cpp +++ b/src/add-ons/accelerants/intel_extreme/accelerant.cpp @@ -23,14 +23,14 @@ #define TRACE_ACCELERANT #ifdef TRACE_ACCELERANT -extern "C" void _sPrintf(const char *format, ...); +extern "C" void _sPrintf(const char* format, ...); # define TRACE(x) _sPrintf x #else # define TRACE(x) ; #endif -struct accelerant_info *gInfo; +struct accelerant_info* gInfo; class AreaCloner { @@ -38,7 +38,7 @@ public: AreaCloner(); ~AreaCloner(); - area_id Clone(const char *name, void **_address, + area_id Clone(const char* name, void** _address, uint32 spec, uint32 protection, area_id sourceArea); status_t InitCheck() @@ -65,7 +65,7 @@ AreaCloner::~AreaCloner() area_id -AreaCloner::Clone(const char *name, void **_address, uint32 spec, +AreaCloner::Clone(const char* name, void** _address, uint32 spec, uint32 protection, area_id sourceArea) { fArea = clone_area(name, _address, spec, protection, sourceArea); @@ -91,7 +91,7 @@ init_common(int device, bool isClone) { // initialize global accelerant info structure - gInfo = (accelerant_info *)malloc(sizeof(accelerant_info)); + gInfo = (accelerant_info*)malloc(sizeof(accelerant_info)); if (gInfo == NULL) return B_NO_MEMORY; @@ -113,7 +113,7 @@ init_common(int device, bool isClone) AreaCloner sharedCloner; gInfo->shared_info_area = sharedCloner.Clone("intel extreme shared info", - (void **)&gInfo->shared_info, B_ANY_ADDRESS, B_READ_AREA | B_WRITE_AREA, + (void**)&gInfo->shared_info, B_ANY_ADDRESS, B_READ_AREA | B_WRITE_AREA, data.shared_info_area); status_t status = sharedCloner.InitCheck(); if (status < B_OK) { @@ -123,7 +123,7 @@ init_common(int device, bool isClone) AreaCloner regsCloner; gInfo->regs_area = regsCloner.Clone("intel extreme regs", - (void **)&gInfo->registers, B_ANY_ADDRESS, B_READ_AREA | B_WRITE_AREA, + (void**)&gInfo->registers, B_ANY_ADDRESS, B_READ_AREA | B_WRITE_AREA, gInfo->shared_info->registers_area); status = regsCloner.InitCheck(); if (status < B_OK) { @@ -137,7 +137,7 @@ init_common(int device, bool isClone) // The overlay registers, hardware status, and cursor memory share // a single area with the shared_info - gInfo->overlay_registers = (struct overlay_registers *) + gInfo->overlay_registers = (struct overlay_registers*) (gInfo->shared_info->graphics_memory + gInfo->shared_info->overlay_offset); @@ -242,7 +242,7 @@ intel_accelerant_clone_info_size(void) void -intel_get_accelerant_clone_info(void *info) +intel_get_accelerant_clone_info(void* info) { TRACE(("intel_get_accelerant_clone_info()\n")); ioctl(gInfo->device, INTEL_GET_DEVICE_NAME, info, B_PATH_NAME_LENGTH); @@ -250,7 +250,7 @@ intel_get_accelerant_clone_info(void *info) status_t -intel_clone_accelerant(void *info) +intel_clone_accelerant(void* info) { TRACE(("intel_clone_accelerant()\n")); @@ -258,9 +258,9 @@ intel_clone_accelerant(void *info) char path[B_PATH_NAME_LENGTH]; strcpy(path, "/dev/"); #ifdef __HAIKU__ - strlcat(path, (const char *)info, sizeof(path)); + strlcat(path, (const char*)info, sizeof(path)); #else - strcat(path, (const char *)info); + strcat(path, (const char*)info); #endif int fd = open(path, B_READ_WRITE); @@ -273,7 +273,7 @@ intel_clone_accelerant(void *info) // get read-only clone of supported display modes status = gInfo->mode_list_area = clone_area( - "intel extreme cloned modes", (void **)&gInfo->mode_list, + "intel extreme cloned modes", (void**)&gInfo->mode_list, B_ANY_ADDRESS, B_READ_AREA, gInfo->shared_info->mode_list_area); if (status < B_OK) goto err2; @@ -312,7 +312,7 @@ intel_uninit_accelerant(void) status_t -intel_get_accelerant_device_info(accelerant_device_info *info) +intel_get_accelerant_device_info(accelerant_device_info* info) { TRACE(("intel_get_accelerant_device_info()\n")); diff --git a/src/add-ons/accelerants/intel_extreme/accelerant.h b/src/add-ons/accelerants/intel_extreme/accelerant.h index a0216a9115..1f8aa4523c 100644 --- a/src/add-ons/accelerants/intel_extreme/accelerant.h +++ b/src/add-ons/accelerants/intel_extreme/accelerant.h @@ -31,17 +31,17 @@ struct overlay_frame { }; struct accelerant_info { - uint8 *registers; + uint8* registers; area_id regs_area; - intel_shared_info *shared_info; + intel_shared_info* shared_info; area_id shared_info_area; - display_mode *mode_list; // cloned list of standard display modes + display_mode* mode_list; // cloned list of standard display modes area_id mode_list_area; - struct overlay_registers *overlay_registers; - overlay *current_overlay; + struct overlay_registers* overlay_registers; + overlay* current_overlay; overlay_view last_overlay_view; overlay_frame last_overlay_frame; uint32 last_horizontal_overlay_scale; @@ -69,14 +69,14 @@ struct accelerant_info { #define HEAD_MODE_CLONE 0x03 #define HEAD_MODE_LVDS_PANEL 0x08 -extern accelerant_info *gInfo; +extern accelerant_info* gInfo; // register access inline uint32 read32(uint32 encodedRegister) { - return *(volatile uint32 *)(gInfo->registers + return *(volatile uint32*)(gInfo->registers + gInfo->shared_info->register_blocks[REGISTER_BLOCK(encodedRegister)] + REGISTER_REGISTER(encodedRegister)); } @@ -84,7 +84,7 @@ read32(uint32 encodedRegister) inline void write32(uint32 encodedRegister, uint32 value) { - *(volatile uint32 *)(gInfo->registers + *(volatile uint32*)(gInfo->registers + gInfo->shared_info->register_blocks[REGISTER_BLOCK(encodedRegister)] + REGISTER_REGISTER(encodedRegister)) = value; } @@ -96,7 +96,7 @@ extern void set_display_power_mode(uint32 mode); // engine.cpp extern void uninit_ring_buffer(ring_buffer &ringBuffer); -extern void setup_ring_buffer(ring_buffer &ringBuffer, const char *name); +extern void setup_ring_buffer(ring_buffer &ringBuffer, const char* name); // modes.cpp extern void wait_for_vblank(void); diff --git a/src/add-ons/accelerants/intel_extreme/accelerant_protos.h b/src/add-ons/accelerants/intel_extreme/accelerant_protos.h index 2768ee6483..fc7031d77d 100644 --- a/src/add-ons/accelerants/intel_extreme/accelerant_protos.h +++ b/src/add-ons/accelerants/intel_extreme/accelerant_protos.h @@ -22,25 +22,27 @@ void spin(bigtime_t delay); // general status_t intel_init_accelerant(int fd); ssize_t intel_accelerant_clone_info_size(void); -void intel_get_accelerant_clone_info(void *data); -status_t intel_clone_accelerant(void *data); +void intel_get_accelerant_clone_info(void* data); +status_t intel_clone_accelerant(void* data); void intel_uninit_accelerant(void); -status_t intel_get_accelerant_device_info(accelerant_device_info *info); +status_t intel_get_accelerant_device_info(accelerant_device_info* info); sem_id intel_accelerant_retrace_semaphore(void); // modes & constraints uint32 intel_accelerant_mode_count(void); -status_t intel_get_mode_list(display_mode *dm); -status_t intel_propose_display_mode(display_mode *target, const display_mode *low, - const display_mode *high); -status_t intel_set_display_mode(display_mode *mode); -status_t intel_get_display_mode(display_mode *currentMode); +status_t intel_get_mode_list(display_mode* dm); +status_t intel_propose_display_mode(display_mode* target, + const display_mode* low, const display_mode* high); +status_t intel_set_display_mode(display_mode* mode); +status_t intel_get_display_mode(display_mode* currentMode); status_t intel_get_edid_info(void* info, size_t size, uint32* _version); -status_t intel_get_frame_buffer_config(frame_buffer_config *config); -status_t intel_get_pixel_clock_limits(display_mode *mode, uint32 *low, uint32 *high); +status_t intel_get_frame_buffer_config(frame_buffer_config* config); +status_t intel_get_pixel_clock_limits(display_mode* mode, uint32* low, + uint32* high); status_t intel_move_display(uint16 hDisplayStart, uint16 vDisplayStart); -status_t intel_get_timing_constraints(display_timing_constraints *constraints); -void intel_set_indexed_colors(uint count, uint8 first, uint8 *colorData, uint32 flags); +status_t intel_get_timing_constraints(display_timing_constraints* constraints); +void intel_set_indexed_colors(uint count, uint8 first, uint8* colorData, + uint32 flags); // DPMS uint32 intel_dpms_capabilities(void); @@ -48,42 +50,47 @@ uint32 intel_dpms_mode(void); status_t intel_set_dpms_mode(uint32 flags); // cursor -status_t intel_set_cursor_shape(uint16 width, uint16 height, uint16 hotX, uint16 hotY, - uint8 *andMask, uint8 *xorMask); +status_t intel_set_cursor_shape(uint16 width, uint16 height, uint16 hotX, + uint16 hotY, uint8* andMask, uint8* xorMask); void intel_move_cursor(uint16 x, uint16 y); void intel_show_cursor(bool isVisible); // accelerant engine uint32 intel_accelerant_engine_count(void); status_t intel_acquire_engine(uint32 capabilities, uint32 maxWait, - sync_token *syncToken, engine_token **_engineToken); -status_t intel_release_engine(engine_token *engineToken, sync_token *syncToken); + sync_token* syncToken, engine_token** _engineToken); +status_t intel_release_engine(engine_token* engineToken, sync_token* syncToken); void intel_wait_engine_idle(void); -status_t intel_get_sync_token(engine_token *engineToken, sync_token *syncToken); -status_t intel_sync_to_token(sync_token *syncToken); +status_t intel_get_sync_token(engine_token* engineToken, sync_token* syncToken); +status_t intel_sync_to_token(sync_token* syncToken); // 2D acceleration -void intel_screen_to_screen_blit(engine_token *engineToken, blit_params *list, uint32 count); -void intel_fill_rectangle(engine_token *engineToken, uint32 color, fill_rect_params *list, - uint32 count); -void intel_invert_rectangle(engine_token *engineToken, fill_rect_params *list, uint32 count); -void intel_fill_span(engine_token *engineToken, uint32 color, uint16 *list, uint32 count); +void intel_screen_to_screen_blit(engine_token* engineToken, + blit_params* list, uint32 count); +void intel_fill_rectangle(engine_token* engineToken, uint32 color, + fill_rect_params* list, uint32 count); +void intel_invert_rectangle(engine_token* engineToken, fill_rect_params* list, + uint32 count); +void intel_fill_span(engine_token* engineToken, uint32 color, uint16* list, + uint32 count); // overlay -uint32 intel_overlay_count(const display_mode *mode); -const uint32 *intel_overlay_supported_spaces(const display_mode *mode); +uint32 intel_overlay_count(const display_mode* mode); +const uint32* intel_overlay_supported_spaces(const display_mode* mode); uint32 intel_overlay_supported_features(uint32 colorSpace); -const overlay_buffer *intel_allocate_overlay_buffer(color_space space, uint16 width, - uint16 height); -status_t intel_release_overlay_buffer(const overlay_buffer *buffer); -status_t intel_get_overlay_constraints(const display_mode *mode, const overlay_buffer *buffer, - overlay_constraints *constraints); +const overlay_buffer* intel_allocate_overlay_buffer(color_space space, + uint16 width, uint16 height); +status_t intel_release_overlay_buffer(const overlay_buffer* buffer); +status_t intel_get_overlay_constraints(const display_mode* mode, + const overlay_buffer* buffer, overlay_constraints* constraints); overlay_token intel_allocate_overlay(void); status_t intel_release_overlay(overlay_token overlayToken); -status_t intel_configure_overlay(overlay_token overlayToken, const overlay_buffer *buffer, - const overlay_window *window, const overlay_view *view); -status_t i965_configure_overlay(overlay_token overlayToken, const overlay_buffer *buffer, - const overlay_window *window, const overlay_view *view); +status_t intel_configure_overlay(overlay_token overlayToken, + const overlay_buffer* buffer, const overlay_window* window, + const overlay_view* view); +status_t i965_configure_overlay(overlay_token overlayToken, + const overlay_buffer* buffer, const overlay_window* window, + const overlay_view* view); #ifdef __cplusplus } diff --git a/src/add-ons/accelerants/intel_extreme/commands.h b/src/add-ons/accelerants/intel_extreme/commands.h index f0b04f15a1..094c5e21ab 100644 --- a/src/add-ons/accelerants/intel_extreme/commands.h +++ b/src/add-ons/accelerants/intel_extreme/commands.h @@ -15,7 +15,7 @@ struct command { uint32 opcode; - uint32 *Data() { return &opcode; } + uint32* Data() { return &opcode; } }; class QueueCommands { diff --git a/src/add-ons/accelerants/intel_extreme/cursor.cpp b/src/add-ons/accelerants/intel_extreme/cursor.cpp index 793c96d191..5ab49b0f29 100644 --- a/src/add-ons/accelerants/intel_extreme/cursor.cpp +++ b/src/add-ons/accelerants/intel_extreme/cursor.cpp @@ -15,7 +15,7 @@ status_t intel_set_cursor_shape(uint16 width, uint16 height, uint16 hotX, uint16 hotY, - uint8 *andMask, uint8 *xorMask) + uint8* andMask, uint8* xorMask) { if (width > 64 || height > 64) return B_BAD_VALUE; @@ -23,7 +23,8 @@ intel_set_cursor_shape(uint16 width, uint16 height, uint16 hotX, uint16 hotY, write32(INTEL_CURSOR_CONTROL, 0); // disable cursor - // In two-color mode, the data is ordered as follows (always 64 bit per line): + // In two-color mode, the data is ordered as follows (always 64 bit per + // line): // plane 1: line 0 (AND mask) // plane 0: line 0 (XOR mask) // plane 1: line 1 (AND mask) @@ -33,7 +34,7 @@ intel_set_cursor_shape(uint16 width, uint16 height, uint16 hotX, uint16 hotY, // transparent, for 0x3 it inverts the background, so only the first // two palette entries will be used (since we're using the 2 color mode). - uint8 *data = gInfo->shared_info->cursor_memory; + uint8* data = gInfo->shared_info->cursor_memory; uint8 byteWidth = (width + 7) / 8; for (int32 y = 0; y < height; y++) { @@ -49,10 +50,12 @@ intel_set_cursor_shape(uint16 width, uint16 height, uint16 hotX, uint16 hotY, gInfo->shared_info->cursor_format = CURSOR_FORMAT_2_COLORS; - write32(INTEL_CURSOR_CONTROL, CURSOR_ENABLED | gInfo->shared_info->cursor_format); + write32(INTEL_CURSOR_CONTROL, + CURSOR_ENABLED | gInfo->shared_info->cursor_format); write32(INTEL_CURSOR_SIZE, height << 12 | width); - write32(INTEL_CURSOR_BASE, (uint32)gInfo->shared_info->physical_graphics_memory + write32(INTEL_CURSOR_BASE, + (uint32)gInfo->shared_info->physical_graphics_memory + gInfo->shared_info->cursor_buffer_offset); // changing the hot point changes the cursor position, too @@ -104,7 +107,8 @@ intel_show_cursor(bool isVisible) write32(INTEL_CURSOR_CONTROL, (isVisible ? CURSOR_ENABLED : 0) | gInfo->shared_info->cursor_format); - write32(INTEL_CURSOR_BASE, (uint32)gInfo->shared_info->physical_graphics_memory + write32(INTEL_CURSOR_BASE, + (uint32)gInfo->shared_info->physical_graphics_memory + gInfo->shared_info->cursor_buffer_offset); gInfo->shared_info->cursor_visible = isVisible; diff --git a/src/add-ons/accelerants/intel_extreme/dpms.cpp b/src/add-ons/accelerants/intel_extreme/dpms.cpp index 4a4a3beea2..bbd2ec37bd 100644 --- a/src/add-ons/accelerants/intel_extreme/dpms.cpp +++ b/src/add-ons/accelerants/intel_extreme/dpms.cpp @@ -13,7 +13,7 @@ //#define TRACE_DPMS #ifdef TRACE_DPMS -extern "C" void _sPrintf(const char *format, ...); +extern "C" void _sPrintf(const char* format, ...); # define TRACE(x) _sPrintf x #else # define TRACE(x) ; @@ -27,21 +27,32 @@ enable_display_plane(bool enable) uint32 planeBControl = read32(INTEL_DISPLAY_B_CONTROL); if (enable) { - // when enabling the display, the register values are updated automatically - if (gInfo->head_mode & HEAD_MODE_A_ANALOG) - write32(INTEL_DISPLAY_A_CONTROL, planeAControl | DISPLAY_CONTROL_ENABLED); - if (gInfo->head_mode & HEAD_MODE_B_DIGITAL) - write32(INTEL_DISPLAY_B_CONTROL, planeBControl | DISPLAY_CONTROL_ENABLED); + // when enabling the display, the register values are updated + // automatically + if (gInfo->head_mode & HEAD_MODE_A_ANALOG) { + write32(INTEL_DISPLAY_A_CONTROL, + planeAControl | DISPLAY_CONTROL_ENABLED); + } + + if (gInfo->head_mode & HEAD_MODE_B_DIGITAL) { + write32(INTEL_DISPLAY_B_CONTROL, + planeBControl | DISPLAY_CONTROL_ENABLED); + } read32(INTEL_DISPLAY_A_BASE); // flush the eventually cached PCI bus writes } else { // when disabling it, we have to trigger the update using a write to // the display base address - if (gInfo->head_mode & HEAD_MODE_A_ANALOG) - write32(INTEL_DISPLAY_A_CONTROL, planeAControl & ~DISPLAY_CONTROL_ENABLED); - if (gInfo->head_mode & HEAD_MODE_B_DIGITAL) - write32(INTEL_DISPLAY_B_CONTROL, planeBControl & ~DISPLAY_CONTROL_ENABLED); + if (gInfo->head_mode & HEAD_MODE_A_ANALOG) { + write32(INTEL_DISPLAY_A_CONTROL, + planeAControl & ~DISPLAY_CONTROL_ENABLED); + } + + if (gInfo->head_mode & HEAD_MODE_B_DIGITAL) { + write32(INTEL_DISPLAY_B_CONTROL, + planeBControl & ~DISPLAY_CONTROL_ENABLED); + } set_frame_buffer_base(); } @@ -55,15 +66,25 @@ enable_display_pipe(bool enable) uint32 pipeBControl = read32(INTEL_DISPLAY_B_PIPE_CONTROL); if (enable) { - if (gInfo->head_mode & HEAD_MODE_A_ANALOG) - write32(INTEL_DISPLAY_A_PIPE_CONTROL, pipeAControl | DISPLAY_PIPE_ENABLED); - if (gInfo->head_mode & HEAD_MODE_B_DIGITAL) - write32(INTEL_DISPLAY_B_PIPE_CONTROL, pipeBControl | DISPLAY_PIPE_ENABLED); + if (gInfo->head_mode & HEAD_MODE_A_ANALOG) { + write32(INTEL_DISPLAY_A_PIPE_CONTROL, + pipeAControl | DISPLAY_PIPE_ENABLED); + } + + if (gInfo->head_mode & HEAD_MODE_B_DIGITAL) { + write32(INTEL_DISPLAY_B_PIPE_CONTROL, + pipeBControl | DISPLAY_PIPE_ENABLED); + } } else { - if (gInfo->head_mode & HEAD_MODE_A_ANALOG) - write32(INTEL_DISPLAY_A_PIPE_CONTROL, pipeAControl & ~DISPLAY_PIPE_ENABLED); - if (gInfo->head_mode & HEAD_MODE_B_DIGITAL) - write32(INTEL_DISPLAY_B_PIPE_CONTROL, pipeBControl & ~DISPLAY_PIPE_ENABLED); + if (gInfo->head_mode & HEAD_MODE_A_ANALOG) { + write32(INTEL_DISPLAY_A_PIPE_CONTROL, + pipeAControl & ~DISPLAY_PIPE_ENABLED); + } + + if (gInfo->head_mode & HEAD_MODE_B_DIGITAL) { + write32(INTEL_DISPLAY_B_PIPE_CONTROL, + pipeBControl & ~DISPLAY_PIPE_ENABLED); + } } read32(INTEL_DISPLAY_A_BASE); @@ -167,7 +188,8 @@ set_display_power_mode(uint32 mode) write32(INTEL_DISPLAY_A_ANALOG_PORT, (read32(INTEL_DISPLAY_A_ANALOG_PORT) & ~(DISPLAY_MONITOR_MODE_MASK | DISPLAY_MONITOR_PORT_ENABLED)) - | monitorMode | (mode != B_DPMS_OFF ? DISPLAY_MONITOR_PORT_ENABLED : 0)); + | monitorMode + | (mode != B_DPMS_OFF ? DISPLAY_MONITOR_PORT_ENABLED : 0)); } if (gInfo->head_mode & HEAD_MODE_B_DIGITAL) { write32(INTEL_DISPLAY_B_DIGITAL_PORT, diff --git a/src/add-ons/accelerants/intel_extreme/engine.cpp b/src/add-ons/accelerants/intel_extreme/engine.cpp index 1d8e21c9b2..fa42be4774 100644 --- a/src/add-ons/accelerants/intel_extreme/engine.cpp +++ b/src/add-ons/accelerants/intel_extreme/engine.cpp @@ -161,7 +161,7 @@ uninit_ring_buffer(ring_buffer &ringBuffer) void -setup_ring_buffer(ring_buffer &ringBuffer, const char *name) +setup_ring_buffer(ring_buffer &ringBuffer, const char* name) { TRACE(("Setup ring buffer %s, offset %lx, size %lx\n", name, ringBuffer.offset, ringBuffer.size)); @@ -197,8 +197,8 @@ intel_accelerant_engine_count(void) status_t -intel_acquire_engine(uint32 capabilities, uint32 maxWait, sync_token *syncToken, - engine_token **_engineToken) +intel_acquire_engine(uint32 capabilities, uint32 maxWait, sync_token* syncToken, + engine_token** _engineToken) { TRACE(("intel_acquire_engine()\n")); *_engineToken = &sEngineToken; @@ -214,7 +214,7 @@ intel_acquire_engine(uint32 capabilities, uint32 maxWait, sync_token *syncToken, status_t -intel_release_engine(engine_token *engineToken, sync_token *syncToken) +intel_release_engine(engine_token* engineToken, sync_token* syncToken) { TRACE(("intel_release_engine()\n")); if (syncToken != NULL) @@ -264,7 +264,7 @@ intel_wait_engine_idle(void) status_t -intel_get_sync_token(engine_token *engineToken, sync_token *syncToken) +intel_get_sync_token(engine_token* engineToken, sync_token* syncToken) { TRACE(("intel_get_sync_token()\n")); return B_OK; @@ -272,7 +272,7 @@ intel_get_sync_token(engine_token *engineToken, sync_token *syncToken) status_t -intel_sync_to_token(sync_token *syncToken) +intel_sync_to_token(sync_token* syncToken) { TRACE(("intel_sync_to_token()\n")); intel_wait_engine_idle(); @@ -284,7 +284,7 @@ intel_sync_to_token(sync_token *syncToken) void -intel_screen_to_screen_blit(engine_token *token, blit_params *params, +intel_screen_to_screen_blit(engine_token* token, blit_params* params, uint32 count) { QueueCommands queue(gInfo->shared_info->primary_ring_buffer); @@ -304,8 +304,8 @@ intel_screen_to_screen_blit(engine_token *token, blit_params *params, void -intel_fill_rectangle(engine_token *token, uint32 color, - fill_rect_params *params, uint32 count) +intel_fill_rectangle(engine_token* token, uint32 color, + fill_rect_params* params, uint32 count) { QueueCommands queue(gInfo->shared_info->primary_ring_buffer); @@ -323,7 +323,7 @@ intel_fill_rectangle(engine_token *token, uint32 color, void -intel_invert_rectangle(engine_token *token, fill_rect_params *params, +intel_invert_rectangle(engine_token* token, fill_rect_params* params, uint32 count) { QueueCommands queue(gInfo->shared_info->primary_ring_buffer); @@ -342,14 +342,14 @@ intel_invert_rectangle(engine_token *token, fill_rect_params *params, void -intel_fill_span(engine_token *token, uint32 color, uint16* _params, +intel_fill_span(engine_token* token, uint32 color, uint16* _params, uint32 count) { struct params { uint16 top; uint16 left; uint16 right; - } *params = (struct params *)_params; + } *params = (struct params*)_params; QueueCommands queue(gInfo->shared_info->primary_ring_buffer); diff --git a/src/add-ons/accelerants/intel_extreme/hooks.cpp b/src/add-ons/accelerants/intel_extreme/hooks.cpp index 7ac7c3895e..eeedee226a 100644 --- a/src/add-ons/accelerants/intel_extreme/hooks.cpp +++ b/src/add-ons/accelerants/intel_extreme/hooks.cpp @@ -11,8 +11,8 @@ #include "accelerant.h" -extern "C" void * -get_accelerant_hook(uint32 feature, void *data) +extern "C" void* +get_accelerant_hook(uint32 feature, void* data) { switch (feature) { /* general */ diff --git a/src/add-ons/accelerants/intel_extreme/memory.cpp b/src/add-ons/accelerants/intel_extreme/memory.cpp index 1f2a705f42..e32a7e77f2 100644 --- a/src/add-ons/accelerants/intel_extreme/memory.cpp +++ b/src/add-ons/accelerants/intel_extreme/memory.cpp @@ -16,7 +16,7 @@ //#define TRACE_MEMORY #ifdef TRACE_MEMORY -extern "C" void _sPrintf(const char *format, ...); +extern "C" void _sPrintf(const char* format, ...); # define TRACE(x) _sPrintf x #else # define TRACE(x) ; diff --git a/src/add-ons/accelerants/intel_extreme/mode.cpp b/src/add-ons/accelerants/intel_extreme/mode.cpp index 4e09262329..c14f213b51 100644 --- a/src/add-ons/accelerants/intel_extreme/mode.cpp +++ b/src/add-ons/accelerants/intel_extreme/mode.cpp @@ -26,7 +26,7 @@ #define TRACE_MODE #ifdef TRACE_MODE -extern "C" void _sPrintf(const char *format, ...); +extern "C" void _sPrintf(const char* format, ...); # define TRACE(x) _sPrintf x #else # define TRACE(x) ; @@ -99,13 +99,17 @@ set_i2c_signals(void* cookie, int clock, int data) if (data != 0) value |= I2C_DATA_DIRECTION_MASK; - else - value |= I2C_DATA_DIRECTION_MASK | I2C_DATA_DIRECTION_OUT | I2C_DATA_VALUE_MASK; + else { + value |= I2C_DATA_DIRECTION_MASK | I2C_DATA_DIRECTION_OUT + | I2C_DATA_VALUE_MASK; + } if (clock != 0) value |= I2C_CLOCK_DIRECTION_MASK; - else - value |= I2C_CLOCK_DIRECTION_MASK | I2C_CLOCK_DIRECTION_OUT | I2C_CLOCK_VALUE_MASK; + else { + value |= I2C_CLOCK_DIRECTION_MASK | I2C_CLOCK_DIRECTION_OUT + | I2C_CLOCK_VALUE_MASK; + } write32(ioRegister, value); read32(ioRegister); @@ -184,9 +188,9 @@ create_mode_list(void) size_t size = (sizeof(display_mode) + B_PAGE_SIZE - 1) & ~(B_PAGE_SIZE - 1); - display_mode *list; + display_mode* list; area_id area = create_area("intel extreme modes", - (void **)&list, B_ANY_ADDRESS, size, B_NO_LOCK, + (void**)&list, B_ANY_ADDRESS, size, B_NO_LOCK, B_READ_AREA | B_WRITE_AREA); if (area < B_OK) return area; @@ -203,7 +207,7 @@ create_mode_list(void) } // Otherwise return the 'real' list of modes - display_mode *list; + display_mode* list; uint32 count = 0; gInfo->mode_list_area = create_display_modes("intel extreme modes", gInfo->has_edid ? &gInfo->edid_info : NULL, NULL, 0, NULL, 0, NULL, @@ -285,12 +289,14 @@ get_pll_limits(pll_limits &limits) limits = kLimits; } - TRACE(("PLL limits, min: p %lu (p1 %lu, p2 %lu), n %lu, m %lu (m1 %lu, m2 %lu)\n", - limits.min.post, limits.min.post1, limits.min.post2, limits.min.n, - limits.min.m, limits.min.m1, limits.min.m2)); - TRACE(("PLL limits, max: p %lu (p1 %lu, p2 %lu), n %lu, m %lu (m1 %lu, m2 %lu)\n", - limits.max.post, limits.max.post1, limits.max.post2, limits.max.n, - limits.max.m, limits.max.m1, limits.max.m2)); + TRACE(("PLL limits, min: p %lu (p1 %lu, p2 %lu), n %lu, m %lu " + "(m1 %lu, m2 %lu)\n", limits.min.post, limits.min.post1, + limits.min.post2, limits.min.n, limits.min.m, limits.min.m1, + limits.min.m2)); + TRACE(("PLL limits, max: p %lu (p1 %lu, p2 %lu), n %lu, m %lu " + "(m1 %lu, m2 %lu)\n", limits.max.post, limits.max.post1, + limits.max.post2, limits.max.n, limits.max.m, limits.max.m1, + limits.max.m2)); } @@ -316,7 +322,8 @@ compute_pll_divisors(const display_mode ¤t, pll_divisors& divisors, bool isLVDS) { float requestedPixelClock = current.timing.pixel_clock / 1000.0f; - float referenceClock = gInfo->shared_info->pll_info.reference_frequency / 1000.0f; + float referenceClock + = gInfo->shared_info->pll_info.reference_frequency / 1000.0f; pll_limits limits; get_pll_limits(limits); @@ -344,7 +351,8 @@ compute_pll_divisors(const display_mode ¤t, pll_divisors& divisors, pll_divisors bestDivisors; bool is_igd = gInfo->shared_info->device_type.InGroup(INTEL_TYPE_IGD); - for (divisors.m1 = limits.min.m1; divisors.m1 <= limits.max.m1; divisors.m1++) { + for (divisors.m1 = limits.min.m1; divisors.m1 <= limits.max.m1; + divisors.m1++) { for (divisors.m2 = limits.min.m2; divisors.m2 <= limits.max.m2 && ((divisors.m2 < divisors.m1) || is_igd); divisors.m2++) { for (divisors.n = limits.min.n; divisors.n <= limits.max.n; @@ -358,7 +366,8 @@ compute_pll_divisors(const display_mode ¤t, pll_divisors& divisors, continue; float error = fabs(requestedPixelClock - - ((referenceClock * divisors.m) / divisors.n) / divisors.post); + - ((referenceClock * divisors.m) / divisors.n) + / divisors.post); if (error < best) { best = error; bestDivisors = divisors; @@ -373,7 +382,8 @@ compute_pll_divisors(const display_mode ¤t, pll_divisors& divisors, divisors = bestDivisors; - TRACE(("found: %g MHz, p = %lu (p1 = %lu, p2 = %lu), n = %lu, m = %lu (m1 = %lu, m2 = %lu)\n", + TRACE(("found: %g MHz, p = %lu (p1 = %lu, p2 = %lu), n = %lu, m = %lu " + "(m1 = %lu, m2 = %lu)\n", ((referenceClock * divisors.m) / divisors.n) / divisors.post, divisors.post, divisors.post1, divisors.post2, divisors.n, divisors.m, divisors.m1, divisors.m2)); @@ -618,7 +628,7 @@ intel_accelerant_mode_count(void) status_t -intel_get_mode_list(display_mode *modeList) +intel_get_mode_list(display_mode* modeList) { TRACE(("intel_get_mode_info()\n")); memcpy(modeList, gInfo->mode_list, @@ -628,8 +638,8 @@ intel_get_mode_list(display_mode *modeList) status_t -intel_propose_display_mode(display_mode *target, const display_mode *low, - const display_mode *high) +intel_propose_display_mode(display_mode* target, const display_mode* low, + const display_mode* high) { TRACE(("intel_propose_display_mode()\n")); @@ -641,7 +651,7 @@ intel_propose_display_mode(display_mode *target, const display_mode *low, status_t -intel_set_display_mode(display_mode *mode) +intel_set_display_mode(display_mode* mode) { TRACE(("intel_set_display_mode(%ldx%ld)\n", mode->virtual_width, mode->virtual_height)); @@ -712,7 +722,7 @@ if (first) { } // clear frame buffer before using it - memset((uint8 *)base, 0, bytesPerRow * target.virtual_height); + memset((uint8*)base, 0, bytesPerRow * target.virtual_height); sharedInfo.frame_buffer = base; sharedInfo.frame_buffer_offset = base - (addr_t)sharedInfo.graphics_memory; @@ -1105,7 +1115,7 @@ if (first) { status_t -intel_get_display_mode(display_mode *_currentMode) +intel_get_display_mode(display_mode* _currentMode) { TRACE(("intel_get_display_mode()\n")); @@ -1131,7 +1141,7 @@ intel_get_edid_info(void* info, size_t size, uint32* _version) status_t -intel_get_frame_buffer_config(frame_buffer_config *config) +intel_get_frame_buffer_config(frame_buffer_config* config) { TRACE(("intel_get_frame_buffer_config()\n")); @@ -1139,7 +1149,7 @@ intel_get_frame_buffer_config(frame_buffer_config *config) config->frame_buffer = gInfo->shared_info->graphics_memory + offset; config->frame_buffer_dma - = (uint8 *)gInfo->shared_info->physical_graphics_memory + offset; + = (uint8*)gInfo->shared_info->physical_graphics_memory + offset; config->bytes_per_row = gInfo->shared_info->bytes_per_row; return B_OK; @@ -1147,13 +1157,14 @@ intel_get_frame_buffer_config(frame_buffer_config *config) status_t -intel_get_pixel_clock_limits(display_mode *mode, uint32 *_low, uint32 *_high) +intel_get_pixel_clock_limits(display_mode* mode, uint32* _low, uint32* _high) { TRACE(("intel_get_pixel_clock_limits()\n")); if (_low != NULL) { // lower limit of about 48Hz vertical refresh - uint32 totalClocks = (uint32)mode->timing.h_total * (uint32)mode->timing.v_total; + uint32 totalClocks = (uint32)mode->timing.h_total + * (uint32)mode->timing.v_total; uint32 low = (totalClocks * 48L) / 1000L; if (low < gInfo->shared_info->pll_info.min_frequency) low = gInfo->shared_info->pll_info.min_frequency; @@ -1194,7 +1205,7 @@ intel_move_display(uint16 horizontalStart, uint16 verticalStart) status_t -intel_get_timing_constraints(display_timing_constraints *constraints) +intel_get_timing_constraints(display_timing_constraints* constraints) { TRACE(("intel_get_timing_contraints()\n")); return B_ERROR; @@ -1202,9 +1213,10 @@ intel_get_timing_constraints(display_timing_constraints *constraints) void -intel_set_indexed_colors(uint count, uint8 first, uint8 *colors, uint32 flags) +intel_set_indexed_colors(uint count, uint8 first, uint8* colors, uint32 flags) { - TRACE(("intel_set_indexed_colors(colors = %p, first = %u)\n", colors, first)); + TRACE(("intel_set_indexed_colors(colors = %p, first = %u)\n", colors, + first)); if (colors == NULL) return; diff --git a/src/add-ons/accelerants/intel_extreme/overlay.cpp b/src/add-ons/accelerants/intel_extreme/overlay.cpp index a348ac6251..a36f46dd3e 100644 --- a/src/add-ons/accelerants/intel_extreme/overlay.cpp +++ b/src/add-ons/accelerants/intel_extreme/overlay.cpp @@ -23,7 +23,7 @@ //#define TRACE_OVERLAY #ifdef TRACE_OVERLAY -extern "C" void _sPrintf(const char *format, ...); +extern "C" void _sPrintf(const char* format, ...); # define TRACE(x) _sPrintf x #else # define TRACE(x) ; @@ -63,19 +63,23 @@ split_coefficient(double &coefficient, int32 mantissaSize, int32 maxValue = 1 << mantissaSize; res = 12 - mantissaSize; - if ((intCoefficient = (int)(absCoefficient * 4 * maxValue + 0.5)) < maxValue) { + if ((intCoefficient = (int)(absCoefficient * 4 * maxValue + 0.5)) + < maxValue) { splitCoefficient.exponent = 3; splitCoefficient.mantissa = intCoefficient << res; coefficient = (double)intCoefficient / (double)(4 * maxValue); - } else if ((intCoefficient = (int)(absCoefficient * 2 * maxValue + 0.5)) < maxValue) { + } else if ((intCoefficient = (int)(absCoefficient * 2 * maxValue + 0.5)) + < maxValue) { splitCoefficient.exponent = 2; splitCoefficient.mantissa = intCoefficient << res; coefficient = (double)intCoefficient / (double)(2 * maxValue); - } else if ((intCoefficient = (int)(absCoefficient * maxValue + 0.5)) < maxValue) { + } else if ((intCoefficient = (int)(absCoefficient * maxValue + 0.5)) + < maxValue) { splitCoefficient.exponent = 1; splitCoefficient.mantissa = intCoefficient << res; coefficient = (double)intCoefficient / (double)maxValue; - } else if ((intCoefficient = (int)(absCoefficient * maxValue * 0.5 + 0.5)) < maxValue) { + } else if ((intCoefficient = (int)(absCoefficient * maxValue * 0.5 + 0.5)) + < maxValue) { splitCoefficient.exponent = 0; splitCoefficient.mantissa = intCoefficient << res; coefficient = (double)intCoefficient / (double)(maxValue / 2); @@ -94,7 +98,7 @@ split_coefficient(double &coefficient, int32 mantissaSize, static void update_coefficients(int32 taps, double filterCutOff, bool horizontal, bool isY, - phase_coefficient *splitCoefficients) + phase_coefficient* splitCoefficients) { if (filterCutOff < 1) filterCutOff = 1; @@ -184,7 +188,7 @@ static void set_color_key(uint8 red, uint8 green, uint8 blue, uint8 redMask, uint8 greenMask, uint8 blueMask) { - overlay_registers *registers = gInfo->overlay_registers; + overlay_registers* registers = gInfo->overlay_registers; registers->color_key_red = red; registers->color_key_green = green; @@ -197,7 +201,7 @@ set_color_key(uint8 red, uint8 green, uint8 blue, uint8 redMask, static void -set_color_key(const overlay_window *window) +set_color_key(const overlay_window* window) { switch (gInfo->shared_info->current_mode.space) { case B_CMAP8: @@ -205,13 +209,13 @@ set_color_key(const overlay_window *window) break; case B_RGB15: set_color_key(window->red.value << 3, window->green.value << 3, - window->blue.value << 3, window->red.mask << 3, window->green.mask << 3, - window->blue.mask << 3); + window->blue.value << 3, window->red.mask << 3, + window->green.mask << 3, window->blue.mask << 3); break; case B_RGB16: set_color_key(window->red.value << 3, window->green.value << 2, - window->blue.value << 3, window->red.mask << 3, window->green.mask << 2, - window->blue.mask << 3); + window->blue.value << 3, window->red.mask << 3, + window->green.mask << 2, window->blue.mask << 3); break; default: @@ -239,9 +243,11 @@ update_overlay(bool updateCoefficients) queue.PutWaitFor(COMMAND_WAIT_FOR_OVERLAY_FLIP); queue.PutFlush(); - TRACE(("update overlay: UP: %lx, TST: %lx, ST: %lx, CMD: %lx (%lx), ERR: %lx\n", - read32(INTEL_OVERLAY_UPDATE), read32(INtEL_OVERLAY_TEST), read32(INTEL_OVERLAY_STATUS), - *(((uint32 *)gInfo->overlay_registers) + 0x68/4), read32(0x30168), read32(0x2024))); + TRACE(("update overlay: UP: %lx, TST: %lx, ST: %lx, CMD: %lx (%lx), " + "ERR: %lx\n", read32(INTEL_OVERLAY_UPDATE), read32(INtEL_OVERLAY_TEST), + read32(INTEL_OVERLAY_STATUS), + *(((uint32*)gInfo->overlay_registers) + 0x68/4), read32(0x30168), + read32(0x2024))); } @@ -259,9 +265,11 @@ show_overlay(void) queue.PutOverlayFlip(COMMAND_OVERLAY_ON, true); queue.PutFlush(); - TRACE(("show overlay: UP: %lx, TST: %lx, ST: %lx, CMD: %lx (%lx), ERR: %lx\n", - read32(INTEL_OVERLAY_UPDATE), read32(INTEL_OVERLAY_TEST), read32(INTEL_OVERLAY_STATUS), - *(((uint32 *)gInfo->overlay_registers) + 0x68/4), read32(0x30168), read32(0x2024))); + TRACE(("show overlay: UP: %lx, TST: %lx, ST: %lx, CMD: %lx (%lx), " + "ERR: %lx\n", read32(INTEL_OVERLAY_UPDATE), read32(INTEL_OVERLAY_TEST), + read32(INTEL_OVERLAY_STATUS), + *(((uint32*)gInfo->overlay_registers) + 0x68/4), read32(0x30168), + read32(0x2024))); } @@ -272,7 +280,7 @@ hide_overlay(void) || gInfo->shared_info->device_type.InGroup(INTEL_TYPE_965)) return; - overlay_registers *registers = gInfo->overlay_registers; + overlay_registers* registers = gInfo->overlay_registers; gInfo->shared_info->overlay_active = false; registers->overlay_enabled = false; @@ -299,7 +307,7 @@ hide_overlay(void) uint32 -intel_overlay_count(const display_mode *mode) +intel_overlay_count(const display_mode* mode) { // TODO: make this depending on the amount of RAM and the screen mode // (and we could even have more than one when using 3D as well) @@ -307,8 +315,8 @@ intel_overlay_count(const display_mode *mode) } -const uint32 * -intel_overlay_supported_spaces(const display_mode *mode) +const uint32* +intel_overlay_supported_spaces(const display_mode* mode) { static const uint32 kSupportedSpaces[] = {B_RGB15, B_RGB16, B_RGB32, B_YCbCr422, 0}; @@ -332,12 +340,12 @@ intel_overlay_supported_features(uint32 colorSpace) } -const overlay_buffer * +const overlay_buffer* intel_allocate_overlay_buffer(color_space colorSpace, uint16 width, uint16 height) { - TRACE(("intel_allocate_overlay_buffer(width %u, height %u, colorSpace %lu)\n", - width, height, colorSpace)); + TRACE(("intel_allocate_overlay_buffer(width %u, height %u, " + "colorSpace %lu)\n", width, height, colorSpace)); intel_shared_info &sharedInfo = *gInfo->shared_info; uint32 bytesPerPixel; @@ -359,7 +367,7 @@ intel_allocate_overlay_buffer(color_space colorSpace, uint16 width, return NULL; } - struct overlay *overlay = (struct overlay *)malloc(sizeof(struct overlay)); + struct overlay* overlay = (struct overlay*)malloc(sizeof(struct overlay)); if (overlay == NULL) return NULL; @@ -371,7 +379,7 @@ intel_allocate_overlay_buffer(color_space colorSpace, uint16 width, if (sharedInfo.device_type.InGroup(INTEL_TYPE_965)) alignment = 0xff; - overlay_buffer *buffer = &overlay->buffer; + overlay_buffer* buffer = &overlay->buffer; buffer->space = colorSpace; buffer->width = width; buffer->height = height; @@ -400,8 +408,8 @@ intel_allocate_overlay_buffer(color_space colorSpace, uint16 width, overlay->buffer_offset = overlay->buffer_base - (addr_t)gInfo->shared_info->graphics_memory; - buffer->buffer = (uint8 *)overlay->buffer_base; - buffer->buffer_dma = (uint8 *)gInfo->shared_info->physical_graphics_memory + buffer->buffer = (uint8*)overlay->buffer_base; + buffer->buffer_dma = (uint8*)gInfo->shared_info->physical_graphics_memory + overlay->buffer_offset; TRACE(("allocated overlay buffer: base=%x, offset=%x, address=%x, " @@ -413,11 +421,11 @@ intel_allocate_overlay_buffer(color_space colorSpace, uint16 width, status_t -intel_release_overlay_buffer(const overlay_buffer *buffer) +intel_release_overlay_buffer(const overlay_buffer* buffer) { TRACE(("intel_release_overlay_buffer(buffer %p)\n", buffer)); - struct overlay *overlay = (struct overlay *)buffer; + struct overlay* overlay = (struct overlay*)buffer; // TODO: locking! @@ -434,8 +442,8 @@ intel_release_overlay_buffer(const overlay_buffer *buffer) status_t -intel_get_overlay_constraints(const display_mode *mode, - const overlay_buffer *buffer, overlay_constraints *constraints) +intel_get_overlay_constraints(const display_mode* mode, + const overlay_buffer* buffer, overlay_constraints* constraints) { TRACE(("intel_get_overlay_constraints(buffer %p)\n", buffer)); @@ -525,8 +533,9 @@ intel_release_overlay(overlay_token overlayToken) status_t -intel_configure_overlay(overlay_token overlayToken, const overlay_buffer *buffer, - const overlay_window *window, const overlay_view *view) +intel_configure_overlay(overlay_token overlayToken, + const overlay_buffer* buffer, const overlay_window* window, + const overlay_view* view) { TRACE(("intel_configure_overlay: buffer %p, window %p, view %p\n", buffer, window, view)); @@ -539,8 +548,8 @@ intel_configure_overlay(overlay_token overlayToken, const overlay_buffer *buffer return B_OK; } - struct overlay *overlay = (struct overlay *)buffer; - overlay_registers *registers = gInfo->overlay_registers; + struct overlay* overlay = (struct overlay*)buffer; + overlay_registers* registers = gInfo->overlay_registers; bool updateCoefficients = false; uint32 bytesPerPixel = 2; @@ -689,7 +698,7 @@ intel_configure_overlay(overlay_token overlayToken, const overlay_buffer *buffer } gInfo->last_overlay_view = *view; - gInfo->last_overlay_frame = *(overlay_frame *)window; + gInfo->last_overlay_frame = *(overlay_frame*)window; } registers->color_control_output_mode = true; diff --git a/src/add-ons/kernel/busses/agp_gart/intel_gart.cpp b/src/add-ons/kernel/busses/agp_gart/intel_gart.cpp index a11b3323fd..5e3b0923fe 100644 --- a/src/add-ons/kernel/busses/agp_gart/intel_gart.cpp +++ b/src/add-ons/kernel/busses/agp_gart/intel_gart.cpp @@ -34,9 +34,9 @@ (sPCI->write_pci_config((info).bus, (info).device, (info).function, \ (offset), (size), (value))) #define write32(address, data) \ - (*((volatile uint32 *)(address)) = (data)) + (*((volatile uint32*)(address)) = (data)) #define read32(address) \ - (*((volatile uint32 *)(address))) + (*((volatile uint32*)(address))) const struct supported_device { @@ -109,7 +109,7 @@ struct intel_info { }; static intel_info sInfo; -static pci_module_info *sPCI; +static pci_module_info* sPCI; static bool @@ -219,7 +219,8 @@ determine_memory_sizes(intel_info &info, size_t >tSize, size_t &stolenSize) switch (memoryConfig & STOLEN_MEMORY_MASK) { case i830_LOCAL_MEMORY_ONLY: // TODO: determine its size! - dprintf("intel_gart: getting local memory size not implemented.\n"); + dprintf("intel_gart: getting local memory size not " + "implemented.\n"); break; case i830_STOLEN_512K: memorySize >>= 1; @@ -357,17 +358,17 @@ intel_map(intel_info &info) int fbIndex = 0; int mmioIndex = 1; if ((info.type & INTEL_TYPE_FAMILY_MASK) == INTEL_TYPE_9xx) { - // for some reason Intel saw the need to change the order of the mappings - // with the introduction of the i9xx family + // for some reason Intel saw the need to change the order of the + // mappings with the introduction of the i9xx family mmioIndex = 0; fbIndex = 2; } AreaKeeper mmioMapper; info.registers_area = mmioMapper.Map("intel GMCH mmio", - (void *)info.display.u.h0.base_registers[mmioIndex], + (void*)info.display.u.h0.base_registers[mmioIndex], info.display.u.h0.base_register_sizes[mmioIndex], B_ANY_KERNEL_ADDRESS, - B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA, (void **)&info.registers); + B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA, (void**)&info.registers); if (mmioMapper.InitCheck() < B_OK) { dprintf("agp_intel: could not map memory I/O!\n"); return info.registers_area; @@ -378,7 +379,7 @@ intel_map(intel_info &info) get_pci_config(info.display, PCI_command, 2) | PCI_command_io | PCI_command_memory | PCI_command_master); - void *scratchAddress; + void* scratchAddress; AreaKeeper scratchCreator; info.scratch_area = scratchCreator.Create("intel GMCH scratch", &scratchAddress, B_ANY_KERNEL_ADDRESS, B_PAGE_SIZE, B_FULL_LOCK, @@ -398,7 +399,8 @@ intel_map(intel_info &info) info.gtt_physical_base = info.display.u.h0.base_registers[mmioIndex] + (2UL << 20); } else - info.gtt_physical_base = get_pci_config(info.display, i915_GTT_BASE, 4); + info.gtt_physical_base + = get_pci_config(info.display, i915_GTT_BASE, 4); } else { info.gtt_physical_base = read32(info.registers + INTEL_PAGE_TABLE_CONTROL) & ~PAGE_TABLE_ENABLED; @@ -417,13 +419,13 @@ intel_map(intel_info &info) info.gtt_entries = gttSize / 4096; info.gtt_stolen_entries = stolenSize / 4096; - TRACE("GTT base %lx, size %lu, entries %lu, stolen %lu\n", info.gtt_physical_base, - gttSize, info.gtt_entries, stolenSize); + TRACE("GTT base %lx, size %lu, entries %lu, stolen %lu\n", + info.gtt_physical_base, gttSize, info.gtt_entries, stolenSize); AreaKeeper gttMapper; info.gtt_area = gttMapper.Map("intel GMCH gtt", - (void *)info.gtt_physical_base, gttSize, B_ANY_KERNEL_ADDRESS, - B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA, (void **)&info.gtt_base); + (void*)info.gtt_physical_base, gttSize, B_ANY_KERNEL_ADDRESS, + B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA, (void**)&info.gtt_base); if (gttMapper.InitCheck() < B_OK) { dprintf("intel_gart: could not map GTT!\n"); return info.gtt_area; @@ -439,22 +441,23 @@ intel_map(intel_info &info) info.aperture_size >> 20, gttSize >> 10); dprintf("intel_gart: GTT base = 0x%lx\n", info.gtt_physical_base); - dprintf("intel_gart: MMIO base = 0x%lx\n", info.display.u.h0.base_registers[mmioIndex]); + dprintf("intel_gart: MMIO base = 0x%lx\n", + info.display.u.h0.base_registers[mmioIndex]); dprintf("intel_gart: GMR base = 0x%lx\n", info.aperture_physical_base); AreaKeeper apertureMapper; info.aperture_area = apertureMapper.Map("intel graphics aperture", - (void *)info.aperture_physical_base, info.aperture_size, + (void*)info.aperture_physical_base, info.aperture_size, B_ANY_KERNEL_BLOCK_ADDRESS | B_MTR_WC, - B_READ_AREA | B_WRITE_AREA, (void **)&info.aperture_base); + B_READ_AREA | B_WRITE_AREA, (void**)&info.aperture_base); if (apertureMapper.InitCheck() < B_OK) { // try again without write combining dprintf(DEVICE_NAME ": enabling write combined mode failed.\n"); info.aperture_area = apertureMapper.Map("intel graphics aperture", - (void *)info.aperture_physical_base, info.aperture_size, + (void*)info.aperture_physical_base, info.aperture_size, B_ANY_KERNEL_BLOCK_ADDRESS, B_READ_AREA | B_WRITE_AREA, - (void **)&info.aperture_base); + (void**)&info.aperture_base); } if (apertureMapper.InitCheck() < B_OK) { dprintf(DEVICE_NAME ": could not map graphics aperture!\n"); @@ -477,7 +480,7 @@ intel_map(intel_info &info) status_t intel_create_aperture(uint8 bus, uint8 device, uint8 function, size_t size, - void **_aperture) + void** _aperture) { // TODO: we currently only support a single AGP bridge! if ((bus != sInfo.bridge.bus || device != sInfo.bridge.device @@ -514,14 +517,14 @@ intel_create_aperture(uint8 bus, uint8 device, uint8 function, size_t size, void -intel_delete_aperture(void *aperture) +intel_delete_aperture(void* aperture) { intel_unmap(sInfo); } static status_t -intel_get_aperture_info(void *aperture, aperture_info *info) +intel_get_aperture_info(void* aperture, aperture_info* info) { if (info == NULL) return B_BAD_VALUE; @@ -536,14 +539,14 @@ intel_get_aperture_info(void *aperture, aperture_info *info) status_t -intel_set_aperture_size(void *aperture, size_t size) +intel_set_aperture_size(void* aperture, size_t size) { return B_ERROR; } static status_t -intel_bind_page(void *aperture, uint32 offset, phys_addr_t physicalAddress) +intel_bind_page(void* aperture, uint32 offset, phys_addr_t physicalAddress) { //TRACE("bind_page(offset %lx, physical %lx)\n", offset, physicalAddress); @@ -553,7 +556,7 @@ intel_bind_page(void *aperture, uint32 offset, phys_addr_t physicalAddress) static status_t -intel_unbind_page(void *aperture, uint32 offset) +intel_unbind_page(void* aperture, uint32 offset) { //TRACE("unbind_page(offset %lx)\n", offset); @@ -565,7 +568,7 @@ intel_unbind_page(void *aperture, uint32 offset) void -intel_flush_tlbs(void *aperture) +intel_flush_tlbs(void* aperture) { read32(sInfo.gtt_base + sInfo.gtt_entries - 1); asm("wbinvd;"); @@ -580,7 +583,7 @@ intel_init() { TRACE("bus manager init\n"); - if (get_module(B_PCI_MODULE_NAME, (module_info **)&sPCI) != B_OK) + if (get_module(B_PCI_MODULE_NAME, (module_info**)&sPCI) != B_OK) return B_ERROR; bool found = false; @@ -652,7 +655,7 @@ static struct agp_gart_bus_module_info sIntelModuleInfo = { intel_flush_tlbs }; -module_info *modules[] = { - (module_info *)&sIntelModuleInfo, +module_info* modules[] = { + (module_info*)&sIntelModuleInfo, NULL }; diff --git a/src/add-ons/kernel/drivers/graphics/intel_extreme/device.cpp b/src/add-ons/kernel/drivers/graphics/intel_extreme/device.cpp index d3321f390a..df259cbdd7 100644 --- a/src/add-ons/kernel/drivers/graphics/intel_extreme/device.cpp +++ b/src/add-ons/kernel/drivers/graphics/intel_extreme/device.cpp @@ -36,12 +36,15 @@ /* device hooks prototypes */ -static status_t device_open(const char *name, uint32 flags, void **_cookie); -static status_t device_close(void *data); -static status_t device_free(void *data); -static status_t device_ioctl(void *data, uint32 opcode, void *buffer, size_t length); -static status_t device_read(void *data, off_t offset, void *buffer, size_t *length); -static status_t device_write(void *data, off_t offset, const void *buffer, size_t *length); +static status_t device_open(const char* name, uint32 flags, void** _cookie); +static status_t device_close(void* data); +static status_t device_free(void* data); +static status_t device_ioctl(void* data, uint32 opcode, void* buffer, + size_t length); +static status_t device_read(void* data, off_t offset, void* buffer, + size_t* length); +static status_t device_write(void* data, off_t offset, const void* buffer, + size_t* length); device_hooks gDeviceHooks = { @@ -60,7 +63,7 @@ device_hooks gDeviceHooks = { #ifdef DEBUG_COMMANDS static int -getset_register(int argc, char **argv) +getset_register(int argc, char** argv) { if (argc < 2 || argc > 3) { kprintf("usage: %s [set-to-value]\n", argv[0]); @@ -96,14 +99,14 @@ getset_register(int argc, char **argv) static status_t -device_open(const char *name, uint32 /*flags*/, void **_cookie) +device_open(const char* name, uint32 /*flags*/, void** _cookie) { TRACE((DEVICE_NAME ": open(name = %s)\n", name)); int32 id; // find accessed device { - char *thisName; + char* thisName; // search for device name for (id = 0; (thisName = gDeviceNames[id]) != NULL; id++) { @@ -114,7 +117,7 @@ device_open(const char *name, uint32 /*flags*/, void **_cookie) return B_BAD_VALUE; } - intel_info *info = gDeviceInfo[id]; + intel_info* info = gDeviceInfo[id]; mutex_lock(&gLock); @@ -142,7 +145,7 @@ device_open(const char *name, uint32 /*flags*/, void **_cookie) static status_t -device_close(void */*data*/) +device_close(void* /*data*/) { TRACE((DEVICE_NAME ": close\n")); return B_OK; @@ -150,9 +153,9 @@ device_close(void */*data*/) static status_t -device_free(void *data) +device_free(void* data) { - struct intel_info *info = (intel_info *)data; + struct intel_info* info = (intel_info*)data; mutex_lock(&gLock); @@ -173,20 +176,20 @@ device_free(void *data) static status_t -device_ioctl(void *data, uint32 op, void *buffer, size_t bufferLength) +device_ioctl(void* data, uint32 op, void* buffer, size_t bufferLength) { - struct intel_info *info = (intel_info *)data; + struct intel_info* info = (intel_info*)data; switch (op) { case B_GET_ACCELERANT_SIGNATURE: - strcpy((char *)buffer, INTEL_ACCELERANT_NAME); + strcpy((char*)buffer, INTEL_ACCELERANT_NAME); TRACE((DEVICE_NAME ": accelerant: %s\n", INTEL_ACCELERANT_NAME)); return B_OK; // needed to share data between kernel and accelerant case INTEL_GET_PRIVATE_DATA: { - intel_get_private_data *data = (intel_get_private_data *)buffer; + intel_get_private_data* data = (intel_get_private_data* )buffer; if (data->magic == INTEL_PRIVATE_DATA_MAGIC) { data->shared_info_area = info->shared_area; @@ -198,12 +201,12 @@ device_ioctl(void *data, uint32 op, void *buffer, size_t bufferLength) // needed for cloning case INTEL_GET_DEVICE_NAME: #ifdef __HAIKU__ - if (user_strlcpy((char *)buffer, gDeviceNames[info->id], + if (user_strlcpy((char* )buffer, gDeviceNames[info->id], B_PATH_NAME_LENGTH) < B_OK) return B_BAD_ADDRESS; #else - strncpy((char *)buffer, gDeviceNames[info->id], B_PATH_NAME_LENGTH); - ((char *)buffer)[B_PATH_NAME_LENGTH - 1] = '\0'; + strncpy((char* )buffer, gDeviceNames[info->id], B_PATH_NAME_LENGTH); + ((char* )buffer)[B_PATH_NAME_LENGTH - 1] = '\0'; #endif return B_OK; @@ -216,7 +219,8 @@ device_ioctl(void *data, uint32 op, void *buffer, size_t bufferLength) sizeof(intel_allocate_graphics_memory)) < B_OK) return B_BAD_ADDRESS; #else - memcpy(&allocMemory, buffer, sizeof(intel_allocate_graphics_memory)); + memcpy(&allocMemory, buffer, + sizeof(intel_allocate_graphics_memory)); #endif if (allocMemory.magic != INTEL_PRIVATE_DATA_MAGIC) @@ -224,7 +228,7 @@ device_ioctl(void *data, uint32 op, void *buffer, size_t bufferLength) status_t status = intel_allocate_memory(*info, allocMemory.size, allocMemory.alignment, allocMemory.flags, - (addr_t *)&allocMemory.buffer_base); + (addr_t* )&allocMemory.buffer_base); if (status == B_OK) { // copy result #ifdef __HAIKU__ @@ -266,7 +270,7 @@ device_ioctl(void *data, uint32 op, void *buffer, size_t bufferLength) static status_t -device_read(void */*data*/, off_t /*pos*/, void */*buffer*/, size_t *_length) +device_read(void* /*data*/, off_t /*pos*/, void* /*buffer*/, size_t* _length) { *_length = 0; return B_NOT_ALLOWED; @@ -274,7 +278,8 @@ device_read(void */*data*/, off_t /*pos*/, void */*buffer*/, size_t *_length) static status_t -device_write(void */*data*/, off_t /*pos*/, const void */*buffer*/, size_t *_length) +device_write(void* /*data*/, off_t /*pos*/, const void* /*buffer*/, + size_t* _length) { *_length = 0; return B_NOT_ALLOWED; diff --git a/src/add-ons/kernel/drivers/graphics/intel_extreme/driver.cpp b/src/add-ons/kernel/drivers/graphics/intel_extreme/driver.cpp index 835fcee462..5a0329df11 100644 --- a/src/add-ons/kernel/drivers/graphics/intel_extreme/driver.cpp +++ b/src/add-ons/kernel/drivers/graphics/intel_extreme/driver.cpp @@ -86,7 +86,7 @@ mutex gLock; static status_t -get_next_intel_extreme(int32 *_cookie, pci_info &info, uint32 &type) +get_next_intel_extreme(int32* _cookie, pci_info &info, uint32 &type) { int32 index = *_cookie; @@ -114,11 +114,11 @@ get_next_intel_extreme(int32 *_cookie, pci_info &info, uint32 &type) } -extern "C" const char ** +extern "C" const char** publish_devices(void) { TRACE((DEVICE_NAME ": publish_devices()\n")); - return (const char **)gDeviceNames; + return (const char**)gDeviceNames; } @@ -127,7 +127,7 @@ init_hardware(void) { TRACE((DEVICE_NAME ": init_hardware()\n")); - status_t status = get_module(B_PCI_MODULE_NAME,(module_info **)&gPCI); + status_t status = get_module(B_PCI_MODULE_NAME,(module_info**)&gPCI); if (status != B_OK) { TRACE((DEVICE_NAME ": pci module unavailable\n")); return status; @@ -202,7 +202,7 @@ init_driver(void) gDeviceInfo[found]->init_status = B_NO_INIT; gDeviceInfo[found]->id = found; gDeviceInfo[found]->pci = info; - gDeviceInfo[found]->registers = (uint8 *)info->u.h0.base_registers[0]; + gDeviceInfo[found]->registers = (uint8*)info->u.h0.base_registers[0]; gDeviceInfo[found]->device_identifier = kSupportedDevices[type].name; gDeviceInfo[found]->device_type = kSupportedDevices[type].type; diff --git a/src/add-ons/kernel/drivers/graphics/intel_extreme/driver.h b/src/add-ons/kernel/drivers/graphics/intel_extreme/driver.h index 06956d7e58..1c83e729ed 100644 --- a/src/add-ons/kernel/drivers/graphics/intel_extreme/driver.h +++ b/src/add-ons/kernel/drivers/graphics/intel_extreme/driver.h @@ -43,7 +43,7 @@ set_pci_config(pci_info* info, uint8 offset, uint8 size, uint32 value) static inline uint16 read16(intel_info &info, uint32 encodedRegister) { - return *(volatile uint16 *)(info.registers + return *(volatile uint16*)(info.registers + info.shared_info->register_blocks[REGISTER_BLOCK(encodedRegister)] + REGISTER_REGISTER(encodedRegister)); } @@ -52,7 +52,7 @@ read16(intel_info &info, uint32 encodedRegister) static inline uint32 read32(intel_info &info, uint32 encodedRegister) { - return *(volatile uint32 *)(info.registers + return *(volatile uint32*)(info.registers + info.shared_info->register_blocks[REGISTER_BLOCK(encodedRegister)] + REGISTER_REGISTER(encodedRegister)); } @@ -61,7 +61,7 @@ read32(intel_info &info, uint32 encodedRegister) static inline void write16(intel_info &info, uint32 encodedRegister, uint16 value) { - *(volatile uint16 *)(info.registers + *(volatile uint16*)(info.registers + info.shared_info->register_blocks[REGISTER_BLOCK(encodedRegister)] + REGISTER_REGISTER(encodedRegister)) = value; } @@ -70,7 +70,7 @@ write16(intel_info &info, uint32 encodedRegister, uint16 value) static inline void write32(intel_info &info, uint32 encodedRegister, uint32 value) { - *(volatile uint32 *)(info.registers + *(volatile uint32*)(info.registers + info.shared_info->register_blocks[REGISTER_BLOCK(encodedRegister)] + REGISTER_REGISTER(encodedRegister)) = value; } diff --git a/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp b/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp index 34c9fbd216..7e445d218d 100644 --- a/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp +++ b/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp @@ -31,7 +31,7 @@ static void -init_overlay_registers(overlay_registers *registers) +init_overlay_registers(overlay_registers* registers) { memset(registers, 0, B_PAGE_SIZE); @@ -46,7 +46,7 @@ read_settings(bool &hardwareCursor) { hardwareCursor = false; - void *settings = load_driver_settings("intel_extreme"); + void* settings = load_driver_settings("intel_extreme"); if (settings != NULL) { hardwareCursor = get_driver_boolean_parameter(settings, "hardware_cursor", true, true); @@ -72,9 +72,9 @@ release_vblank_sem(intel_info &info) static int32 -intel_interrupt_handler(void *data) +intel_interrupt_handler(void* data) { - intel_info &info = *(intel_info *)data; + intel_info &info = *(intel_info*)data; uint16 identity = read16(info, INTEL_INTERRUPT_IDENTITY); if (identity == 0) @@ -135,7 +135,7 @@ init_interrupt_handler(intel_info &info) info.fake_interrupts = false; status = install_io_interrupt_handler(info.pci->u.h0.interrupt_line, - &intel_interrupt_handler, (void *)&info, 0); + &intel_interrupt_handler, (void*)&info, 0); if (status == B_OK) { write32(info, INTEL_DISPLAY_A_PIPE_STATUS, DISPLAY_PIPE_VBLANK_STATUS | DISPLAY_PIPE_VBLANK_ENABLED); @@ -162,7 +162,8 @@ init_interrupt_handler(intel_info &info) info.fake_interrupts = true; // TODO: fake interrupts! - TRACE((DEVICE_NAME "Fake interrupt mode (no PCI interrupt line assigned)")); + TRACE((DEVICE_NAME "Fake interrupt mode (no PCI interrupt line " + "assigned)")); status = B_ERROR; } @@ -185,7 +186,7 @@ intel_free_memory(intel_info &info, addr_t base) status_t intel_allocate_memory(intel_info &info, size_t size, size_t alignment, - uint32 flags, addr_t *_base, phys_addr_t *_physicalBase) + uint32 flags, addr_t* _base, phys_addr_t* _physicalBase) { return gGART->allocate_memory(info.aperture, size, alignment, flags, _base, _physicalBase); @@ -202,7 +203,7 @@ intel_extreme_init(intel_info &info) AreaKeeper sharedCreator; info.shared_area = sharedCreator.Create("intel extreme shared info", - (void **)&info.shared_info, B_ANY_KERNEL_ADDRESS, + (void**)&info.shared_info, B_ANY_KERNEL_ADDRESS, ROUND_TO_PAGE_SIZE(sizeof(intel_shared_info)) + 3 * B_PAGE_SIZE, B_FULL_LOCK, 0); if (info.shared_area < B_OK) { @@ -210,7 +211,7 @@ intel_extreme_init(intel_info &info) return info.shared_area; } - memset((void *)info.shared_info, 0, sizeof(intel_shared_info)); + memset((void*)info.shared_info, 0, sizeof(intel_shared_info)); int fbIndex = 0; int mmioIndex = 1; @@ -233,17 +234,17 @@ intel_extreme_init(intel_info &info) AreaKeeper mmioMapper; info.registers_area = mmioMapper.Map("intel extreme mmio", - (void *)info.pci->u.h0.base_registers[mmioIndex], + (void*)info.pci->u.h0.base_registers[mmioIndex], info.pci->u.h0.base_register_sizes[mmioIndex], B_ANY_KERNEL_ADDRESS, B_KERNEL_READ_AREA | B_KERNEL_WRITE_AREA, - (void **)&info.registers); + (void**)&info.registers); if (mmioMapper.InitCheck() < B_OK) { dprintf(DEVICE_NAME ": could not map memory I/O!\n"); gGART->unmap_aperture(info.aperture); return info.registers_area; } - uint32 *blocks = info.shared_info->register_blocks; + uint32* blocks = info.shared_info->register_blocks; blocks[REGISTER_BLOCK(REGS_FLAT)] = 0; // setup the register blocks for the different architectures @@ -278,8 +279,9 @@ intel_extreme_init(intel_info &info) } // make sure bus master, memory-mapped I/O, and frame buffer is enabled - set_pci_config(info.pci, PCI_command, 2, get_pci_config(info.pci, PCI_command, 2) - | PCI_command_io | PCI_command_memory | PCI_command_master); + set_pci_config(info.pci, PCI_command, 2, get_pci_config(info.pci, + PCI_command, 2) | PCI_command_io | PCI_command_memory + | PCI_command_master); // reserve ring buffer memory (currently, this memory is placed in // the graphics memory), but this could bring us problems with @@ -287,7 +289,7 @@ intel_extreme_init(intel_info &info) ring_buffer &primary = info.shared_info->primary_ring_buffer; if (intel_allocate_memory(info, 16 * B_PAGE_SIZE, 0, 0, - (addr_t *)&primary.base) == B_OK) { + (addr_t*)&primary.base) == B_OK) { primary.register_base = INTEL_PRIMARY_RING_BUFFER; primary.size = 16 * B_PAGE_SIZE; primary.offset = (addr_t)primary.base - info.aperture_base; @@ -328,7 +330,7 @@ intel_extreme_init(intel_info &info) gGART->get_aperture_info(info.aperture, &apertureInfo); info.shared_info->registers_area = info.registers_area; - info.shared_info->graphics_memory = (uint8 *)info.aperture_base; + info.shared_info->graphics_memory = (uint8*)info.aperture_base; info.shared_info->physical_graphics_memory = apertureInfo.physical_base; info.shared_info->graphics_memory_size = apertureInfo.size; info.shared_info->frame_buffer = 0; @@ -361,7 +363,7 @@ intel_extreme_init(intel_info &info) if (intel_allocate_memory(info, B_PAGE_SIZE, 0, intel_uses_physical_overlay(*info.shared_info) ? B_APERTURE_NEED_PHYSICAL : 0, - (addr_t *)&info.overlay_registers, + (addr_t*)&info.overlay_registers, &info.shared_info->physical_overlay_registers) == B_OK) { info.shared_info->overlay_offset = (addr_t)info.overlay_registers - info.aperture_base; @@ -372,13 +374,13 @@ intel_extreme_init(intel_info &info) // Allocate hardware status page and the cursor memory if (intel_allocate_memory(info, B_PAGE_SIZE, 0, B_APERTURE_NEED_PHYSICAL, - (addr_t *)info.shared_info->status_page, + (addr_t*)info.shared_info->status_page, &info.shared_info->physical_status_page) == B_OK) { // TODO: set status page } if (hardwareCursor) { intel_allocate_memory(info, B_PAGE_SIZE, 0, B_APERTURE_NEED_PHYSICAL, - (addr_t *)&info.shared_info->cursor_memory, + (addr_t*)&info.shared_info->cursor_memory, &info.shared_info->physical_cursor_memory); }