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drivers/intel_extreme: Fix ValleyView block offsets

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This commit is contained in:
Alexander von Gluck IV
2015-10-22 14:48:56 -05:00
parent bc5cad7395
commit c7af18fd9c
1 changed files with 12 additions and 3 deletions
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src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp
+12 -3
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@@ -349,12 +349,21 @@ intel_extreme_init(intel_info &info)
// "I nearly got violent with the hw guys when they told me..." // "I nearly got violent with the hw guys when they told me..."
if (info.device_type.InGroup(INTEL_TYPE_VLV)) { if (info.device_type.InGroup(INTEL_TYPE_VLV)) {
TRACE("%s: ValleyView MMIO offset engaged\n", __func__); TRACE("%s: ValleyView MMIO offset engaged\n", __func__);
blocks[REGISTER_BLOCK(REGS_NORTH_PIPE_AND_PORT)] += VLV_DISPLAY_BASE;
blocks[REGISTER_BLOCK(REGS_NORTH_PLANE_CONTROL)] += VLV_DISPLAY_BASE; blocks[REGISTER_BLOCK(REGS_NORTH_PLANE_CONTROL)] += VLV_DISPLAY_BASE;
blocks[REGISTER_BLOCK(REGS_NORTH_SHARED)] += VLV_DISPLAY_BASE;
blocks[REGISTER_BLOCK(REGS_SOUTH_SHARED)] += VLV_DISPLAY_BASE;
blocks[REGISTER_BLOCK(REGS_SOUTH_TRANSCODER_PORT)] += VLV_DISPLAY_BASE;
} }
TRACE("REGS_NORTH_SHARED: 0x%X\n",
blocks[REGISTER_BLOCK(REGS_NORTH_SHARED)]);
TRACE("REGS_NORTH_PIPE_AND_PORT: 0x%X\n",
blocks[REGISTER_BLOCK(REGS_NORTH_PIPE_AND_PORT)]);
TRACE("REGS_NORTH_PLANE_CONTROL: 0x%X\n",
blocks[REGISTER_BLOCK(REGS_NORTH_PLANE_CONTROL)]);
TRACE("REGS_SOUTH_SHARED: 0x%X\n",
blocks[REGISTER_BLOCK(REGS_SOUTH_SHARED)]);
TRACE("REGS_SOUTH_TRANSCODER_PORT: 0x%X\n",
blocks[REGISTER_BLOCK(REGS_SOUTH_TRANSCODER_PORT)]);
// make sure bus master, memory-mapped I/O, and frame buffer is enabled // make sure bus master, memory-mapped I/O, and frame buffer is enabled
set_pci_config(info.pci, PCI_command, 2, get_pci_config(info.pci, set_pci_config(info.pci, PCI_command, 2, get_pci_config(info.pci,
PCI_command, 2) | PCI_command_io | PCI_command_memory PCI_command, 2) | PCI_command_io | PCI_command_memory