diff --git a/headers/private/graphics/intel_extreme/intel_extreme.h b/headers/private/graphics/intel_extreme/intel_extreme.h index a77398f3fc..9f5594bd90 100644 --- a/headers/private/graphics/intel_extreme/intel_extreme.h +++ b/headers/private/graphics/intel_extreme/intel_extreme.h @@ -571,6 +571,34 @@ struct intel_free_graphics_memory { #define INTEL_TRANSCODER_B_VBLANK (0x1010 | REGS_SOUTH_TRANSCODER_PORT) #define INTEL_TRANSCODER_B_VSYNC (0x1014 | REGS_SOUTH_TRANSCODER_PORT) +// transcoder M/N DATA AND LINK VALUES (refreshrate) +#define INTEL_TRANSCODER_A_DATA_M1 (0x0030 | REGS_SOUTH_TRANSCODER_PORT) +#define INTEL_TRANSCODER_A_DATA_M2 (0x0038 | REGS_SOUTH_TRANSCODER_PORT) +#define INTEL_TRANSCODER_B_DATA_M1 (0x1030 | REGS_SOUTH_TRANSCODER_PORT) +#define INTEL_TRANSCODER_B_DATA_M2 (0x1038 | REGS_SOUTH_TRANSCODER_PORT) +#define INTEL_TRANSCODER_C_DATA_M1 (0x2030 | REGS_SOUTH_TRANSCODER_PORT) +#define INTEL_TRANSCODER_C_DATA_M2 (0x2038 | REGS_SOUTH_TRANSCODER_PORT) +#define INTEL_TRANSCODER_A_DATA_N1 (0x0034 | REGS_SOUTH_TRANSCODER_PORT) +#define INTEL_TRANSCODER_A_DATA_N2 (0x003c | REGS_SOUTH_TRANSCODER_PORT) +#define INTEL_TRANSCODER_B_DATA_N1 (0x1034 | REGS_SOUTH_TRANSCODER_PORT) +#define INTEL_TRANSCODER_B_DATA_N2 (0x103c | REGS_SOUTH_TRANSCODER_PORT) +#define INTEL_TRANSCODER_C_DATA_N1 (0x2034 | REGS_SOUTH_TRANSCODER_PORT) +#define INTEL_TRANSCODER_C_DATA_N2 (0x203c | REGS_SOUTH_TRANSCODER_PORT) +#define INTEL_TRANSCODER_A_LINK_M1 (0x0040 | REGS_SOUTH_TRANSCODER_PORT) +#define INTEL_TRANSCODER_A_LINK_M2 (0x0048 | REGS_SOUTH_TRANSCODER_PORT) +#define INTEL_TRANSCODER_B_LINK_M1 (0x1040 | REGS_SOUTH_TRANSCODER_PORT) +#define INTEL_TRANSCODER_B_LINK_M2 (0x1048 | REGS_SOUTH_TRANSCODER_PORT) +#define INTEL_TRANSCODER_C_LINK_M1 (0x2040 | REGS_SOUTH_TRANSCODER_PORT) +#define INTEL_TRANSCODER_C_LINK_M2 (0x2048 | REGS_SOUTH_TRANSCODER_PORT) +#define INTEL_TRANSCODER_A_LINK_N1 (0x0044 | REGS_SOUTH_TRANSCODER_PORT) +#define INTEL_TRANSCODER_A_LINK_N2 (0x004c | REGS_SOUTH_TRANSCODER_PORT) +#define INTEL_TRANSCODER_B_LINK_N1 (0x1044 | REGS_SOUTH_TRANSCODER_PORT) +#define INTEL_TRANSCODER_B_LINK_N2 (0x104c | REGS_SOUTH_TRANSCODER_PORT) +#define INTEL_TRANSCODER_C_LINK_N1 (0x2044 | REGS_SOUTH_TRANSCODER_PORT) +#define INTEL_TRANSCODER_C_LINK_N2 (0x204c | REGS_SOUTH_TRANSCODER_PORT) +#define INTEL_TRANSCODER_MN_TU_SIZE_MASK (0x3f << 25) +#define INTEL_TRANSCODER_MN_VALUE_MASK (0xffffff << 0) + #define INTEL_TRANSCODER_A_IMAGE_SIZE (0x001c | REGS_SOUTH_TRANSCODER_PORT) #define INTEL_TRANSCODER_B_IMAGE_SIZE (0x101c | REGS_SOUTH_TRANSCODER_PORT) @@ -655,9 +683,14 @@ struct intel_free_graphics_memory { #define INTEL_DISPLAY_A_PIPE_CONTROL (0x0008 | REGS_NORTH_PLANE_CONTROL) #define INTEL_DISPLAY_B_PIPE_CONTROL (0x1008 | REGS_NORTH_PLANE_CONTROL) +#define INTEL_DISPLAY_C_PIPE_CONTROL (0x2008 | REGS_NORTH_PLANE_CONTROL) #define INTEL_DISPLAY_A_PIPE_STATUS (0x0024 | REGS_NORTH_PLANE_CONTROL) #define INTEL_DISPLAY_B_PIPE_STATUS (0x1024 | REGS_NORTH_PLANE_CONTROL) +#define INTEL_DISPLAY_A_PIPE_WATERMARK (0x5100 | REGS_NORTH_PLANE_CONTROL) +#define INTEL_DISPLAY_B_PIPE_WATERMARK (0x5104 | REGS_NORTH_PLANE_CONTROL) +#define INTEL_DISPLAY_C_PIPE_WATERMARK (0x5200 | REGS_NORTH_PLANE_CONTROL) + #define DISPLAY_PIPE_VBLANK_ENABLED (1UL << 17) #define DISPLAY_PIPE_VBLANK_STATUS (1UL << 1) @@ -884,6 +917,14 @@ struct intel_free_graphics_memory { #define FDI_RX_ENABLE (1 << 31) #define FDI_RX_PLL_ENABLED (1 << 13) +// Transcoder - same base as FDI_RX +#define PCH_TRANS_CONF_A 0x0008 +#define PCH_TRANS_CONF_B 0x1008 +#define PCH_TRANS_CONF_C 0x2008 + +#define TRANS_ENABLE (1 << 31) +#define TRANS_ENABLED (1 << 30) + // FDI_tX interrupt register #define FDI_RX_INTER_LANE_ALIGN (1 << 10) #define FDI_RX_SYMBOL_LOCK (1 << 9) @@ -936,6 +977,34 @@ struct intel_free_graphics_memory { #define FDI_LINK_TRAIN_PRE_EMPHASIS_2X (2 << 22) #define FDI_LINK_TRAIN_PRE_EMPHASIS_3X (3 << 22) +//FDI PIPE M/N DATA AND LINK VALUES (refreshrate) +#define PCH_FDI_PIPE_A_DATA_M1 0x0030 +#define PCH_FDI_PIPE_A_DATA_M2 0x0038 +#define PCH_FDI_PIPE_B_DATA_M1 0x1030 +#define PCH_FDI_PIPE_B_DATA_M2 0x1038 +#define PCH_FDI_PIPE_C_DATA_M1 0x2030 +#define PCH_FDI_PIPE_C_DATA_M2 0x2038 +#define PCH_FDI_PIPE_A_DATA_N1 0x0034 +#define PCH_FDI_PIPE_A_DATA_N2 0x003c +#define PCH_FDI_PIPE_B_DATA_N1 0x1034 +#define PCH_FDI_PIPE_B_DATA_N2 0x103c +#define PCH_FDI_PIPE_C_DATA_N1 0x2034 +#define PCH_FDI_PIPE_C_DATA_N2 0x203c +#define PCH_FDI_PIPE_A_LINK_M1 0x0040 +#define PCH_FDI_PIPE_A_LINK_M2 0x0048 +#define PCH_FDI_PIPE_B_LINK_M1 0x1040 +#define PCH_FDI_PIPE_B_LINK_M2 0x1048 +#define PCH_FDI_PIPE_C_LINK_M1 0x2040 +#define PCH_FDI_PIPE_C_LINK_M2 0x2048 +#define PCH_FDI_PIPE_A_LINK_N1 0x0044 +#define PCH_FDI_PIPE_A_LINK_N2 0x004c +#define PCH_FDI_PIPE_B_LINK_N1 0x1044 +#define PCH_FDI_PIPE_B_LINK_N2 0x104c +#define PCH_FDI_PIPE_C_LINK_N1 0x2044 +#define PCH_FDI_PIPE_C_LINK_N2 0x204c +#define FDI_PIPE_MN_TU_SIZE_MASK (0x3f << 25) +#define FDI_PIPE_MN_VALUE_MASK (0xffffff << 0) + // SNB A stepping #define FDI_LINK_TRAIN_400MV_0DB_SNB_A (0x38 << 22) #define FDI_LINK_TRAIN_400MV_6DB_SNB_A (0x02 << 22) @@ -998,6 +1067,14 @@ struct intel_free_graphics_memory { #define PANEL_FITTER_SCALING_MODE_MASK (7 << 26) #define PANEL_FITTER_FILTER_MASK (3 << 24) +// panel fitters again, more directly +#define INTEL_PANELFITTER_0_CTRL (0x8080 | REGS_NORTH_PIPE_AND_PORT) +#define INTEL_PANELFITTER_1_CTRL (0x8880 | REGS_NORTH_PIPE_AND_PORT) +#define INTEL_PANELFITTER_2_CTRL (0x9080 | REGS_NORTH_PIPE_AND_PORT) +#define INTEL_PANELFITTER_0_WINDOW_SIZE (0x8074 | REGS_NORTH_PIPE_AND_PORT) +#define INTEL_PANELFITTER_1_WINDOW_SIZE (0x8874 | REGS_NORTH_PIPE_AND_PORT) +#define INTEL_PANELFITTER_2_WINDOW_SIZE (0x9074 | REGS_NORTH_PIPE_AND_PORT) + struct overlay_scale { uint32 _reserved0 : 3; uint32 horizontal_scale_fraction : 12; diff --git a/src/add-ons/accelerants/intel_extreme/Pipes.cpp b/src/add-ons/accelerants/intel_extreme/Pipes.cpp index f3167d87f8..5eeef0ba20 100644 --- a/src/add-ons/accelerants/intel_extreme/Pipes.cpp +++ b/src/add-ons/accelerants/intel_extreme/Pipes.cpp @@ -101,43 +101,21 @@ Pipe::IsEnabled() void Pipe::Configure(display_mode* mode) { -#if 0 - // FIXME the previous values are never masked out from the - // register, so we just OR things together and hope to fall on a working - // mode. Better do nothing at all for now. uint32 pipeControl = read32(INTEL_DISPLAY_A_PIPE_CONTROL + fPipeOffset); // TODO: Haswell+ dithering changes. - if (gInfo->shared_info->device_type.Generation() >= 4) { - pipeControl |= (INTEL_PIPE_DITHER_EN | INTEL_PIPE_DITHER_TYPE_SP); - // FIXME this makes no sense, if only because B_CMAP8, B_RGB24 and - // B_RGB32 have the same color precision (8bit per component). - // Also because the color mode is a property of the hardware - // (depends on which LVDS panel is used, typically), not the video mode. - switch (mode->space) { - case B_CMAP8: - case B_RGB15_LITTLE: - case B_RGB16_LITTLE: - pipeControl |= INTEL_PIPE_6BPC; - break; - case B_RGB24_LITTLE: - pipeControl |= INTEL_PIPE_8BPC; - break; - case B_RGB32_LITTLE: - default: - pipeControl |= INTEL_PIPE_10BPC; - break; - } - } + //if (gInfo->shared_info->device_type.Generation() >= 4) { + // pipeControl |= (INTEL_PIPE_DITHER_EN | INTEL_PIPE_DITHER_TYPE_SP); + //Link bit depth, which is currently hardcoded to 8-bits per color + pipeControl = (pipeControl & ~(0x7 << 5)) | INTEL_PIPE_8BPC; // TODO: CxSR downclocking? // TODO: Interlaced modes - pipeControl |= INTEL_PIPE_PROGRESSIVE; + pipeControl = (pipeControl & ~(0x7 << 21)) | INTEL_PIPE_PROGRESSIVE; write32(INTEL_DISPLAY_A_PIPE_CONTROL + fPipeOffset, pipeControl); read32(INTEL_DISPLAY_A_PIPE_CONTROL + fPipeOffset); -#endif if (gInfo->shared_info->device_type.Generation() >= 6) { // According to SandyBridge modesetting sequence, pipe must be enabled @@ -277,6 +255,10 @@ Pipe::ConfigureClocks(const pll_divisors& divisors, uint32 pixelClock, pllMD = INTEL_DISPLAY_B_PLL_MD; } + // Disable DPLL first + write32(pllControl, read32(pllControl) & ~DISPLAY_PLL_ENABLED); + spin(150); + float refFreq = gInfo->shared_info->pll_info.reference_frequency / 1000.0f; if (gInfo->shared_info->device_type.InGroup(INTEL_GROUP_96x)) { @@ -311,6 +293,8 @@ Pipe::ConfigureClocks(const pll_divisors& divisors, uint32 pixelClock, & DISPLAY_PLL_M2_DIVISOR_MASK)); } + //note: bit DISPLAY_PLL_NO_VGA_CONTROL does not exist on IvyBridge and should be left + // zero there. It does not influence it though. uint32 pll = DISPLAY_PLL_ENABLED | DISPLAY_PLL_NO_VGA_CONTROL | extraFlags; if (gInfo->shared_info->device_type.Generation() >= 3) { @@ -353,13 +337,14 @@ Pipe::ConfigureClocks(const pll_divisors& divisors, uint32 pixelClock, pll |= DISPLAY_PLL_POST1_DIVIDE_2; } - write32(pllControl, pll & ~DISPLAY_PLL_NO_VGA_CONTROL); - // FIXME what is this doing? Why put the PLL back under VGA_CONTROL - // here? + // Configure PLL while -keeping- it disabled + //note: on older chipsets DISPLAY_PLL_NO_VGA_CONTROL probably enables the PLL and locks regs; + // on newer chipsets DISPLAY_PLL_ENABLED does this. + write32(pllControl, pll & ~DISPLAY_PLL_ENABLED & ~DISPLAY_PLL_NO_VGA_CONTROL); read32(pllControl); spin(150); - // Configure and enable the PLL + // enable pre-configured PLL (locks PLL settings directly blocking changes in this write even) write32(pllControl, pll); read32(pllControl); @@ -401,7 +386,6 @@ Pipe::ConfigureClocks(const pll_divisors& divisors, uint32 pixelClock, } } - void Pipe::Enable(bool enable) { @@ -416,12 +400,19 @@ Pipe::Enable(bool enable) write32(pipeReg, read32(pipeReg) | INTEL_PIPE_ENABLED); wait_for_vblank(); write32(planeReg, read32(planeReg) | DISPLAY_CONTROL_ENABLED); + + //Enable default display main watermarks + write32(INTEL_DISPLAY_A_PIPE_WATERMARK, 0x0783818); } else { write32(planeReg, read32(planeReg) & ~DISPLAY_CONTROL_ENABLED); wait_for_vblank(); - write32(pipeReg, read32(pipeReg) & ~INTEL_PIPE_ENABLED); + //Sandy+: when link training is to be done re-enable this line but otherwise don't touch! + //GMA(Q45): must disable PIPE or DPLL programming fails. + if (gInfo->shared_info->device_type.Generation() <= 5) { + write32(pipeReg, read32(pipeReg) & ~INTEL_PIPE_ENABLED); + } } + // flush the eventually cached PCI bus writes read32(INTEL_DISPLAY_A_BASE); - // flush the eventually cached PCI bus writes } diff --git a/src/add-ons/accelerants/intel_extreme/mode.cpp b/src/add-ons/accelerants/intel_extreme/mode.cpp index 8220f4a9be..cf9dba3dfc 100644 --- a/src/add-ons/accelerants/intel_extreme/mode.cpp +++ b/src/add-ons/accelerants/intel_extreme/mode.cpp @@ -480,6 +480,7 @@ intel_set_display_mode(display_mode* mode) set_frame_buffer_base(); // triggers writing back double-buffered registers + // which is INTEL_DISPLAY_X_BYTES_PER_ROW only apparantly // Second register dump //dump_registers();