From c80ea549756fe8d3655f71153801dcd90e72bb69 Mon Sep 17 00:00:00 2001 From: Rudolf Cornelissen Date: Sun, 5 Dec 2021 16:56:15 +0000 Subject: [PATCH] intel_extreme: PLLs post skylake work differently again. Refclk update. --- .../graphics/intel_extreme/intel_extreme.h | 8 +++ .../accelerants/intel_extreme/Ports.cpp | 53 ++++++++++--------- src/add-ons/accelerants/intel_extreme/pll.cpp | 3 +- .../graphics/intel_extreme/intel_extreme.cpp | 26 ++++++++- 4 files changed, 63 insertions(+), 27 deletions(-) diff --git a/headers/private/graphics/intel_extreme/intel_extreme.h b/headers/private/graphics/intel_extreme/intel_extreme.h index 731b052a73..a3b18c0ffc 100644 --- a/headers/private/graphics/intel_extreme/intel_extreme.h +++ b/headers/private/graphics/intel_extreme/intel_extreme.h @@ -616,6 +616,14 @@ struct intel_free_graphics_memory { #define SKL_DPLL_CTRL2 (0xc05c | REGS_NORTH_PIPE_AND_PORT) #define SKL_DPLL_STATUS (0xc060 | REGS_NORTH_PIPE_AND_PORT) +// Icelake PLLs +#define ICL_DSSM 0x51004 +#define ICL_DSSM_REF_FREQ_SHIFT 29 +#define ICL_DSSM_REF_FREQ_MASK (7 << ICL_DSSM_REF_FREQ_SHIFT) +#define ICL_DSSM_24000 0 +#define ICL_DSSM_19200 1 +#define ICL_DSSM_38400 2 + // display #define INTEL_DISPLAY_OFFSET 0x1000 diff --git a/src/add-ons/accelerants/intel_extreme/Ports.cpp b/src/add-ons/accelerants/intel_extreme/Ports.cpp index 2863ff6706..00006fb8b1 100644 --- a/src/add-ons/accelerants/intel_extreme/Ports.cpp +++ b/src/add-ons/accelerants/intel_extreme/Ports.cpp @@ -1364,30 +1364,35 @@ DigitalDisplayInterface::IsConnected() return false; } - // Probe a little port info. - if ((read32(DDI_BUF_CTL_A) & DDI_A_4_LANES) != 0) { - switch (PortIndex()) { - case INTEL_PORT_A: - fMaxLanes = 4; - break; - case INTEL_PORT_E: - fMaxLanes = 0; - break; - default: - fMaxLanes = 4; - break; - } - } else { - switch (PortIndex()) { - case INTEL_PORT_A: - fMaxLanes = 2; - break; - case INTEL_PORT_E: - fMaxLanes = 2; - break; - default: - fMaxLanes = 4; - break; + // newer chipsets support 4 lanes on all ports + fMaxLanes = 4; + if ((gInfo->shared_info->device_type.Generation() < 9) || + gInfo->shared_info->device_type.InGroup(INTEL_GROUP_SKY)) { + // Probe a little port info. + if ((read32(DDI_BUF_CTL_A) & DDI_A_4_LANES) != 0) { + switch (PortIndex()) { + case INTEL_PORT_A: + fMaxLanes = 4; + break; + case INTEL_PORT_E: + fMaxLanes = 0; + break; + default: + fMaxLanes = 4; + break; + } + } else { + switch (PortIndex()) { + case INTEL_PORT_A: + fMaxLanes = 2; + break; + case INTEL_PORT_E: + fMaxLanes = 2; + break; + default: + fMaxLanes = 4; + break; + } } } diff --git a/src/add-ons/accelerants/intel_extreme/pll.cpp b/src/add-ons/accelerants/intel_extreme/pll.cpp index dff8d0006e..96517b9f0e 100644 --- a/src/add-ons/accelerants/intel_extreme/pll.cpp +++ b/src/add-ons/accelerants/intel_extreme/pll.cpp @@ -980,6 +980,7 @@ static void skl_wrpll_params_populate(struct skl_wrpll_params *params, (uint64)params->dco_integer * 1000000) * 0x8000 / 1000000; + TRACE("%s: Reference clock: %gMhz\n", __func__, ref_clock / 1000.0f); TRACE("%s: DCO integer %" B_PRIu32 "\n", __func__, params->dco_integer); TRACE("%s: DCO fraction 0x%" B_PRIx32 "\n", __func__, params->dco_fraction); } @@ -1047,7 +1048,7 @@ skip_remaining_dividers: TRACE("%s: No valid divider found for %dHz\n", __func__, clock); return false; } - TRACE("%s: Full devider (p) found is %d\n", __func__, ctx.p); + TRACE("%s: Full divider (p) found is %d\n", __func__, ctx.p); /* * gcc incorrectly analyses that these can be used without being diff --git a/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp b/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp index 5bcbb95ae5..623919a425 100644 --- a/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp +++ b/src/add-ons/kernel/drivers/graphics/intel_extreme/intel_extreme.cpp @@ -462,16 +462,38 @@ intel_extreme_init(intel_info &info) info.shared_info->pll_info.max_frequency = 400000; // 400 MHz RAM DAC speed info.shared_info->pll_info.min_frequency = 20000; // 20 MHz - } else if ((info.device_type.HasDDI()) && (info.device_type.Generation() <= 8)) { + } else if (info.device_type.HasDDI() && (info.device_type.Generation() <= 8)) { info.shared_info->pll_info.reference_frequency = 135000;// 135 MHz info.shared_info->pll_info.max_frequency = 350000; // 350 MHz RAM DAC speed info.shared_info->pll_info.min_frequency = 25000; // 25 MHz - } else if (info.device_type.Generation() == 9) { + } else if ((info.device_type.Generation() == 9) && + info.device_type.InGroup(INTEL_GROUP_SKY)) { info.shared_info->pll_info.reference_frequency = 24000; // 24 MHz info.shared_info->pll_info.max_frequency = 350000; // 350 MHz RAM DAC speed info.shared_info->pll_info.min_frequency = 25000; // 25 MHz + } else if (info.device_type.Generation() == 9) { + uint32 refInfo = + (read32(info, ICL_DSSM) & ICL_DSSM_REF_FREQ_MASK) >> ICL_DSSM_REF_FREQ_SHIFT; + switch (refInfo) { + case ICL_DSSM_24000: + info.shared_info->pll_info.reference_frequency = 24000; // 24 MHz + break; + case ICL_DSSM_19200: + info.shared_info->pll_info.reference_frequency = 19200; // 19.2 MHz + break; + case ICL_DSSM_38400: + info.shared_info->pll_info.reference_frequency = 38400; // 38.4 MHz + break; + default: + ERROR("error: unknown ref. freq. strap, using 24Mhz! %" B_PRIx32 "\n", refInfo); + info.shared_info->pll_info.reference_frequency = 24000; // 24 MHz + break; + } + info.shared_info->pll_info.max_frequency = 350000; + // 350 MHz RAM DAC speed + info.shared_info->pll_info.min_frequency = 25000; // 25 MHz } else { info.shared_info->pll_info.reference_frequency = 48000; // 48 MHz info.shared_info->pll_info.max_frequency = 350000;