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finally! NV28 up and running as secondary card over here: added some framebuffer access registerprogramming apparantly needed. Now all cards work as secondary card over here :-)

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git-svn-id: file:///srv/svn/repos/haiku/trunk/current@9449 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Rudolf Cornelissen
2004-10-22 20:50:30 +00:00
parent 9e7f8b786d
commit c9ae7f9cc9
1 changed files with 21 additions and 0 deletions
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src/add-ons/accelerants/nvidia/engine/nv_info.c
+21
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@@ -296,9 +296,19 @@ static status_t coldstart_card_516_up(uint8* rom, PinsTables tabs, uint16 ram_ta
{ {
status_t result = B_OK; status_t result = B_OK;
uint16 adress; uint16 adress;
uint32 fb_mrs1 = 0;
uint32 fb_mrs2 = 0;
LOG(8,("INFO: now executing coldstart...\n")); LOG(8,("INFO: now executing coldstart...\n"));
/* get some strapinfo(?) for NV28 framebuffer access */
//fixme?: works on at least one NV28... how about other cards?
if (si->ps.card_type == NV28)
{
fb_mrs2 = NV_REG32(NV32_FB_MRS2);
fb_mrs1 = NV_REG32(NV32_FB_MRS1);
}
/* select colormode CRTC registers base adresses */ /* select colormode CRTC registers base adresses */
NV_REG8(NV8_MISCW) = 0xcb; NV_REG8(NV8_MISCW) = 0xcb;
@@ -358,6 +368,14 @@ static status_t coldstart_card_516_up(uint8* rom, PinsTables tabs, uint16 ram_ta
adress = *((uint16*)(&(rom[index]))); adress = *((uint16*)(&(rom[index])));
} }
/* get NV28 RAM access up and running */
//fixme?: works on at least one NV28... how about other cards?
if (si->ps.card_type == NV28)
{
NV_REG32(NV32_FB_MRS2) = fb_mrs2;
NV_REG32(NV32_FB_MRS1) = fb_mrs1;
}
/* now enable ROM shadow or the card will remain shut-off! */ /* now enable ROM shadow or the card will remain shut-off! */
CFGW(ROMSHADOW, (CFGR(ROMSHADOW) |= 0x00000001)); CFGW(ROMSHADOW, (CFGR(ROMSHADOW) |= 0x00000001));
@@ -1421,6 +1439,9 @@ static status_t exec_type2_script_mode(uint8* rom, uint16* adress, int16* size,
*exec = true; *exec = true;
break; break;
case 0x74: /* identical to type1 */ case 0x74: /* identical to type1 */
//fixme? on at least NV28 this cmd hammers the CRTC PCI-timeout register
//'data' number of times instead of snoozing.
//Couldn't see any diff in behaviour though!
*size -= 3; *size -= 3;
if (*size < 0) if (*size < 0)
{ {