From cb050a33beef2d4e477b4d100d6bce55943b1881 Mon Sep 17 00:00:00 2001
From: Alexander von Gluck IV <kallisti5@unixzen.com>
Date: Thu, 24 Nov 2011 19:42:45 -0600
Subject: [PATCH] Add support for thermal status queries on newer chipsets

* add temperature query support for Juniper, Sumo, Evergreen, and North Islands
* add missing thermal defines for evergreen cards
* northern island cards use the evergreen thermal calculations
---
 .../private/graphics/radeon_hd/evergreend.h   | 13 ++++++
 src/add-ons/accelerants/radeon_hd/gpu.cpp     | 40 +++++++++++++++++--
 2 files changed, 49 insertions(+), 4 deletions(-)

diff --git a/headers/private/graphics/radeon_hd/evergreend.h b/headers/private/graphics/radeon_hd/evergreend.h
index 25abc28a00..6aba71c40e 100644
--- a/headers/private/graphics/radeon_hd/evergreend.h
+++ b/headers/private/graphics/radeon_hd/evergreend.h
@@ -80,5 +80,18 @@
 #define	EVERGREEN_SCRATCH_UMSK						0x8540
 #define	EVERGREEN_SCRATCH_ADDR						0x8544
 
+/* evergreen */
+#define EVERGREEN_CG_THERMAL_CTRL					0x72c
+#define		EVERGREEN_TOFFSET_MASK					0x00003FE0
+#define		EVERGREEN_TOFFSET_SHIFT					5
+#define EVERGREEN_CG_MULT_THERMAL_STATUS			0x740
+#define		EVERGREEN_ASIC_T(x)						((x) << 16)
+#define		EVERGREEN_ASIC_T_MASK					0x07FF0000
+#define     EVERGREEN_ASIC_T_SHIFT					16
+#define EVERGREEN_CG_TS0_STATUS						0x760
+#define		EVERGREEN_TS0_ADC_DOUT_MASK				0x000003FF
+#define		EVERGREEN_TS0_ADC_DOUT_SHIFT			0
+/* APU */
+#define EVERGREEN_CG_THERMAL_STATUS					0x678
 
 #endif
diff --git a/src/add-ons/accelerants/radeon_hd/gpu.cpp b/src/add-ons/accelerants/radeon_hd/gpu.cpp
index 038ae4020e..c9213fc5c0 100644
--- a/src/add-ons/accelerants/radeon_hd/gpu.cpp
+++ b/src/add-ons/accelerants/radeon_hd/gpu.cpp
@@ -783,10 +783,43 @@ radeon_get_temp()
 
 	radeon_shared_info &info = *gInfo->shared_info;
 
-	uint32 rawTemp = 0;	// temp
-	int32 finalTemp = 0; // actual_temp
+	uint32 rawTemp = 0;
+	int32 finalTemp = 0;
 
-	if (info.chipsetID >= RADEON_RV770) {
+	if (info.chipsetID == RADEON_JUNIPER) {
+		uint32 offset = (Read32(OUT, EVERGREEN_CG_THERMAL_CTRL)
+			& EVERGREEN_TOFFSET_MASK) >> EVERGREEN_TOFFSET_SHIFT;
+		rawTemp = (Read32(OUT, EVERGREEN_CG_TS0_STATUS)
+			& EVERGREEN_TS0_ADC_DOUT_MASK) >> EVERGREEN_TS0_ADC_DOUT_SHIFT;
+
+		if (offset & 0x100)
+			finalTemp = rawTemp / 2 - (0x200 - offset);
+		else
+			finalTemp = rawTemp / 2 + offset;
+
+		return finalTemp * 1000;
+	} else if (info.chipsetID == RADEON_SUMO
+		|| info.chipsetID == RADEON_SUMO2) {
+		uint32 rawTemp = Read32(OUT, EVERGREEN_CG_THERMAL_STATUS) & 0xff;
+		finalTemp = rawTemp - 49;
+
+		return finalTemp * 1000;
+	} else if (info.chipsetID >= RADEON_CEDAR) {
+		rawTemp = (Read32(OUT, EVERGREEN_CG_MULT_THERMAL_STATUS)
+			& EVERGREEN_ASIC_T_MASK) >> EVERGREEN_ASIC_T_SHIFT;
+
+		if (rawTemp & 0x400)
+			finalTemp = -256;
+		else if (rawTemp & 0x200)
+			finalTemp = 255;
+		else if (rawTemp & 0x100) {
+			finalTemp = rawTemp & 0x1ff;
+			finalTemp |= ~0x1ff;
+		} else
+			finalTemp = rawTemp & 0xff;
+
+		return (finalTemp * 1000) / 2;
+	} else if (info.chipsetID >= RADEON_RV770) {
 		rawTemp = (Read32(OUT, R700_CG_MULT_THERMAL_STATUS) & R700_ASIC_T_MASK)
 			>> R700_ASIC_T_SHIFT;
 		if (rawTemp & 0x400)
@@ -800,7 +833,6 @@ radeon_get_temp()
 			finalTemp = rawTemp & 0xff;
 
 		return (finalTemp * 1000) / 2;
-
 	} else if (info.chipsetID >= RADEON_R600) {
 		rawTemp = (Read32(OUT, R600_CG_THERMAL_STATUS) & R600_ASIC_T_MASK)
 			>> R600_ASIC_T_SHIFT;