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* Fixed PLL timing computation for the i9xx chips - I mixed post2 min/max values, and did

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not take the VCO limits into account; both could (and would during testing) create invalid
  frequencies.
* Also reverted the order in which the PLL divisors are traversed to match the order of what
  is used in the X driver to create comparable output (our error computation is based on float,
  though, and should therefore create more accurate values).
* The i965 introduced a special register for the surface; the former display base register
  is now only used for the view offset. Instead of setting the base manually here and there,
  there is now a set_frame_buffer_base() function.
* The DPMS code will now also turn off/on the PLL clock generator.
* The code needs some more cleanup, and while the driver now produces the correct timing on
  my i965 system, I'm now greeted by a black screen after startup.


git-svn-id: file:///srv/svn/repos/haiku/haiku/trunk@22289 a95241bf-73f2-0310-859d-f6bbb57e9c96
This commit is contained in:
Axel Dörfler
2007-09-24 09:02:35 +00:00
parent 9c7408528e
commit cbd4081064
5 changed files with 126 additions and 64 deletions
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headers/private/graphics/intel_extreme/intel_extreme.h
+3
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@@ -194,6 +194,7 @@ struct intel_free_graphics_memory {
#define INTEL_DISPLAY_A_CONTROL 0x70180
#define INTEL_DISPLAY_A_BASE 0x70184
#define INTEL_DISPLAY_A_BYTES_PER_ROW 0x70188
#define INTEL_DISPLAY_A_SURFACE 0x7019c // i965 and up only
#define DISPLAY_CONTROL_ENABLED (1UL << 31)
#define DISPLAY_CONTROL_GAMMA (1UL << 30)
#define DISPLAY_CONTROL_COLOR_MASK (0x0fUL << 26)
@@ -238,6 +239,7 @@ struct intel_free_graphics_memory {
#define INTEL_DISPLAY_A_ANALOG_PORT 0x61100
#define DISPLAY_MONITOR_PORT_ENABLED (1UL << 31)
#define DISPLAY_MONITOR_PIPE_B (1UL << 30)
#define DISPLAY_MONITOR_VGA_POLARITY (1UL << 15)
#define DISPLAY_MONITOR_MODE_MASK (3UL << 10)
#define DISPLAY_MONITOR_ON 0
@@ -257,6 +259,7 @@ struct intel_free_graphics_memory {
#define INTEL_DISPLAY_B_CONTROL 0x71180
#define INTEL_DISPLAY_B_BASE 0x71184
#define INTEL_DISPLAY_B_BYTES_PER_ROW 0x71188
#define INTEL_DISPLAY_B_SURFACE 0x7119c // i965 and up only
#define INTEL_DISPLAY_B_PALETTE 0x0a800