x86: AMD C1E with no ARAT(Always Running APIC Timer) idle support

AMD C1E is a BIOS controlled C3 state. Certain processors families
may cut off TSC and the lapic timer when it is in a deep C state,
including C1E state, thus the cpu can't be waken up and system will hang.

This patch firstly adds the support of idle selection during boot. Then
it implements amdc1e_noarat_idle() routine which checks the MSR which
contains the C1eOnCmpHalt (bit 28) and SmiOnCmpHalt (bit 27)  before
executing the halt instruction, then clear them once set.

However intel C1E doesn't has such problem. AMD C1E is a BIOS controlled
C3 state. The difference between C1E and C3 is that transition into C1E
is not initiated by the operating system. System will enter C1E state
automatically when both cores enters C1 state. As for intel C1E, it
means "reduce CPU voltage before entering corresponding Cx-state".

This patch may fix #8111, #3999, #7562, #7940 and #8060

Copied from the description of #3999:
>but for some reason I hit the power button instead of the reset one. And
>the boot continued!!
The reason is CPUs are waken up once power button is hit.

Signed-off-by: Fredrik Holmqvist <[email protected]>

This commit is contained in:

Yongcong Du

2012-04-14 18:18:29 +02:00

committed by

Fredrik Holmqvist

parent eaa5e0936d

commit cc586f1655

2 changed files with 52 additions and 1 deletions

									
										headers/private/kernel/arch/x86/arch_cpu.h
									
		+3
		
												View File
												
				@@ -33,6 +33,9 @@

				#define IA32_MSR_MTRR_PHYSICAL_BASE_0	0x200

				#define IA32_MSR_MTRR_PHYSICAL_MASK_0	0x201

				// K8 MSR registers

				#define K8_MSR_IPM						0xc0010055

				// x86 features from cpuid eax 1, edx register

				// reference http://www.intel.com/assets/pdf/appnote/241618.pdf (Table 5-5)

				#define IA32_FEATURE_FPU	(1 << 0) // x87 fpu