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intel_extreme: Clear all framebuffer tile mode bits

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Some newer architecture added Y tiling

Maybe fixes #17688

Change-Id: I048c2523b8a804e53752f12cfed436616a6a6964
Reviewed-on: https://review.haiku-os.org/c/haiku/+/11027
Tested-by: Commit checker robot <[email protected]>
Reviewed-by: waddlesplash <[email protected]>
This commit is contained in:
Sam Roberts
2026-05-28 12:20:19 +00:00
committed by Jérôme Duval
parent 0088ac13b0
commit ce692ecc03
2 changed files with 2 additions and 2 deletions
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headers/private/graphics/intel_extreme/intel_extreme.h
+1 -1
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@@ -1316,7 +1316,7 @@ struct intel_brightness_legacy {
#define DISPLAY_CONTROL_RGB16_SKY (0x0eUL << 24) #define DISPLAY_CONTROL_RGB16_SKY (0x0eUL << 24)
#define DISPLAY_CONTROL_RGB32_SKY (0x04UL << 24) #define DISPLAY_CONTROL_RGB32_SKY (0x04UL << 24)
#define DISPLAY_CONTROL_RGB64_SKY (0x06UL << 24) #define DISPLAY_CONTROL_RGB64_SKY (0x06UL << 24)
#define DISPLAY_CONTROL_X_TILED (1UL << 10) #define DISPLAY_CONTROL_TILE_MODE_MASK (7UL << 10)
// INTEL_DISPLAY_A_PIPE_CONTROL ILK+ // INTEL_DISPLAY_A_PIPE_CONTROL ILK+
#define INTEL_PIPE_DITHER_TYPE_MASK (0x0000000c) #define INTEL_PIPE_DITHER_TYPE_MASK (0x0000000c)
src/add-ons/accelerants/intel_extreme/Pipes.cpp
+1 -1
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@@ -636,7 +636,7 @@ Pipe::Enable(bool enable)
write32(pipeReg, read32(pipeReg) | INTEL_PIPE_ENABLED); write32(pipeReg, read32(pipeReg) | INTEL_PIPE_ENABLED);
wait_for_vblank(); wait_for_vblank();
write32(planeReg, (read32(planeReg) | DISPLAY_CONTROL_ENABLED) write32(planeReg, (read32(planeReg) | DISPLAY_CONTROL_ENABLED)
& ~DISPLAY_CONTROL_X_TILED); & ~DISPLAY_CONTROL_TILE_MODE_MASK);
//Enable default display main watermarks //Enable default display main watermarks
if (gInfo->shared_info->pch_info == INTEL_PCH_CPT) { if (gInfo->shared_info->pch_info == INTEL_PCH_CPT) {