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arm64: Reuse possible TTBR1 allocations only if we come from a valid EL1 context.

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* This allows rPI3 reaching the kernel
* Handling & reporting this value helps understanding the behaviour of the different boot contexts
* As long as more real HW platforms are being ported, reusing this value needs to be reevaluated

Change-Id: I1a3b6d8e1df7c9a131875daf2c7abb64b6061ce8
Reviewed-on: https://review.haiku-os.org/c/haiku/+/5234
Tested-by: Commit checker robot <[email protected]>
Reviewed-by: David Karoly <[email protected]>
Reviewed-by: Fredrik Holmqvist <[email protected]>
This commit is contained in:
urnenfeld
2022-04-23 14:59:22 +00:00
committed by Fredrik Holmqvist
parent 8b858379e2
commit ce72745ebe
1 changed files with 13 additions and 3 deletions
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src/system/boot/platform/efi/arch/arm64/arch_mmu.cpp
+13 -3
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@@ -408,7 +408,19 @@ arch_mmu_post_efi_setup(size_t memory_map_size,
void void
arch_mmu_allocate_kernel_page_tables(void) arch_mmu_allocate_kernel_page_tables(void)
{ {
uint64* page = reinterpret_cast<uint64*>(READ_SPECIALREG(TTBR1_EL1)); uint64* page = NULL;
uint64 ttbr1 = READ_SPECIALREG(TTBR1_EL1);
// Trust possible previous allocations of TTBR1
// only if we come from a preset EL1 context
if (ttbr1 != 0ll) {
if (arch_exception_level() == 1) {
page = reinterpret_cast<uint64*>(ttbr1);
TRACE(("Resusing TTBR1_EL1 present : %" B_PRIx64 "\n", ttbr1));
} else if (arch_exception_level() == 2) {
TRACE(("Ignoring EL1 TTBR1(%" B_PRIx64") tables\n", ttbr1));
}
}
// NOTE: On devices supporting multiple translation base registers, TTBR0 must // NOTE: On devices supporting multiple translation base registers, TTBR0 must
// be used solely. // be used solely.
@@ -419,8 +431,6 @@ arch_mmu_allocate_kernel_page_tables(void)
} else { } else {
panic("Not enough memory for kernel initial page\n"); panic("Not enough memory for kernel initial page\n");
} }
} else {
TRACE(("TTBR1_EL1 present ..."));
} }
sPageDirectory = page; sPageDirectory = page;