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intel_extreme: log srcclk info, Sandy/Ivy eDP detect BIOS pipe setup and use that.

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Rudolf Cornelissen
2022-02-12 23:29:42 +01:00
parent 9aa0aea3a8
commit cfd3bb41aa
3 changed files with 47 additions and 0 deletions
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headers/private/graphics/intel_extreme/intel_extreme.h
+10
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@@ -857,6 +857,16 @@ struct intel_free_graphics_memory {
#define INTEL_DISPLAY_PORT_C (0x4200 | REGS_SOUTH_TRANSCODER_PORT)
#define INTEL_DISPLAY_PORT_D (0x4300 | REGS_SOUTH_TRANSCODER_PORT)
#define INTEL_DISP_PORTA_SNB_PIPE_SHIFT 30
#define INTEL_DISP_PORTA_SNB_PIPE_MASK (1 << INTEL_DISP_PORTA_SNB_PIPE_SHIFT)
#define INTEL_DISP_PORTA_SNB_PIPE_A 0
#define INTEL_DISP_PORTA_SNB_PIPE_B 1
#define INTEL_DISP_PORTA_IVB_PIPE_SHIFT 29
#define INTEL_DISP_PORTA_IVB_PIPE_MASK (3 << INTEL_DISP_PORTA_IVB_PIPE_SHIFT)
#define INTEL_DISP_PORTA_IVB_PIPE_A 0
#define INTEL_DISP_PORTA_IVB_PIPE_B 1
#define INTEL_DISP_PORTA_IVB_PIPE_C 2
#define INTEL_DISP_PORT_WIDTH_SHIFT 19
#define INTEL_DISP_PORT_WIDTH_MASK (7 << INTEL_DISP_PORT_WIDTH_SHIFT)
#define INTEL_DISP_PORT_WIDTH_1 0