From d442692fab98226e7032847100595a67165fbf15 Mon Sep 17 00:00:00 2001 From: Alexander von Gluck IV Date: Mon, 9 Nov 2015 09:15:16 -0600 Subject: [PATCH] intel_extreme: Correct DP port registers --- headers/private/graphics/intel_extreme/intel_extreme.h | 7 ++++--- 1 file changed, 4 insertions(+), 3 deletions(-) diff --git a/headers/private/graphics/intel_extreme/intel_extreme.h b/headers/private/graphics/intel_extreme/intel_extreme.h index 30fbd29957..4534a76703 100644 --- a/headers/private/graphics/intel_extreme/intel_extreme.h +++ b/headers/private/graphics/intel_extreme/intel_extreme.h @@ -510,10 +510,11 @@ struct intel_free_graphics_memory { #define GEN4_HDMI_PORT_C (0x1160 | REGS_NORTH_PIPE_AND_PORT) #define CHV_HDMI_PORT_D (0x116C | REGS_NORTH_PIPE_AND_PORT) +// DP_A always @ 6xxxx, DP_B-DP_D move with PCH #define INTEL_DISPLAY_PORT_A (0x4000 | REGS_NORTH_PIPE_AND_PORT) -#define INTEL_DISPLAY_PORT_B (0x4100 | REGS_NORTH_PIPE_AND_PORT) -#define INTEL_DISPLAY_PORT_C (0x4200 | REGS_NORTH_PIPE_AND_PORT) -#define INTEL_DISPLAY_PORT_D (0x4300 | REGS_NORTH_PIPE_AND_PORT) +#define INTEL_DISPLAY_PORT_B (0x4100 | REGS_SOUTH_TRANSCODER_PORT) +#define INTEL_DISPLAY_PORT_C (0x4200 | REGS_SOUTH_TRANSCODER_PORT) +#define INTEL_DISPLAY_PORT_D (0x4300 | REGS_SOUTH_TRANSCODER_PORT) // planes #define INTEL_PIPE_ENABLED (1UL << 31)