From d472f38a495ac158fde1fa74dc5d36a764a789f8 Mon Sep 17 00:00:00 2001
From: X512 <danger_mail@list.ru>
Date: Mon, 26 Jul 2021 03:13:16 +0900
Subject: [PATCH] riscv64: update hardware definition headers

Change-Id: I0c84f1d5389842d4591cb1548793e08155ba3666
Reviewed-on: https://review.haiku-os.org/c/haiku/+/4311
Reviewed-by: Alex von Gluck IV <kallisti5@unixzen.com>
---
 headers/private/kernel/arch/riscv64/Clint.h   |  6 +--
 .../system/arch/riscv64/arch_cpu_defs.h       | 38 ++++++++++++++++---
 2 files changed, 36 insertions(+), 8 deletions(-)

diff --git a/headers/private/kernel/arch/riscv64/Clint.h b/headers/private/kernel/arch/riscv64/Clint.h
index 384f316d11..1079e4d24f 100644
--- a/headers/private/kernel/arch/riscv64/Clint.h
+++ b/headers/private/kernel/arch/riscv64/Clint.h
@@ -12,9 +12,9 @@
 // core local interruptor
 struct ClintRegs
 {
-	uint8  unknown1[0x4000];
-	uint64 mTimeCmp[4095]; // per CPU core, but not implemented in temu
-	uint64 mTime;          // @0xBFF8
+	uint32 msip    [4096]; // machine software interrupt pending, per CPU core
+	uint64 mtimecmp[4095]; // per CPU core
+	uint64 mtime;          // @0xBFF8
 };
 
 extern ClintRegs* volatile gClintRegs;
diff --git a/headers/private/system/arch/riscv64/arch_cpu_defs.h b/headers/private/system/arch/riscv64/arch_cpu_defs.h
index a456d501a0..5db5cff536 100644
--- a/headers/private/system/arch/riscv64/arch_cpu_defs.h
+++ b/headers/private/system/arch/riscv64/arch_cpu_defs.h
@@ -112,6 +112,18 @@ enum {
 	causeStorePageFault   = 15,
 };
 
+// physical memory protection
+enum {
+	pmpR = 0,
+	pmpW = 1,
+	pmpX = 2,
+};
+
+enum {
+	// naturally aligned power of two
+	pmpMatchNapot = 3 << 3,
+};
+
 enum {
 	pageSize = 4096,
 	pageBits = 12,
@@ -167,12 +179,12 @@ struct SatpReg {
 	SatpReg(uint64 val): val(val) {}
 };
 
-static B_ALWAYS_INLINE uint64 PhysAdrPte(uint64 physAdr, uint32 level)
+static B_ALWAYS_INLINE uint64 VirtAdrPte(uint64 physAdr, uint32 level)
 {
 	return (physAdr >> (pageBits + pteIdxBits*level)) % (1 << pteIdxBits);
 }
 
-static B_ALWAYS_INLINE uint64 PhysAdrOfs(uint64 physAdr)
+static B_ALWAYS_INLINE uint64 VirtAdrOfs(uint64 physAdr)
 {
 	return physAdr % pageSize;
 }
@@ -246,7 +258,7 @@ static B_ALWAYS_INLINE void SetStvec(uint64 x) {
 static B_ALWAYS_INLINE uint64 Satp() {
 	uint64 x; asm volatile("csrr %0, satp" : "=r" (x)); return x;}
 static B_ALWAYS_INLINE void SetSatp(uint64 x) {
-	asm volatile("csrw satp, %0" : : "r" (x));}
+	asm volatile("csrw satp, %0" : : "r" (x) : "memory");}
 
 // scratch register
 static B_ALWAYS_INLINE uint64 Mscratch() {
@@ -284,18 +296,34 @@ static B_ALWAYS_INLINE uint64 Mcounteren() {
 static B_ALWAYS_INLINE void SetMcounteren(uint64 x) {
 	asm volatile("csrw mcounteren, %0" : : "r" (x));}
 
-// machine-mode cycle counter
-static B_ALWAYS_INLINE uint64 Mcycle() {
+// cycle counter
+static B_ALWAYS_INLINE uint64 CpuMcycle() {
 	uint64 x; asm volatile("csrr %0, mcycle" : "=r" (x)); return x;}
+static B_ALWAYS_INLINE uint64 CpuCycle() {
+	uint64 x; asm volatile("csrr %0, cycle" : "=r" (x)); return x;}
 // monotonic timer
 static B_ALWAYS_INLINE uint64 CpuTime() {
 	uint64 x; asm volatile("csrr %0, time" : "=r" (x)); return x;}
 
+// physical memory protection
+static B_ALWAYS_INLINE uint64 Pmpaddr0() {
+	uint64 x; asm volatile("csrr %0, pmpaddr0" : "=r" (x)); return x;}
+static B_ALWAYS_INLINE uint64 Pmpcfg0() {
+	uint64 x; asm volatile("csrr %0, pmpcfg0" : "=r" (x)); return x;}
+static B_ALWAYS_INLINE void SetPmpaddr0(uint64 x) {
+	asm volatile("csrw pmpaddr0, %0" : : "r" (x));}
+static B_ALWAYS_INLINE void SetPmpcfg0(uint64 x) {
+	asm volatile("csrw pmpcfg0, %0" : : "r" (x));}
+
 // flush the TLB
 static B_ALWAYS_INLINE void FlushTlbAll() {
 	asm volatile("sfence.vma" : : : "memory");}
 static B_ALWAYS_INLINE void FlushTlbPage(uint64 x) {
 	asm volatile("sfence.vma %0" : : "r" (x) : "memory");}
+static B_ALWAYS_INLINE void FlushTlbAllAsid(uint64 asid) {
+	asm volatile("sfence.vma x0, %0" : : "r" (asid) : "memory");}
+static B_ALWAYS_INLINE void FlushTlbPageAsid(uint64 page, uint64 asid) {
+	asm volatile("sfence.vma %0, %0" : : "r" (page), "r" (asid) : "memory");}
 
 static B_ALWAYS_INLINE uint64 Sp() {
 	uint64 x; asm volatile("mv %0, sp" : "=r" (x)); return x;}